ARM: S5P64X0: Add Power Management support

Add suspend-to-ram support for SMDK6440/50

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

4 files changed, 168 insertions, 0 deletions

diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index c5ef50c26291..4d3ac8a3709d 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -88,5 +88,6 @@
 #define S5P_PA_UART5            S5P6450_PA_UART(5)
 
 #define S5P_SZ_UART             SZ_256
+#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
new file mode 100644
index 000000000000..e52f7545d3aa
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
@@ -0,0 +1,117 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
+ *
+ * Based on PM core support for S3C64XX by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/regs-gpio.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+        u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
+
+        /*
+         * As a note, since the S5P64X0 UARTs generally have multiple
+         * clock sources, we simply enable PCLK at the moment and hope
+         * that the resume settings for the UART are suitable for the
+         * use with PCLK.
+         */
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART0;
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART1;
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART2;
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART3;
+
+        __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
+        udelay(10);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+        /* VIC should have already been taken care of */
+
+        /* clear any pending EINT0 interrupts */
+        __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void) { }
+static inline void s3c_pm_arch_show_resume_irqs(void) { }
+
+/*
+ * make these defines, we currently do not have any need to change
+ * the IRQ wake controls depending on the CPU we are running on
+ */
+#define s3c_irqwake_eintallow   ((1 << 16) - 1)
+#define s3c_irqwake_intallow    (~0)
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                        struct pm_uart_save *save)
+{
+        u32 ucon = __raw_readl(regs + S3C2410_UCON);
+        u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
+        u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
+        u32 new_ucon;
+        u32 delta;
+
+        /*
+         * S5P64X0 UART blocks only support level interrupts, so ensure that
+         * when we restore unused UART blocks we force the level interrupt
+         * settings.
+         */
+        save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
+
+        /*
+         * We have a constraint on changing the clock type of the UART
+         * between UCLKx and PCLK, so ensure that when we restore UCON
+         * that the CLK field is correctly modified if the bootloader
+         * has changed anything.
+         */
+        if (ucon_clk != save_clk) {
+                new_ucon = save->ucon;
+                delta = ucon_clk ^ save_clk;
+
+                /*
+                 * change from UCLKx => wrong PCLK,
+                 * either UCLK can be tested for by a bit-test
+                 * with UCLK0
+                 */
+                if (ucon_clk & S3C6400_UCON_UCLK0 &&
+                !(save_clk & S3C6400_UCON_UCLK0) &&
+                delta & S3C6400_UCON_PCLK2) {
+                        new_ucon &= ~S3C6400_UCON_UCLK0;
+                } else if (delta == S3C6400_UCON_PCLK2) {
+                        /*
+                         * as a precaution, don't change from
+                         * PCLK2 => PCLK or vice-versa
+                         */
+                        new_ucon ^= S3C6400_UCON_PCLK2;
+                }
+
+                S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
+                        ucon, new_ucon, save->ucon);
+                save->ucon = new_ucon;
+        }
+}
+
+static inline void s3c_pm_restored_gpios(void)
+{
+        /* ensure sleep mode has been cleared from the system */
+        __raw_writel(0, S5P64X0_SLPEN);
+}
+
+static inline void samsung_pm_saved_gpios(void)
+{
+        /*
+         * turn on the sleep mode and keep it there, as it seems that during
+         * suspend the xCON registers get re-set and thus you can end up with
+         * problems between going to sleep and resuming.
+         */
+        __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
+}
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
index a133f22fa155..bd91112c813c 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -41,17 +41,50 @@
 #define S5P6450_DPLL_CON                S5P_CLKREG(0x50)
 #define S5P6450_DPLL_CON_K              S5P_CLKREG(0x54)
 
+#define S5P64X0_AHB_CON0                S5P_CLKREG(0x100)
 #define S5P64X0_CLK_SRC1                S5P_CLKREG(0x10C)
 
 #define S5P64X0_SYS_ID                  S5P_CLKREG(0x118)
 #define S5P64X0_SYS_OTHERS              S5P_CLKREG(0x11C)
 
 #define S5P64X0_PWR_CFG                 S5P_CLKREG(0x804)
+#define S5P64X0_EINT_WAKEUP_MASK        S5P_CLKREG(0x808)
+#define S5P64X0_SLEEP_CFG               S5P_CLKREG(0x818)
+#define S5P64X0_PWR_STABLE              S5P_CLKREG(0x828)
+
 #define S5P64X0_OTHERS                  S5P_CLKREG(0x900)
+#define S5P64X0_WAKEUP_STAT             S5P_CLKREG(0x908)
+
+#define S5P64X0_INFORM0                 S5P_CLKREG(0xA00)
 
 #define S5P64X0_CLKDIV0_HCLK_SHIFT      (8)
 #define S5P64X0_CLKDIV0_HCLK_MASK       (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
 
+/* HCLK GATE Registers */
+#define S5P64X0_CLK_GATE_HCLK1_FIMGVG   (1 << 2)
+#define S5P64X0_CLK_GATE_SCLK1_FIMGVG   (1 << 2)
+
+/* PCLK GATE Registers */
+#define S5P64X0_CLK_GATE_PCLK_UART3     (1 << 4)
+#define S5P64X0_CLK_GATE_PCLK_UART2     (1 << 3)
+#define S5P64X0_CLK_GATE_PCLK_UART1     (1 << 2)
+#define S5P64X0_CLK_GATE_PCLK_UART0     (1 << 1)
+
+#define S5P64X0_PWR_CFG_MMC1_DISABLE            (1 << 15)
+#define S5P64X0_PWR_CFG_MMC0_DISABLE            (1 << 14)
+#define S5P64X0_PWR_CFG_RTC_TICK_DISABLE        (1 << 11)
+#define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE        (1 << 10)
+#define S5P64X0_PWR_CFG_WFI_MASK                (3 << 5)
+#define S5P64X0_PWR_CFG_WFI_SLEEP               (3 << 5)
+
+#define S5P64X0_SLEEP_CFG_OSC_EN        (1 << 0)
+
+#define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0)
+
+#define S5P6450_OTHERS_DISABLE_INT      (1 << 31)
+#define S5P64X0_OTHERS_RET_UART         (1 << 26)
+#define S5P64X0_OTHERS_RET_MMC1         (1 << 25)
+#define S5P64X0_OTHERS_RET_MMC0         (1 << 24)
 #define S5P64X0_OTHERS_USB_SIG_MASK     (1 << 16)
 
 /* Compatibility defines */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 88269ec70a38..cfdfa4fdadf2 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -37,15 +37,32 @@
 #define S5P64X0_SPCON0                  (S5P_VA_GPIO + 0x1A0)
 #define S5P64X0_SPCON0_LCD_SEL_MASK     (0x3 << 0)
 #define S5P64X0_SPCON0_LCD_SEL_RGB      (0x1 << 0)
+#define S5P64X0_SPCON1                  (S5P_VA_GPIO + 0x2B0)
+
+#define S5P64X0_MEM0CONSLP0             (S5P_VA_GPIO + 0x1C0)
+#define S5P64X0_MEM0CONSLP1             (S5P_VA_GPIO + 0x1C4)
+#define S5P64X0_MEM0DRVCON              (S5P_VA_GPIO + 0x1D0)
+#define S5P64X0_MEM1DRVCON              (S5P_VA_GPIO + 0x1D4)
+
+#define S5P64X0_EINT12CON               (S5P_VA_GPIO + 0x200)
+#define S5P64X0_EINT12FLTCON            (S5P_VA_GPIO + 0x220)
+#define S5P64X0_EINT12MASK              (S5P_VA_GPIO + 0x240)
 
 /* External interrupt control registers for group0 */
 
 #define EINT0CON0_OFFSET                (0x900)
+#define EINT0FLTCON0_OFFSET             (0x910)
+#define EINT0FLTCON1_OFFSET             (0x914)
 #define EINT0MASK_OFFSET                (0x920)
 #define EINT0PEND_OFFSET                (0x924)
 
 #define S5P64X0_EINT0CON0               (S5P_VA_GPIO + EINT0CON0_OFFSET)
+#define S5P64X0_EINT0FLTCON0            (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
+#define S5P64X0_EINT0FLTCON1            (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
 #define S5P64X0_EINT0MASK               (S5P_VA_GPIO + EINT0MASK_OFFSET)
 #define S5P64X0_EINT0PEND               (S5P_VA_GPIO + EINT0PEND_OFFSET)
 
+#define S5P64X0_SLPEN                   (S5P_VA_GPIO + 0x930)
+#define S5P64X0_SLPEN_USE_xSLP          (1 << 0)
+
 #endif /* __ASM_ARCH_REGS_GPIO_H */