ARM: S5P64X0: Update Clock for S5P6440 and S5P6450

This patch updates regarding clock files for supporting S5P6440 and
S5P6450 with one kernel image. The mach-s5p64x0/clock.c is for common
of them and there are specific clock files for each SoCs.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

2 files changed, 109 insertions, 0 deletions

diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
new file mode 100644
index 000000000000..58e1bc813804
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -0,0 +1,63 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_CLKREG(x)                   (S3C_VA_SYS + (x))
+
+#define S5P64X0_APLL_CON                S5P_CLKREG(0x0C)
+#define S5P64X0_MPLL_CON                S5P_CLKREG(0x10)
+#define S5P64X0_EPLL_CON                S5P_CLKREG(0x14)
+#define S5P64X0_EPLL_CON_K              S5P_CLKREG(0x18)
+
+#define S5P64X0_CLK_SRC0                S5P_CLKREG(0x1C)
+
+#define S5P64X0_CLK_DIV0                S5P_CLKREG(0x20)
+#define S5P64X0_CLK_DIV1                S5P_CLKREG(0x24)
+#define S5P64X0_CLK_DIV2                S5P_CLKREG(0x28)
+
+#define S5P64X0_CLK_GATE_HCLK0          S5P_CLKREG(0x30)
+#define S5P64X0_CLK_GATE_PCLK           S5P_CLKREG(0x34)
+#define S5P64X0_CLK_GATE_SCLK0          S5P_CLKREG(0x38)
+#define S5P64X0_CLK_GATE_MEM0           S5P_CLKREG(0x3C)
+
+#define S5P64X0_CLK_DIV3                S5P_CLKREG(0x40)
+
+#define S5P64X0_CLK_GATE_HCLK1          S5P_CLKREG(0x44)
+#define S5P64X0_CLK_GATE_SCLK1          S5P_CLKREG(0x48)
+
+#define S5P6450_DPLL_CON                S5P_CLKREG(0x50)
+#define S5P6450_DPLL_CON_K              S5P_CLKREG(0x54)
+
+#define S5P64X0_CLK_SRC1                S5P_CLKREG(0x10C)
+
+#define S5P64X0_SYS_ID                  S5P_CLKREG(0x118)
+#define S5P64X0_SYS_OTHERS              S5P_CLKREG(0x11C)
+
+#define S5P64X0_PWR_CFG                 S5P_CLKREG(0x804)
+#define S5P64X0_OTHERS                  S5P_CLKREG(0x900)
+
+#define S5P64X0_CLKDIV0_HCLK_SHIFT      (8)
+#define S5P64X0_CLKDIV0_HCLK_MASK       (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
+
+#define S5P64X0_OTHERS_USB_SIG_MASK     (1 << 16)
+
+/* Compatibility defines */
+
+#define ARM_CLK_DIV                     S5P64X0_CLK_DIV0
+#define ARM_DIV_RATIO_SHIFT             0
+#define ARM_DIV_MASK                    (0xF << ARM_DIV_RATIO_SHIFT)
+
+#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
new file mode 100644
index 000000000000..ff85b4b6e8d9
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
@@ -0,0 +1,46 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for s5p64x0 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clksrc_clk clk_mout_apll;
+extern struct clksrc_clk clk_mout_mpll;
+extern struct clksrc_clk clk_mout_epll;
+
+extern int s5p64x0_epll_enable(struct clk *clk, int enable);
+extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
+
+extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
+extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
+extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
+
+extern struct clk_ops s5p64x0_clkarm_ops;
+
+extern struct clksrc_clk clk_armclk;
+extern struct clksrc_clk clk_dout_mpll;
+
+extern struct clk *clkset_hclk_low_list[];
+extern struct clksrc_sources clkset_hclk_low;
+
+extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
+
+extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */