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authorBoojin Kim <boojin.kim@samsung.com>2011-09-01 20:44:39 -0400
committerVinod Koul <vinod.koul@intel.com>2011-09-14 01:40:03 -0400
commit3091e61173211de3fbd9bcb99ddc33333377fcb7 (patch)
tree66c27156e48119d1520bf5aad7502c9d7a56064e /arch/arm/mach-s5p64x0/dma.c
parenta422bd0f6d50bcb9c529d890bde70295915bb3e9 (diff)
ARM: S5P64X0: Use generic DMA PL330 driver
This patch makes Samsung S5P64X0 to use DMA PL330 driver on DMADEVICE. The S5P64X0 uses DMA generic APIs instead of SAMSUNG specific S3C-PL330 APIs. Signed-off-by: Boojin Kim <boojin.kim@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'arch/arm/mach-s5p64x0/dma.c')
-rw-r--r--arch/arm/mach-s5p64x0/dma.c273
1 files changed, 182 insertions, 91 deletions
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index d7ad944b3475..aebf3fcb1ebe 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -21,128 +21,219 @@
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22*/ 22*/
23 23
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h> 24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
27
28#include <asm/irq.h>
26 29
27#include <mach/map.h> 30#include <mach/map.h>
28#include <mach/irqs.h> 31#include <mach/irqs.h>
29#include <mach/regs-clock.h> 32#include <mach/regs-clock.h>
33#include <mach/dma.h>
30 34
31#include <plat/devs.h> 35#include <plat/devs.h>
32#include <plat/s3c-pl330-pdata.h> 36#include <plat/irqs.h>
33 37
34static u64 dma_dmamask = DMA_BIT_MASK(32); 38static u64 dma_dmamask = DMA_BIT_MASK(32);
35 39
36static struct resource s5p64x0_pdma_resource[] = { 40struct dma_pl330_peri s5p6440_pdma_peri[22] = {
37 [0] = { 41 {
38 .start = S5P64X0_PA_PDMA, 42 .peri_id = (u8)DMACH_UART0_RX,
39 .end = S5P64X0_PA_PDMA + SZ_4K, 43 .rqtype = DEVTOMEM,
40 .flags = IORESOURCE_MEM, 44 }, {
41 }, 45 .peri_id = (u8)DMACH_UART0_TX,
42 [1] = { 46 .rqtype = MEMTODEV,
43 .start = IRQ_DMA0, 47 }, {
44 .end = IRQ_DMA0, 48 .peri_id = (u8)DMACH_UART1_RX,
45 .flags = IORESOURCE_IRQ, 49 .rqtype = DEVTOMEM,
50 }, {
51 .peri_id = (u8)DMACH_UART1_TX,
52 .rqtype = MEMTODEV,
53 }, {
54 .peri_id = (u8)DMACH_UART2_RX,
55 .rqtype = DEVTOMEM,
56 }, {
57 .peri_id = (u8)DMACH_UART2_TX,
58 .rqtype = MEMTODEV,
59 }, {
60 .peri_id = (u8)DMACH_UART3_RX,
61 .rqtype = DEVTOMEM,
62 }, {
63 .peri_id = (u8)DMACH_UART3_TX,
64 .rqtype = MEMTODEV,
65 }, {
66 .peri_id = DMACH_MAX,
67 }, {
68 .peri_id = DMACH_MAX,
69 }, {
70 .peri_id = (u8)DMACH_PCM0_TX,
71 .rqtype = MEMTODEV,
72 }, {
73 .peri_id = (u8)DMACH_PCM0_RX,
74 .rqtype = DEVTOMEM,
75 }, {
76 .peri_id = (u8)DMACH_I2S0_TX,
77 .rqtype = MEMTODEV,
78 }, {
79 .peri_id = (u8)DMACH_I2S0_RX,
80 .rqtype = DEVTOMEM,
81 }, {
82 .peri_id = (u8)DMACH_SPI0_TX,
83 .rqtype = MEMTODEV,
84 }, {
85 .peri_id = (u8)DMACH_SPI0_RX,
86 .rqtype = DEVTOMEM,
87 }, {
88 .peri_id = (u8)DMACH_MAX,
89 }, {
90 .peri_id = (u8)DMACH_MAX,
91 }, {
92 .peri_id = (u8)DMACH_MAX,
93 }, {
94 .peri_id = (u8)DMACH_MAX,
95 }, {
96 .peri_id = (u8)DMACH_SPI1_TX,
97 .rqtype = MEMTODEV,
98 }, {
99 .peri_id = (u8)DMACH_SPI1_RX,
100 .rqtype = DEVTOMEM,
46 }, 101 },
47}; 102};
48 103
49static struct s3c_pl330_platdata s5p6440_pdma_pdata = { 104struct dma_pl330_platdata s5p6440_pdma_pdata = {
50 .peri = { 105 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
51 [0] = DMACH_UART0_RX, 106 .peri = s5p6440_pdma_peri,
52 [1] = DMACH_UART0_TX,
53 [2] = DMACH_UART1_RX,
54 [3] = DMACH_UART1_TX,
55 [4] = DMACH_UART2_RX,
56 [5] = DMACH_UART2_TX,
57 [6] = DMACH_UART3_RX,
58 [7] = DMACH_UART3_TX,
59 [8] = DMACH_MAX,
60 [9] = DMACH_MAX,
61 [10] = DMACH_PCM0_TX,
62 [11] = DMACH_PCM0_RX,
63 [12] = DMACH_I2S0_TX,
64 [13] = DMACH_I2S0_RX,
65 [14] = DMACH_SPI0_TX,
66 [15] = DMACH_SPI0_RX,
67 [16] = DMACH_MAX,
68 [17] = DMACH_MAX,
69 [18] = DMACH_MAX,
70 [19] = DMACH_MAX,
71 [20] = DMACH_SPI1_TX,
72 [21] = DMACH_SPI1_RX,
73 [22] = DMACH_MAX,
74 [23] = DMACH_MAX,
75 [24] = DMACH_MAX,
76 [25] = DMACH_MAX,
77 [26] = DMACH_MAX,
78 [27] = DMACH_MAX,
79 [28] = DMACH_MAX,
80 [29] = DMACH_PWM,
81 [30] = DMACH_MAX,
82 [31] = DMACH_MAX,
83 },
84}; 107};
85 108
86static struct s3c_pl330_platdata s5p6450_pdma_pdata = { 109struct dma_pl330_peri s5p6450_pdma_peri[32] = {
87 .peri = { 110 {
88 [0] = DMACH_UART0_RX, 111 .peri_id = (u8)DMACH_UART0_RX,
89 [1] = DMACH_UART0_TX, 112 .rqtype = DEVTOMEM,
90 [2] = DMACH_UART1_RX, 113 }, {
91 [3] = DMACH_UART1_TX, 114 .peri_id = (u8)DMACH_UART0_TX,
92 [4] = DMACH_UART2_RX, 115 .rqtype = MEMTODEV,
93 [5] = DMACH_UART2_TX, 116 }, {
94 [6] = DMACH_UART3_RX, 117 .peri_id = (u8)DMACH_UART1_RX,
95 [7] = DMACH_UART3_TX, 118 .rqtype = DEVTOMEM,
96 [8] = DMACH_UART4_RX, 119 }, {
97 [9] = DMACH_UART4_TX, 120 .peri_id = (u8)DMACH_UART1_TX,
98 [10] = DMACH_PCM0_TX, 121 .rqtype = MEMTODEV,
99 [11] = DMACH_PCM0_RX, 122 }, {
100 [12] = DMACH_I2S0_TX, 123 .peri_id = (u8)DMACH_UART2_RX,
101 [13] = DMACH_I2S0_RX, 124 .rqtype = DEVTOMEM,
102 [14] = DMACH_SPI0_TX, 125 }, {
103 [15] = DMACH_SPI0_RX, 126 .peri_id = (u8)DMACH_UART2_TX,
104 [16] = DMACH_PCM1_TX, 127 .rqtype = MEMTODEV,
105 [17] = DMACH_PCM1_RX, 128 }, {
106 [18] = DMACH_PCM2_TX, 129 .peri_id = (u8)DMACH_UART3_RX,
107 [19] = DMACH_PCM2_RX, 130 .rqtype = DEVTOMEM,
108 [20] = DMACH_SPI1_TX, 131 }, {
109 [21] = DMACH_SPI1_RX, 132 .peri_id = (u8)DMACH_UART3_TX,
110 [22] = DMACH_USI_TX, 133 .rqtype = MEMTODEV,
111 [23] = DMACH_USI_RX, 134 }, {
112 [24] = DMACH_MAX, 135 .peri_id = (u8)DMACH_UART4_RX,
113 [25] = DMACH_I2S1_TX, 136 .rqtype = DEVTOMEM,
114 [26] = DMACH_I2S1_RX, 137 }, {
115 [27] = DMACH_I2S2_TX, 138 .peri_id = (u8)DMACH_UART4_TX,
116 [28] = DMACH_I2S2_RX, 139 .rqtype = MEMTODEV,
117 [29] = DMACH_PWM, 140 }, {
118 [30] = DMACH_UART5_RX, 141 .peri_id = (u8)DMACH_PCM0_TX,
119 [31] = DMACH_UART5_TX, 142 .rqtype = MEMTODEV,
143 }, {
144 .peri_id = (u8)DMACH_PCM0_RX,
145 .rqtype = DEVTOMEM,
146 }, {
147 .peri_id = (u8)DMACH_I2S0_TX,
148 .rqtype = MEMTODEV,
149 }, {
150 .peri_id = (u8)DMACH_I2S0_RX,
151 .rqtype = DEVTOMEM,
152 }, {
153 .peri_id = (u8)DMACH_SPI0_TX,
154 .rqtype = MEMTODEV,
155 }, {
156 .peri_id = (u8)DMACH_SPI0_RX,
157 .rqtype = DEVTOMEM,
158 }, {
159 .peri_id = (u8)DMACH_PCM1_TX,
160 .rqtype = MEMTODEV,
161 }, {
162 .peri_id = (u8)DMACH_PCM1_RX,
163 .rqtype = DEVTOMEM,
164 }, {
165 .peri_id = (u8)DMACH_PCM2_TX,
166 .rqtype = MEMTODEV,
167 }, {
168 .peri_id = (u8)DMACH_PCM2_RX,
169 .rqtype = DEVTOMEM,
170 }, {
171 .peri_id = (u8)DMACH_SPI1_TX,
172 .rqtype = MEMTODEV,
173 }, {
174 .peri_id = (u8)DMACH_SPI1_RX,
175 .rqtype = DEVTOMEM,
176 }, {
177 .peri_id = (u8)DMACH_USI_TX,
178 .rqtype = MEMTODEV,
179 }, {
180 .peri_id = (u8)DMACH_USI_RX,
181 .rqtype = DEVTOMEM,
182 }, {
183 .peri_id = (u8)DMACH_MAX,
184 }, {
185 .peri_id = (u8)DMACH_I2S1_TX,
186 .rqtype = MEMTODEV,
187 }, {
188 .peri_id = (u8)DMACH_I2S1_RX,
189 .rqtype = DEVTOMEM,
190 }, {
191 .peri_id = (u8)DMACH_I2S2_TX,
192 .rqtype = MEMTODEV,
193 }, {
194 .peri_id = (u8)DMACH_I2S2_RX,
195 .rqtype = DEVTOMEM,
196 }, {
197 .peri_id = (u8)DMACH_PWM,
198 }, {
199 .peri_id = (u8)DMACH_UART5_RX,
200 .rqtype = DEVTOMEM,
201 }, {
202 .peri_id = (u8)DMACH_UART5_TX,
203 .rqtype = MEMTODEV,
120 }, 204 },
121}; 205};
122 206
123static struct platform_device s5p64x0_device_pdma = { 207struct dma_pl330_platdata s5p6450_pdma_pdata = {
124 .name = "s3c-pl330", 208 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
125 .id = -1, 209 .peri = s5p6450_pdma_peri,
126 .num_resources = ARRAY_SIZE(s5p64x0_pdma_resource), 210};
127 .resource = s5p64x0_pdma_resource, 211
128 .dev = { 212struct amba_device s5p64x0_device_pdma = {
213 .dev = {
214 .init_name = "dma-pl330",
129 .dma_mask = &dma_dmamask, 215 .dma_mask = &dma_dmamask,
130 .coherent_dma_mask = DMA_BIT_MASK(32), 216 .coherent_dma_mask = DMA_BIT_MASK(32),
131 }, 217 },
218 .res = {
219 .start = S5P64X0_PA_PDMA,
220 .end = S5P64X0_PA_PDMA + SZ_4K,
221 .flags = IORESOURCE_MEM,
222 },
223 .irq = {IRQ_DMA0, NO_IRQ},
224 .periphid = 0x00041330,
132}; 225};
133 226
134static int __init s5p64x0_dma_init(void) 227static int __init s5p64x0_dma_init(void)
135{ 228{
136 unsigned int id; 229 unsigned int id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
137
138 id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
139 230
140 if (id == 0x50000) 231 if (id == 0x50000)
141 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; 232 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
142 else 233 else
143 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; 234 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
144 235
145 platform_device_register(&s5p64x0_device_pdma); 236 amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
146 237
147 return 0; 238 return 0;
148} 239}
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