diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2012-01-20 21:29:30 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-01-20 23:06:10 -0500 |
commit | 15545026ad615e15bd9457941a66c8a6d5387fe4 (patch) | |
tree | fa42257d3a5ca35a9c3291516a7b45f8709334f1 /arch/arm/mach-s5p64x0/clock.c | |
parent | 5086c6c882a392d2f48704c0a03e17bdcbf01e8f (diff) |
ARM: S5P64X0: use static declaration when it is not used in other files
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5p64x0/clock.c')
-rw-r--r-- | arch/arm/mach-s5p64x0/clock.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c index 241d0e645c85..57e718957ef3 100644 --- a/arch/arm/mach-s5p64x0/clock.c +++ b/arch/arm/mach-s5p64x0/clock.c | |||
@@ -73,7 +73,7 @@ static const u32 clock_table[][3] = { | |||
73 | {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, | 73 | {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, |
74 | }; | 74 | }; |
75 | 75 | ||
76 | unsigned long s5p64x0_armclk_get_rate(struct clk *clk) | 76 | static unsigned long s5p64x0_armclk_get_rate(struct clk *clk) |
77 | { | 77 | { |
78 | unsigned long rate = clk_get_rate(clk->parent); | 78 | unsigned long rate = clk_get_rate(clk->parent); |
79 | u32 clkdiv; | 79 | u32 clkdiv; |
@@ -84,7 +84,8 @@ unsigned long s5p64x0_armclk_get_rate(struct clk *clk) | |||
84 | return rate / (clkdiv + 1); | 84 | return rate / (clkdiv + 1); |
85 | } | 85 | } |
86 | 86 | ||
87 | unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate) | 87 | static unsigned long s5p64x0_armclk_round_rate(struct clk *clk, |
88 | unsigned long rate) | ||
88 | { | 89 | { |
89 | u32 iter; | 90 | u32 iter; |
90 | 91 | ||
@@ -96,7 +97,7 @@ unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate) | |||
96 | return clock_table[ARRAY_SIZE(clock_table) - 1][0]; | 97 | return clock_table[ARRAY_SIZE(clock_table) - 1][0]; |
97 | } | 98 | } |
98 | 99 | ||
99 | int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate) | 100 | static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate) |
100 | { | 101 | { |
101 | u32 round_tmp; | 102 | u32 round_tmp; |
102 | u32 iter; | 103 | u32 iter; |
@@ -148,7 +149,7 @@ int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate) | |||
148 | return 0; | 149 | return 0; |
149 | } | 150 | } |
150 | 151 | ||
151 | struct clk_ops s5p64x0_clkarm_ops = { | 152 | static struct clk_ops s5p64x0_clkarm_ops = { |
152 | .get_rate = s5p64x0_armclk_get_rate, | 153 | .get_rate = s5p64x0_armclk_get_rate, |
153 | .set_rate = s5p64x0_armclk_set_rate, | 154 | .set_rate = s5p64x0_armclk_set_rate, |
154 | .round_rate = s5p64x0_armclk_round_rate, | 155 | .round_rate = s5p64x0_armclk_round_rate, |
@@ -173,7 +174,7 @@ struct clksrc_clk clk_dout_mpll = { | |||
173 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 }, | 174 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 }, |
174 | }; | 175 | }; |
175 | 176 | ||
176 | struct clk *clkset_hclk_low_list[] = { | 177 | static struct clk *clkset_hclk_low_list[] = { |
177 | &clk_mout_apll.clk, | 178 | &clk_mout_apll.clk, |
178 | &clk_mout_mpll.clk, | 179 | &clk_mout_mpll.clk, |
179 | }; | 180 | }; |