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authorThomas Abraham <thomas.abraham@linaro.org>2012-07-12 18:15:14 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-07-13 02:23:46 -0400
commita5238e360b715e9a1bb39d7d3537f78cc9e9e286 (patch)
treeb6503a7429b93b7c15f90d5e3b0124a191215423 /arch/arm/mach-s5p64x0/clock-s5p6440.c
parent2b54be661191532ddf1628c3b151b81ae8743caa (diff)
spi: s3c64xx: move controller information into driver data
Platform data is used to specify controller hardware specific information such as the tx/rx fifo level mask and bit offset of rx fifo level. Such information is not suitable to be supplied from device tree. Instead, it can be moved into the driver data and removed from platform data. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5p64x0/clock-s5p6440.c')
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index ee1e8e7f5631..000445596ec4 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = {
227 .ctrlbit = (1 << 17), 227 .ctrlbit = (1 << 17),
228 }, { 228 }, {
229 .name = "spi", 229 .name = "spi",
230 .devname = "s3c64xx-spi.0", 230 .devname = "s5p64x0-spi.0",
231 .parent = &clk_pclk_low.clk, 231 .parent = &clk_pclk_low.clk,
232 .enable = s5p64x0_pclk_ctrl, 232 .enable = s5p64x0_pclk_ctrl,
233 .ctrlbit = (1 << 21), 233 .ctrlbit = (1 << 21),
234 }, { 234 }, {
235 .name = "spi", 235 .name = "spi",
236 .devname = "s3c64xx-spi.1", 236 .devname = "s5p64x0-spi.1",
237 .parent = &clk_pclk_low.clk, 237 .parent = &clk_pclk_low.clk,
238 .enable = s5p64x0_pclk_ctrl, 238 .enable = s5p64x0_pclk_ctrl,
239 .ctrlbit = (1 << 22), 239 .ctrlbit = (1 << 22),
@@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = {
467static struct clksrc_clk clk_sclk_spi0 = { 467static struct clksrc_clk clk_sclk_spi0 = {
468 .clk = { 468 .clk = {
469 .name = "sclk_spi", 469 .name = "sclk_spi",
470 .devname = "s3c64xx-spi.0", 470 .devname = "s5p64x0-spi.0",
471 .ctrlbit = (1 << 20), 471 .ctrlbit = (1 << 20),
472 .enable = s5p64x0_sclk_ctrl, 472 .enable = s5p64x0_sclk_ctrl,
473 }, 473 },
@@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
479static struct clksrc_clk clk_sclk_spi1 = { 479static struct clksrc_clk clk_sclk_spi1 = {
480 .clk = { 480 .clk = {
481 .name = "sclk_spi", 481 .name = "sclk_spi",
482 .devname = "s3c64xx-spi.1", 482 .devname = "s5p64x0-spi.1",
483 .ctrlbit = (1 << 21), 483 .ctrlbit = (1 << 21),
484 .enable = s5p64x0_sclk_ctrl, 484 .enable = s5p64x0_sclk_ctrl,
485 }, 485 },
@@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
519 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 519 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
520 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 520 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
521 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 521 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
522 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 522 CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
523 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 523 CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
524 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), 524 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
525 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 525 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
526 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 526 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),