diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2011-01-04 04:12:57 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-01-04 04:27:43 -0500 |
commit | 9f6bb3f5675a22fdcebb9565ec2122a2b2903aa2 (patch) | |
tree | e15654978c6aaa71bfcc9eb84fcb8f76e51bce0a /arch/arm/mach-s5p64x0/clock-s5p6440.c | |
parent | cdb216de6e3291493f6bd033f2eec49c80dc8015 (diff) |
ARM: S5P6440: Tidy register and disable clock usage
This patch changes the clock registration code to use the s3c_register_clocks()
followed by s3c_disable_clocks() instead of the loops it was using.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5p64x0/clock-s5p6440.c')
-rw-r--r-- | arch/arm/mach-s5p64x0/clock-s5p6440.c | 16 |
1 files changed, 3 insertions, 13 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index e4883dc1c8d7..3d54ac4bc16c 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c | |||
@@ -133,7 +133,7 @@ static struct clksrc_clk clk_pclk_low = { | |||
133 | * recommended to keep the following clocks disabled until the driver requests | 133 | * recommended to keep the following clocks disabled until the driver requests |
134 | * for enabling the clock. | 134 | * for enabling the clock. |
135 | */ | 135 | */ |
136 | static struct clk init_clocks_disable[] = { | 136 | static struct clk init_clocks_off[] = { |
137 | { | 137 | { |
138 | .name = "nand", | 138 | .name = "nand", |
139 | .id = -1, | 139 | .id = -1, |
@@ -602,8 +602,6 @@ static struct clk *clks[] __initdata = { | |||
602 | 602 | ||
603 | void __init s5p6440_register_clocks(void) | 603 | void __init s5p6440_register_clocks(void) |
604 | { | 604 | { |
605 | struct clk *clkp; | ||
606 | int ret; | ||
607 | int ptr; | 605 | int ptr; |
608 | 606 | ||
609 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | 607 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
@@ -614,16 +612,8 @@ void __init s5p6440_register_clocks(void) | |||
614 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | 612 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); |
615 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | 613 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); |
616 | 614 | ||
617 | clkp = init_clocks_disable; | 615 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
618 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | 616 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
619 | |||
620 | ret = s3c24xx_register_clock(clkp); | ||
621 | if (ret < 0) { | ||
622 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
623 | clkp->name, ret); | ||
624 | } | ||
625 | (clkp->enable)(clkp, 0); | ||
626 | } | ||
627 | 617 | ||
628 | s3c_pwmclk_init(); | 618 | s3c_pwmclk_init(); |
629 | } | 619 | } |