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authorKukjin Kim <kgene.kim@samsung.com>2011-01-04 19:39:23 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-01-04 19:39:23 -0500
commitab10f1dd914ad87e0370bd8b82f77dcd32b6d941 (patch)
tree3879eaf6d7ede69d2757a5db2bf0de5e6bd3c367 /arch/arm/mach-s5p6442
parentf56d463423b825ff5bf4b63e0dc443557934165c (diff)
parent957c461e82f7a8ddcd7fb25c01c43917f64fde33 (diff)
Merge branch 'dev/cleanup-clocks' into for-next
Diffstat (limited to 'arch/arm/mach-s5p6442')
-rw-r--r--arch/arm/mach-s5p6442/clock.c16
1 files changed, 3 insertions, 13 deletions
diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c
index 16d6e7e61b50..fbbc7bede685 100644
--- a/arch/arm/mach-s5p6442/clock.c
+++ b/arch/arm/mach-s5p6442/clock.c
@@ -340,7 +340,7 @@ void __init_or_cpufreq s5p6442_setup_clocks(void)
340 clk_pclkd1.rate = pclkd1; 340 clk_pclkd1.rate = pclkd1;
341} 341}
342 342
343static struct clk init_clocks_disable[] = { 343static struct clk init_clocks_off[] = {
344 { 344 {
345 .name = "pdma", 345 .name = "pdma",
346 .id = -1, 346 .id = -1,
@@ -408,23 +408,13 @@ static struct clk *clks[] __initdata = {
408 408
409void __init s5p6442_register_clocks(void) 409void __init s5p6442_register_clocks(void)
410{ 410{
411 struct clk *clkptr;
412 int i, ret;
413
414 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); 411 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
415 412
416 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 413 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
417 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 414 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
418 415
419 clkptr = init_clocks_disable; 416 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
420 for (i = 0; i < ARRAY_SIZE(init_clocks_disable); i++, clkptr++) { 417 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
421 ret = s3c24xx_register_clock(clkptr);
422 if (ret < 0) {
423 printk(KERN_ERR "Fail to register clock %s (%d)\n",
424 clkptr->name, ret);
425 } else
426 (clkptr->enable)(clkptr, 0);
427 }
428 418
429 s3c_pwmclk_init(); 419 s3c_pwmclk_init();
430} 420}