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authorThomas Abraham <thomas.ab@samsung.com>2010-05-12 20:27:47 -0400
committerBen Dooks <ben-linux@fluff.org>2010-05-12 21:42:47 -0400
commit213907dc1b974019f5eb9c94a1c62b11a515564c (patch)
treeae203a57aa4895b597a0d1e2e2be6a3d959dd927 /arch/arm/mach-s5p6440/clock.c
parent697f8a9fe7835ba24f2da855c5de4ddbe27aa554 (diff)
ARM: S5P6440: Add clocks of type 'struct clk'.
Add definitions of clocks of type 'struct clk'. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s5p6440/clock.c')
-rw-r--r--arch/arm/mach-s5p6440/clock.c82
1 files changed, 80 insertions, 2 deletions
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
index 80d18f54ee70..26b02d43a252 100644
--- a/arch/arm/mach-s5p6440/clock.c
+++ b/arch/arm/mach-s5p6440/clock.c
@@ -467,7 +467,73 @@ static struct clk init_clocks_disable[] = {
467 .parent = &clk_pclk_low.clk, 467 .parent = &clk_pclk_low.clk,
468 .enable = s5p6440_pclk_ctrl, 468 .enable = s5p6440_pclk_ctrl,
469 .ctrlbit = S5P_CLKCON_PCLK_PWM, 469 .ctrlbit = S5P_CLKCON_PCLK_PWM,
470 } 470 }, {
471 .name = "hclk_fimgvg",
472 .id = -1,
473 .parent = &clk_hclk.clk,
474 .enable = s5p6440_hclk1_ctrl,
475 .ctrlbit = (1 << 2),
476 }, {
477 .name = "tsi",
478 .id = -1,
479 .parent = &clk_hclk_low.clk,
480 .enable = s5p6440_hclk1_ctrl,
481 .ctrlbit = (1 << 0),
482 }, {
483 .name = "pclk_fimgvg",
484 .id = -1,
485 .parent = &clk_pclk.clk,
486 .enable = s5p6440_pclk_ctrl,
487 .ctrlbit = (1 << 31),
488 }, {
489 .name = "dmc0",
490 .id = -1,
491 .parent = &clk_pclk.clk,
492 .enable = s5p6440_pclk_ctrl,
493 .ctrlbit = (1 << 30),
494 }, {
495 .name = "etm",
496 .id = -1,
497 .parent = &clk_pclk.clk,
498 .enable = s5p6440_pclk_ctrl,
499 .ctrlbit = (1 << 29),
500 }, {
501 .name = "dsim",
502 .id = -1,
503 .parent = &clk_pclk_low.clk,
504 .enable = s5p6440_pclk_ctrl,
505 .ctrlbit = (1 << 28),
506 }, {
507 .name = "gps",
508 .id = -1,
509 .parent = &clk_pclk_low.clk,
510 .enable = s5p6440_pclk_ctrl,
511 .ctrlbit = (1 << 25),
512 }, {
513 .name = "pcm",
514 .id = -1,
515 .parent = &clk_pclk_low.clk,
516 .enable = s5p6440_pclk_ctrl,
517 .ctrlbit = (1 << 8),
518 }, {
519 .name = "irom",
520 .id = -1,
521 .parent = &clk_hclk.clk,
522 .enable = s5p6440_hclk0_ctrl,
523 .ctrlbit = (1 << 25),
524 }, {
525 .name = "dma",
526 .id = -1,
527 .parent = &clk_hclk_low.clk,
528 .enable = s5p6440_hclk0_ctrl,
529 .ctrlbit = (1 << 12),
530 }, {
531 .name = "2d",
532 .id = -1,
533 .parent = &clk_hclk.clk,
534 .enable = s5p6440_hclk0_ctrl,
535 .ctrlbit = (1 << 8),
536 },
471}; 537};
472 538
473/* 539/*
@@ -504,7 +570,19 @@ static struct clk init_clocks[] = {
504 .parent = &clk_pclk_low.clk, 570 .parent = &clk_pclk_low.clk,
505 .enable = s5p6440_pclk_ctrl, 571 .enable = s5p6440_pclk_ctrl,
506 .ctrlbit = S5P_CLKCON_PCLK_UART3, 572 .ctrlbit = S5P_CLKCON_PCLK_UART3,
507 } 573 }, {
574 .name = "mem",
575 .id = -1,
576 .parent = &clk_hclk.clk,
577 .enable = s5p6440_hclk0_ctrl,
578 .ctrlbit = (1 << 21),
579 }, {
580 .name = "intc",
581 .id = -1,
582 .parent = &clk_hclk.clk,
583 .enable = s5p6440_hclk0_ctrl,
584 .ctrlbit = (1 << 1),
585 },
508}; 586};
509 587
510static struct clk clk_iis_cd_v40 = { 588static struct clk clk_iis_cd_v40 = {