Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Device tree conversions for samsung and tegra

Both platforms had some initial device tree support, but this adds
much more to actually make it usable.

* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (45 commits)
  ARM: dts: Add intial dts file for EXYNOS4210 SoC, SMDKV310 and ORIGEN
  ARM: EXYNOS: Add Exynos4 device tree enabled board file
  rtc: rtc-s3c: Add device tree support
  input: samsung-keypad: Add device tree support
  ARM: S5PV210: Modify platform data for pl330 driver
  ARM: S5PC100: Modify platform data for pl330 driver
  ARM: S5P64x0: Modify platform data for pl330 driver
  ARM: EXYNOS: Add a alias for pdma clocks
  ARM: EXYNOS: Limit usage of pl330 device instance to non-dt build
  ARM: SAMSUNG: Add device tree support for pl330 dma engine wrappers
  DMA: PL330: Add device tree support
  ARM: EXYNOS: Modify platform data for pl330 driver
  DMA: PL330: Infer transfer direction from transfer request instead of platform data
  DMA: PL330: move filter function into driver
  serial: samsung: Fix build for non-Exynos4210 devices
  serial: samsung: add device tree support
  serial: samsung: merge probe() function from all SoC specific extensions
  serial: samsung: merge all SoC specific port reset functions
  ARM: SAMSUNG: register uart clocks to clock lookup list
  serial: samsung: remove all uses of get_clksrc and set_clksrc
  ...

Fix up fairly trivial conflicts in arch/arm/mach-s3c2440/clock.c and
drivers/tty/serial/Kconfig both due to just adding code close to
changes.

1 files changed, 27 insertions, 10 deletions

diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 625219b9cefc..a3aafb6768c9 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -617,16 +617,6 @@ static struct clksrc_clk clksrcs[] = {
                 .sources        = &clkset_uhost,
         }, {
                 .clk    = {
-                        .name           = "uclk1",
-                        .ctrlbit        = S3C_CLKCON_SCLK_UART,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
-                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
-                .sources        = &clkset_uart,
-        }, {
-/* Where does UCLK0 come from? */
-                .clk    = {
                         .name           = "spi-bus",
                         .devname        = "s3c64xx-spi.0",
                         .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
@@ -695,6 +685,18 @@ static struct clksrc_clk clksrcs[] = {
         },
 };
 
+/* Where does UCLK0 come from? */
+static struct clksrc_clk clk_sclk_uclk = {
+        .clk    = {
+                .name           = "uclk1",
+                .ctrlbit        = S3C_CLKCON_SCLK_UART,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
+        .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
+        .sources        = &clkset_uart,
+};
+
 /* Clock initialisation code */
 
 static struct clksrc_clk *init_parents[] = {
@@ -703,6 +705,15 @@ static struct clksrc_clk *init_parents[] = {
         &clk_mout_mpll,
 };
 
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uclk,
+};
+
+static struct clk_lookup s3c64xx_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+};
+
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 
 void __init_or_cpufreq s3c64xx_setup_clocks(void)
@@ -811,6 +822,8 @@ static struct clk *clks[] __initdata = {
 void __init s3c64xx_register_clocks(unsigned long xtal, 
                                     unsigned armclk_divlimit)
 {
+        unsigned int cnt;
+
         armclk_mask = armclk_divlimit;
 
         s3c24xx_register_baseclocks(xtal);
@@ -823,5 +836,9 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
 
         s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
+                s3c_register_clksrc(clksrc_cdev[cnt], 1);
+        clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
+
         s3c_pwmclk_init();
 }