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authorKukjin Kim <kgene.kim@samsung.com>2011-10-04 07:18:36 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 07:18:36 -0400
commitdb3c94a7edc6b29f8d52ba5884dec6a15feeadad (patch)
treeac9207a44cecafb9104ca4e1f46aecb9fe01383d /arch/arm/mach-s3c64xx
parentc9477f38cba225870862fd9e08868ae3d4abdfe0 (diff)
parent568f0e278c6dd33dc11bd19c4ad781d1f8d86800 (diff)
Merge branch 'next-samsung-devel' into next-samsung-devel-2
Conflicts: arch/arm/mach-exynos4/clock.c arch/arm/mach-s3c2412/gpio.c arch/arm/mach-s5p64x0/dma.c arch/arm/mach-s5p64x0/gpiolib.c
Diffstat (limited to 'arch/arm/mach-s3c64xx')
-rw-r--r--arch/arm/mach-s3c64xx/Kconfig1
-rw-r--r--arch/arm/mach-s3c64xx/Makefile3
-rw-r--r--arch/arm/mach-s3c64xx/clock.c8
-rw-r--r--arch/arm/mach-s3c64xx/dma.c12
-rw-r--r--arch/arm/mach-s3c64xx/gpiolib.c290
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/crag6410.h23
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/dma.h8
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pm-core.h2
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-sys.h3
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410-module.c182
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c106
-rw-r--r--arch/arm/mach-s3c64xx/pm.c4
12 files changed, 260 insertions, 382 deletions
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index f057b6ae4f90..5552e048c2be 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -288,5 +288,6 @@ config MACH_WLF_CRAGG_6410
288 select S3C_DEV_RTC 288 select S3C_DEV_RTC
289 select S3C64XX_DEV_SPI 289 select S3C64XX_DEV_SPI
290 select S3C24XX_GPIO_EXTRA128 290 select S3C24XX_GPIO_EXTRA128
291 select I2C
291 help 292 help
292 Machine support for the Wolfson Cragganmore S3C6410 variant. 293 Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 61b4034a0c22..902ab9ace93b 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -13,7 +13,6 @@ obj- :=
13# Core files 13# Core files
14obj-y += cpu.o 14obj-y += cpu.o
15obj-y += clock.o 15obj-y += clock.o
16obj-y += gpiolib.o
17 16
18# Core support for S3C6400 system 17# Core support for S3C6400 system
19 18
@@ -55,7 +54,7 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o
55obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o 54obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
56obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o 55obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o
57obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o 56obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
58obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o 57obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
59 58
60# device support 59# device support
61 60
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 8cf39e33579e..872e68361eb4 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -744,7 +744,13 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
744 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", 744 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
745 apll, mpll, epll); 745 apll, mpll, epll);
746 746
747 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); 747 if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
748 /* Synchronous mode */
749 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
750 else
751 /* Asynchronous mode */
752 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
753
748 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); 754 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
749 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); 755 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
750 756
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 204bfafe4bfc..17d62f4f8204 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -147,14 +147,14 @@ static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
147 u32 control0, control1; 147 u32 control0, control1;
148 148
149 switch (chan->source) { 149 switch (chan->source) {
150 case S3C2410_DMASRC_HW: 150 case DMA_FROM_DEVICE:
151 src = chan->dev_addr; 151 src = chan->dev_addr;
152 dst = data; 152 dst = data;
153 control0 = PL080_CONTROL_SRC_AHB2; 153 control0 = PL080_CONTROL_SRC_AHB2;
154 control0 |= PL080_CONTROL_DST_INCR; 154 control0 |= PL080_CONTROL_DST_INCR;
155 break; 155 break;
156 156
157 case S3C2410_DMASRC_MEM: 157 case DMA_TO_DEVICE:
158 src = data; 158 src = data;
159 dst = chan->dev_addr; 159 dst = chan->dev_addr;
160 control0 = PL080_CONTROL_DST_AHB2; 160 control0 = PL080_CONTROL_DST_AHB2;
@@ -416,7 +416,7 @@ EXPORT_SYMBOL(s3c2410_dma_enqueue);
416 416
417 417
418int s3c2410_dma_devconfig(enum dma_ch channel, 418int s3c2410_dma_devconfig(enum dma_ch channel,
419 enum s3c2410_dmasrc source, 419 enum dma_data_direction source,
420 unsigned long devaddr) 420 unsigned long devaddr)
421{ 421{
422 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); 422 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
@@ -437,11 +437,11 @@ int s3c2410_dma_devconfig(enum dma_ch channel,
437 pr_debug("%s: peripheral %d\n", __func__, peripheral); 437 pr_debug("%s: peripheral %d\n", __func__, peripheral);
438 438
439 switch (source) { 439 switch (source) {
440 case S3C2410_DMASRC_HW: 440 case DMA_FROM_DEVICE:
441 config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT; 441 config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
442 config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT; 442 config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
443 break; 443 break;
444 case S3C2410_DMASRC_MEM: 444 case DMA_TO_DEVICE:
445 config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT; 445 config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
446 config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT; 446 config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
447 break; 447 break;
@@ -740,7 +740,7 @@ static int __init s3c64xx_dma_init(void)
740 } 740 }
741 741
742 /* Set all DMA configuration to be DMA, not SDMA */ 742 /* Set all DMA configuration to be DMA, not SDMA */
743 writel(0xffffff, S3C_SYSREG(0x110)); 743 writel(0xffffff, S3C64XX_SDMA_SEL);
744 744
745 /* Register standard DMA controllers */ 745 /* Register standard DMA controllers */
746 s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000); 746 s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
deleted file mode 100644
index 92b09085caaa..000000000000
--- a/arch/arm/mach-s3c64xx/gpiolib.c
+++ /dev/null
@@ -1,290 +0,0 @@
1/* arch/arm/plat-s3c64xx/gpiolib.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIOlib support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19
20#include <mach/map.h>
21
22#include <plat/gpio-core.h>
23#include <plat/gpio-cfg.h>
24#include <plat/gpio-cfg-helpers.h>
25#include <mach/regs-gpio.h>
26
27/* GPIO bank summary:
28 *
29 * Bank GPIOs Style SlpCon ExtInt Group
30 * A 8 4Bit Yes 1
31 * B 7 4Bit Yes 1
32 * C 8 4Bit Yes 2
33 * D 5 4Bit Yes 3
34 * E 5 4Bit Yes None
35 * F 16 2Bit Yes 4 [1]
36 * G 7 4Bit Yes 5
37 * H 10 4Bit[2] Yes 6
38 * I 16 2Bit Yes None
39 * J 12 2Bit Yes None
40 * K 16 4Bit[2] No None
41 * L 15 4Bit[2] No None
42 * M 6 4Bit No IRQ_EINT
43 * N 16 2Bit No IRQ_EINT
44 * O 16 2Bit Yes 7
45 * P 15 2Bit Yes 8
46 * Q 9 2Bit Yes 9
47 *
48 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
49 * [2] BANK has two control registers, GPxCON0 and GPxCON1
50 */
51
52static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
53 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
54 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
55 .set_pull = s3c_gpio_setpull_updown,
56 .get_pull = s3c_gpio_getpull_updown,
57};
58
59static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
60 .cfg_eint = 7,
61 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
62 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
63 .set_pull = s3c_gpio_setpull_updown,
64 .get_pull = s3c_gpio_getpull_updown,
65};
66
67static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
68 .cfg_eint = 3,
69 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
70 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
71 .set_pull = s3c_gpio_setpull_updown,
72 .get_pull = s3c_gpio_getpull_updown,
73};
74
75static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
76{
77 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
78}
79
80static struct s3c_gpio_chip gpio_4bit[] = {
81 {
82 .base = S3C64XX_GPA_BASE,
83 .config = &gpio_4bit_cfg_eint0111,
84 .chip = {
85 .base = S3C64XX_GPA(0),
86 .ngpio = S3C64XX_GPIO_A_NR,
87 .label = "GPA",
88 },
89 }, {
90 .base = S3C64XX_GPB_BASE,
91 .config = &gpio_4bit_cfg_eint0111,
92 .chip = {
93 .base = S3C64XX_GPB(0),
94 .ngpio = S3C64XX_GPIO_B_NR,
95 .label = "GPB",
96 },
97 }, {
98 .base = S3C64XX_GPC_BASE,
99 .config = &gpio_4bit_cfg_eint0111,
100 .chip = {
101 .base = S3C64XX_GPC(0),
102 .ngpio = S3C64XX_GPIO_C_NR,
103 .label = "GPC",
104 },
105 }, {
106 .base = S3C64XX_GPD_BASE,
107 .config = &gpio_4bit_cfg_eint0111,
108 .chip = {
109 .base = S3C64XX_GPD(0),
110 .ngpio = S3C64XX_GPIO_D_NR,
111 .label = "GPD",
112 },
113 }, {
114 .base = S3C64XX_GPE_BASE,
115 .config = &gpio_4bit_cfg_noint,
116 .chip = {
117 .base = S3C64XX_GPE(0),
118 .ngpio = S3C64XX_GPIO_E_NR,
119 .label = "GPE",
120 },
121 }, {
122 .base = S3C64XX_GPG_BASE,
123 .config = &gpio_4bit_cfg_eint0111,
124 .chip = {
125 .base = S3C64XX_GPG(0),
126 .ngpio = S3C64XX_GPIO_G_NR,
127 .label = "GPG",
128 },
129 }, {
130 .base = S3C64XX_GPM_BASE,
131 .config = &gpio_4bit_cfg_eint0011,
132 .chip = {
133 .base = S3C64XX_GPM(0),
134 .ngpio = S3C64XX_GPIO_M_NR,
135 .label = "GPM",
136 .to_irq = s3c64xx_gpio2int_gpm,
137 },
138 },
139};
140
141static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
142{
143 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
144}
145
146static struct s3c_gpio_chip gpio_4bit2[] = {
147 {
148 .base = S3C64XX_GPH_BASE + 0x4,
149 .config = &gpio_4bit_cfg_eint0111,
150 .chip = {
151 .base = S3C64XX_GPH(0),
152 .ngpio = S3C64XX_GPIO_H_NR,
153 .label = "GPH",
154 },
155 }, {
156 .base = S3C64XX_GPK_BASE + 0x4,
157 .config = &gpio_4bit_cfg_noint,
158 .chip = {
159 .base = S3C64XX_GPK(0),
160 .ngpio = S3C64XX_GPIO_K_NR,
161 .label = "GPK",
162 },
163 }, {
164 .base = S3C64XX_GPL_BASE + 0x4,
165 .config = &gpio_4bit_cfg_eint0011,
166 .chip = {
167 .base = S3C64XX_GPL(0),
168 .ngpio = S3C64XX_GPIO_L_NR,
169 .label = "GPL",
170 .to_irq = s3c64xx_gpio2int_gpl,
171 },
172 },
173};
174
175static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
176 .set_config = s3c_gpio_setcfg_s3c24xx,
177 .get_config = s3c_gpio_getcfg_s3c24xx,
178 .set_pull = s3c_gpio_setpull_updown,
179 .get_pull = s3c_gpio_getpull_updown,
180};
181
182static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
183 .cfg_eint = 2,
184 .set_config = s3c_gpio_setcfg_s3c24xx,
185 .get_config = s3c_gpio_getcfg_s3c24xx,
186 .set_pull = s3c_gpio_setpull_updown,
187 .get_pull = s3c_gpio_getpull_updown,
188};
189
190static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
191 .cfg_eint = 3,
192 .set_config = s3c_gpio_setcfg_s3c24xx,
193 .get_config = s3c_gpio_getcfg_s3c24xx,
194 .set_pull = s3c_gpio_setpull_updown,
195 .get_pull = s3c_gpio_getpull_updown,
196};
197
198static struct s3c_gpio_chip gpio_2bit[] = {
199 {
200 .base = S3C64XX_GPF_BASE,
201 .config = &gpio_2bit_cfg_eint11,
202 .chip = {
203 .base = S3C64XX_GPF(0),
204 .ngpio = S3C64XX_GPIO_F_NR,
205 .label = "GPF",
206 },
207 }, {
208 .base = S3C64XX_GPI_BASE,
209 .config = &gpio_2bit_cfg_noint,
210 .chip = {
211 .base = S3C64XX_GPI(0),
212 .ngpio = S3C64XX_GPIO_I_NR,
213 .label = "GPI",
214 },
215 }, {
216 .base = S3C64XX_GPJ_BASE,
217 .config = &gpio_2bit_cfg_noint,
218 .chip = {
219 .base = S3C64XX_GPJ(0),
220 .ngpio = S3C64XX_GPIO_J_NR,
221 .label = "GPJ",
222 },
223 }, {
224 .base = S3C64XX_GPN_BASE,
225 .irq_base = IRQ_EINT(0),
226 .config = &gpio_2bit_cfg_eint10,
227 .chip = {
228 .base = S3C64XX_GPN(0),
229 .ngpio = S3C64XX_GPIO_N_NR,
230 .label = "GPN",
231 .to_irq = samsung_gpiolib_to_irq,
232 },
233 }, {
234 .base = S3C64XX_GPO_BASE,
235 .config = &gpio_2bit_cfg_eint11,
236 .chip = {
237 .base = S3C64XX_GPO(0),
238 .ngpio = S3C64XX_GPIO_O_NR,
239 .label = "GPO",
240 },
241 }, {
242 .base = S3C64XX_GPP_BASE,
243 .config = &gpio_2bit_cfg_eint11,
244 .chip = {
245 .base = S3C64XX_GPP(0),
246 .ngpio = S3C64XX_GPIO_P_NR,
247 .label = "GPP",
248 },
249 }, {
250 .base = S3C64XX_GPQ_BASE,
251 .config = &gpio_2bit_cfg_eint11,
252 .chip = {
253 .base = S3C64XX_GPQ(0),
254 .ngpio = S3C64XX_GPIO_Q_NR,
255 .label = "GPQ",
256 },
257 },
258};
259
260static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
261{
262 chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
263}
264
265static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
266 int nr_chips,
267 void (*fn)(struct s3c_gpio_chip *))
268{
269 for (; nr_chips > 0; nr_chips--, chips++) {
270 if (fn)
271 (fn)(chips);
272 s3c_gpiolib_add(chips);
273 }
274}
275
276static __init int s3c64xx_gpiolib_init(void)
277{
278 s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
279 samsung_gpiolib_add_4bit);
280
281 s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
282 samsung_gpiolib_add_4bit2);
283
284 s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
285 s3c64xx_gpiolib_add_2bit);
286
287 return 0;
288}
289
290core_initcall(s3c64xx_gpiolib_init);
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
new file mode 100644
index 000000000000..be9074e17dfd
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
@@ -0,0 +1,23 @@
1/* Cragganmore 6410 shared definitions
2 *
3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef MACH_CRAG6410_H
12#define MACH_CRAG6410_H
13
14#include <linux/gpio.h>
15
16#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
17#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
18
19#define PCA935X_GPIO_BASE GPIO_BOARD_START
20#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
21#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
22
23#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index 0a5d9268a23e..fe1a98cf0e4c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -58,11 +58,15 @@ enum dma_ch {
58 DMACH_MAX /* the end */ 58 DMACH_MAX /* the end */
59}; 59};
60 60
61static __inline__ bool s3c_dma_has_circular(void) 61static inline bool samsung_dma_has_circular(void)
62{ 62{
63 return true; 63 return true;
64} 64}
65 65
66static inline bool samsung_dma_is_dmadev(void)
67{
68 return false;
69}
66#define S3C2410_DMAF_CIRCULAR (1 << 0) 70#define S3C2410_DMAF_CIRCULAR (1 << 0)
67 71
68#include <plat/dma.h> 72#include <plat/dma.h>
@@ -95,7 +99,7 @@ struct s3c2410_dma_chan {
95 unsigned char peripheral; 99 unsigned char peripheral;
96 100
97 unsigned int flags; 101 unsigned int flags;
98 enum s3c2410_dmasrc source; 102 enum dma_data_direction source;
99 103
100 104
101 dma_addr_t dev_addr; 105 dma_addr_t dev_addr;
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index 38659bebe4b1..fcf3dcabb694 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -104,7 +104,7 @@ static inline void s3c_pm_restored_gpios(void)
104 __raw_writel(0, S3C64XX_SLPEN); 104 __raw_writel(0, S3C64XX_SLPEN);
105} 105}
106 106
107static inline void s3c_pm_saved_gpios(void) 107static inline void samsung_pm_saved_gpios(void)
108{ 108{
109 /* turn on the sleep mode and keep it there, as it seems that during 109 /* turn on the sleep mode and keep it there, as it seems that during
110 * suspend the xCON registers get re-set and thus you can end up with 110 * suspend the xCON registers get re-set and thus you can end up with
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
index 69b78d9f83b8..b91e02093289 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
@@ -21,8 +21,11 @@
21#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104) 21#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
22#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108) 22#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
23 23
24#define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
25
24#define S3C64XX_OTHERS S3C_SYSREG(0x900) 26#define S3C64XX_OTHERS S3C_SYSREG(0x900)
25 27
26#define S3C64XX_OTHERS_USBMASK (1 << 16) 28#define S3C64XX_OTHERS_USBMASK (1 << 16)
29#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6)
27 30
28#endif /* _PLAT_REGS_SYS_H */ 31#endif /* _PLAT_REGS_SYS_H */
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
new file mode 100644
index 000000000000..66668565ee75
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -0,0 +1,182 @@
1/* Speyside modules for Cragganmore - board data probing
2 *
3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/interrupt.h>
13#include <linux/i2c.h>
14
15#include <linux/mfd/wm831x/irq.h>
16#include <linux/mfd/wm831x/gpio.h>
17
18#include <sound/wm8996.h>
19#include <sound/wm8962.h>
20#include <sound/wm9081.h>
21
22#include <mach/crag6410.h>
23
24static struct wm8996_retune_mobile_config wm8996_retune[] = {
25 {
26 .name = "Sub LPF",
27 .rate = 48000,
28 .regs = {
29 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
30 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
31 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
32 },
33 },
34 {
35 .name = "Sub HPF",
36 .rate = 48000,
37 .regs = {
38 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
39 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
40 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
41 },
42 },
43};
44
45static struct wm8996_pdata wm8996_pdata __initdata = {
46 .ldo_ena = S3C64XX_GPN(7),
47 .gpio_base = CODEC_GPIO_BASE,
48 .micdet_def = 1,
49 .inl_mode = WM8996_DIFFERRENTIAL_1,
50 .inr_mode = WM8996_DIFFERRENTIAL_1,
51
52 .irq_flags = IRQF_TRIGGER_RISING,
53
54 .gpio_default = {
55 0x8001, /* GPIO1 == ADCLRCLK1 */
56 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
57 0x0141, /* GPIO3 == HP_SEL */
58 0x0002, /* GPIO4 == IRQ */
59 0x020e, /* GPIO5 == CLKOUT */
60 },
61
62 .retune_mobile_cfgs = wm8996_retune,
63 .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
64};
65
66static struct wm8962_pdata wm8962_pdata __initdata = {
67 .gpio_init = {
68 0,
69 WM8962_GPIO_FN_OPCLK,
70 WM8962_GPIO_FN_DMICCLK,
71 0,
72 0x8000 | WM8962_GPIO_FN_DMICDAT,
73 WM8962_GPIO_FN_IRQ, /* Open drain mode */
74 },
75 .irq_active_low = true,
76};
77
78static struct wm9081_pdata wm9081_pdata __initdata = {
79 .irq_high = false,
80 .irq_cmos = false,
81};
82
83static const struct i2c_board_info wm1254_devs[] = {
84 { I2C_BOARD_INFO("wm8996", 0x1a),
85 .platform_data = &wm8996_pdata,
86 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
87 },
88 { I2C_BOARD_INFO("wm9081", 0x6c),
89 .platform_data = &wm9081_pdata, },
90};
91
92static const struct i2c_board_info wm1255_devs[] = {
93 { I2C_BOARD_INFO("wm5100", 0x1a),
94 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
95 },
96 { I2C_BOARD_INFO("wm9081", 0x6c),
97 .platform_data = &wm9081_pdata, },
98};
99
100static const struct i2c_board_info wm1259_devs[] = {
101 { I2C_BOARD_INFO("wm8962", 0x1a),
102 .platform_data = &wm8962_pdata,
103 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
104 },
105};
106
107
108static __devinitdata const struct {
109 u8 id;
110 const char *name;
111 const struct i2c_board_info *i2c_devs;
112 int num_i2c_devs;
113} gf_mods[] = {
114 { .id = 0x01, .name = "1250-EV1 Springbank" },
115 { .id = 0x02, .name = "1251-EV1 Jura" },
116 { .id = 0x03, .name = "1252-EV1 Glenlivet" },
117 { .id = 0x11, .name = "6249-EV2 Glenfarclas", },
118 { .id = 0x21, .name = "1275-EV1 Mortlach" },
119 { .id = 0x25, .name = "1274-EV1 Glencadam" },
120 { .id = 0x31, .name = "1253-EV1 Tomatin", },
121 { .id = 0x39, .name = "1254-EV1 Dallas Dhu",
122 .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
123 { .id = 0x3a, .name = "1259-EV1 Tobermory",
124 .i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) },
125 { .id = 0x3b, .name = "1255-EV1 Kilchoman",
126 .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
127 { .id = 0x3c, .name = "1273-EV1 Longmorn" },
128};
129
130static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
131 const struct i2c_device_id *i2c_id)
132{
133 int ret, i, j, id, rev;
134
135 ret = i2c_smbus_read_byte_data(i2c, 0);
136 if (ret < 0) {
137 dev_err(&i2c->dev, "Failed to read ID: %d\n", ret);
138 return ret;
139 }
140
141 id = (ret & 0xfe) >> 2;
142 rev = ret & 0x3;
143 for (i = 0; i < ARRAY_SIZE(gf_mods); i++)
144 if (id == gf_mods[i].id)
145 break;
146
147 if (i < ARRAY_SIZE(gf_mods)) {
148 dev_info(&i2c->dev, "%s revision %d\n",
149 gf_mods[i].name, rev + 1);
150 for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
151 if (!i2c_new_device(i2c->adapter,
152 &(gf_mods[i].i2c_devs[j])))
153 dev_err(&i2c->dev,
154 "Failed to register dev: %d\n", ret);
155 }
156 } else {
157 dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n",
158 id, rev);
159 }
160
161 return 0;
162}
163
164static const struct i2c_device_id wlf_gf_module_id[] = {
165 { "wlf-gf-module", 0 },
166 { }
167};
168
169static struct i2c_driver wlf_gf_module_driver = {
170 .driver = {
171 .name = "wlf-gf-module",
172 .owner = THIS_MODULE,
173 },
174 .probe = wlf_gf_module_probe,
175 .id_table = wlf_gf_module_id,
176};
177
178static int __init wlf_gf_module_register(void)
179{
180 return i2c_add_driver(&wlf_gf_module_driver);
181}
182module_init(wlf_gf_module_register);
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index f32ec68002ef..30afaa537fcf 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -47,6 +47,7 @@
47#include <mach/regs-sys.h> 47#include <mach/regs-sys.h>
48#include <mach/regs-gpio.h> 48#include <mach/regs-gpio.h>
49#include <mach/regs-modem.h> 49#include <mach/regs-modem.h>
50#include <mach/crag6410.h>
50 51
51#include <mach/regs-gpio-memport.h> 52#include <mach/regs-gpio-memport.h>
52 53
@@ -65,17 +66,6 @@
65#include <plat/iic.h> 66#include <plat/iic.h>
66#include <plat/pm.h> 67#include <plat/pm.h>
67 68
68#include <sound/wm8996.h>
69#include <sound/wm8962.h>
70#include <sound/wm9081.h>
71
72#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
73#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
74
75#define PCA935X_GPIO_BASE GPIO_BOARD_START
76#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
77#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
78
79/* serial port setup */ 69/* serial port setup */
80 70
81#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) 71#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
@@ -287,6 +277,11 @@ static struct platform_device speyside_device = {
287 .id = -1, 277 .id = -1,
288}; 278};
289 279
280static struct platform_device lowland_device = {
281 .name = "lowland",
282 .id = -1,
283};
284
290static struct platform_device speyside_wm8962_device = { 285static struct platform_device speyside_wm8962_device = {
291 .name = "speyside-wm8962", 286 .name = "speyside-wm8962",
292 .id = -1, 287 .id = -1,
@@ -295,6 +290,8 @@ static struct platform_device speyside_wm8962_device = {
295static struct regulator_consumer_supply wallvdd_consumers[] = { 290static struct regulator_consumer_supply wallvdd_consumers[] = {
296 REGULATOR_SUPPLY("SPKVDD1", "1-001a"), 291 REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
297 REGULATOR_SUPPLY("SPKVDD2", "1-001a"), 292 REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
293 REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
294 REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
298}; 295};
299 296
300static struct regulator_init_data wallvdd_data = { 297static struct regulator_init_data wallvdd_data = {
@@ -342,6 +339,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
342 &crag6410_backlight_device, 339 &crag6410_backlight_device,
343 &speyside_device, 340 &speyside_device,
344 &speyside_wm8962_device, 341 &speyside_wm8962_device,
342 &lowland_device,
345 &wallvdd_device, 343 &wallvdd_device,
346}; 344};
347 345
@@ -350,6 +348,12 @@ static struct pca953x_platform_data crag6410_pca_data = {
350 .irq_base = 0, 348 .irq_base = 0,
351}; 349};
352 350
351/* VDDARM is controlled by DVS1 connected to GPK(0) */
352static struct wm831x_buckv_pdata vddarm_pdata = {
353 .dvs_control_src = 1,
354 .dvs_gpio = S3C64XX_GPK(0),
355};
356
353static struct regulator_consumer_supply vddarm_consumers[] __initdata = { 357static struct regulator_consumer_supply vddarm_consumers[] __initdata = {
354 REGULATOR_SUPPLY("vddarm", NULL), 358 REGULATOR_SUPPLY("vddarm", NULL),
355}; 359};
@@ -365,6 +369,7 @@ static struct regulator_init_data vddarm __initdata = {
365 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers), 369 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
366 .consumer_supplies = vddarm_consumers, 370 .consumer_supplies = vddarm_consumers,
367 .supply_regulator = "WALLVDD", 371 .supply_regulator = "WALLVDD",
372 .driver_data = &vddarm_pdata,
368}; 373};
369 374
370static struct regulator_init_data vddint __initdata = { 375static struct regulator_init_data vddint __initdata = {
@@ -500,6 +505,8 @@ static struct wm831x_pdata crag_pmic_pdata __initdata = {
500 .backup = &banff_backup_pdata, 505 .backup = &banff_backup_pdata,
501 506
502 .gpio_defaults = { 507 .gpio_defaults = {
508 /* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
509 [4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
503 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/ 510 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
504 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6, 511 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
505 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/ 512 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
@@ -557,8 +564,12 @@ static struct regulator_init_data pvdd_1v2 __initdata = {
557}; 564};
558 565
559static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = { 566static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
567 REGULATOR_SUPPLY("LDOVDD", "1-001a"),
560 REGULATOR_SUPPLY("PLLVDD", "1-001a"), 568 REGULATOR_SUPPLY("PLLVDD", "1-001a"),
561 REGULATOR_SUPPLY("DBVDD", "1-001a"), 569 REGULATOR_SUPPLY("DBVDD", "1-001a"),
570 REGULATOR_SUPPLY("DBVDD1", "1-001a"),
571 REGULATOR_SUPPLY("DBVDD2", "1-001a"),
572 REGULATOR_SUPPLY("DBVDD3", "1-001a"),
562 REGULATOR_SUPPLY("CPVDD", "1-001a"), 573 REGULATOR_SUPPLY("CPVDD", "1-001a"),
563 REGULATOR_SUPPLY("AVDD2", "1-001a"), 574 REGULATOR_SUPPLY("AVDD2", "1-001a"),
564 REGULATOR_SUPPLY("DCVDD", "1-001a"), 575 REGULATOR_SUPPLY("DCVDD", "1-001a"),
@@ -611,81 +622,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
611 .disable_touch = true, 622 .disable_touch = true,
612}; 623};
613 624
614static struct wm8996_retune_mobile_config wm8996_retune[] = {
615 {
616 .name = "Sub LPF",
617 .rate = 48000,
618 .regs = {
619 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
620 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
621 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
622 },
623 },
624 {
625 .name = "Sub HPF",
626 .rate = 48000,
627 .regs = {
628 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
629 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
630 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
631 },
632 },
633};
634
635static struct wm8996_pdata wm8996_pdata __initdata = {
636 .ldo_ena = S3C64XX_GPN(7),
637 .gpio_base = CODEC_GPIO_BASE,
638 .micdet_def = 1,
639 .inl_mode = WM8996_DIFFERRENTIAL_1,
640 .inr_mode = WM8996_DIFFERRENTIAL_1,
641
642 .irq_flags = IRQF_TRIGGER_RISING,
643
644 .gpio_default = {
645 0x8001, /* GPIO1 == ADCLRCLK1 */
646 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
647 0x0141, /* GPIO3 == HP_SEL */
648 0x0002, /* GPIO4 == IRQ */
649 0x020e, /* GPIO5 == CLKOUT */
650 },
651
652 .retune_mobile_cfgs = wm8996_retune,
653 .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
654};
655
656static struct wm8962_pdata wm8962_pdata __initdata = {
657 .gpio_init = {
658 0,
659 WM8962_GPIO_FN_OPCLK,
660 WM8962_GPIO_FN_DMICCLK,
661 0,
662 0x8000 | WM8962_GPIO_FN_DMICDAT,
663 WM8962_GPIO_FN_IRQ, /* Open drain mode */
664 },
665 .irq_active_low = true,
666};
667
668static struct wm9081_pdata wm9081_pdata __initdata = {
669 .irq_high = false,
670 .irq_cmos = false,
671};
672
673static struct i2c_board_info i2c_devs1[] __initdata = { 625static struct i2c_board_info i2c_devs1[] __initdata = {
674 { I2C_BOARD_INFO("wm8311", 0x34), 626 { I2C_BOARD_INFO("wm8311", 0x34),
675 .irq = S3C_EINT(0), 627 .irq = S3C_EINT(0),
676 .platform_data = &glenfarclas_pmic_pdata }, 628 .platform_data = &glenfarclas_pmic_pdata },
677 629
630 { I2C_BOARD_INFO("wlf-gf-module", 0x24) },
631 { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
632 { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
633
678 { I2C_BOARD_INFO("wm1250-ev1", 0x27) }, 634 { I2C_BOARD_INFO("wm1250-ev1", 0x27) },
679 { I2C_BOARD_INFO("wm8996", 0x1a),
680 .platform_data = &wm8996_pdata,
681 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
682 },
683 { I2C_BOARD_INFO("wm9081", 0x6c),
684 .platform_data = &wm9081_pdata, },
685 { I2C_BOARD_INFO("wm8962", 0x1a),
686 .platform_data = &wm8962_pdata,
687 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
688 },
689}; 635};
690 636
691static void __init crag6410_map_io(void) 637static void __init crag6410_map_io(void)
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 055e2858b0dd..b375cd5c47cb 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -29,6 +29,7 @@
29#include <mach/regs-clock.h> 29#include <mach/regs-clock.h>
30#include <mach/regs-syscon-power.h> 30#include <mach/regs-syscon-power.h>
31#include <mach/regs-gpio-memport.h> 31#include <mach/regs-gpio-memport.h>
32#include <mach/regs-modem.h>
32 33
33#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK 34#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
34void s3c_pm_debug_smdkled(u32 set, u32 clear) 35void s3c_pm_debug_smdkled(u32 set, u32 clear)
@@ -85,6 +86,9 @@ static struct sleep_save misc_save[] = {
85 SAVE_ITEM(S3C64XX_MEM0CONSLP0), 86 SAVE_ITEM(S3C64XX_MEM0CONSLP0),
86 SAVE_ITEM(S3C64XX_MEM0CONSLP1), 87 SAVE_ITEM(S3C64XX_MEM0CONSLP1),
87 SAVE_ITEM(S3C64XX_MEM1CONSLP), 88 SAVE_ITEM(S3C64XX_MEM1CONSLP),
89
90 SAVE_ITEM(S3C64XX_SDMA_SEL),
91 SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
88}; 92};
89 93
90void s3c_pm_configure_extint(void) 94void s3c_pm_configure_extint(void)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 19:03:34 -0500