Merge tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Cleanups for the Samsung platforms

Various cleanup changes that the device driver changes are built upon.
Since the samsung cleanups depend on the device tree series, which
depends on the first set of cleanups for tegra.

* tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: EXYNOS: Use gpio_request_one
  ARM: S5PV210: Use gpio_request_one
  ARM: S3C64XX: Modified according to SPI consolidation work
  ARM: S5PV210: Modified files for SPI consolidation work
  ARM: S5P64X0: Modified files for SPI consolidation work
  ARM: S5PC100: Modified files for SPI consolidation work
  ARM: S3C64XX: Modified files for SPI consolidation work
  ARM: SAMSUNG: Consolidation of SPI platform devices to plat-samsung
  ARM: SAMSUNG: Remove SPI bus clocks from platform data
  ARM: S5PV210: Add SPI clkdev support
  ARM: S5P64X0: Add SPI clkdev support
  ARM: S5PC100: Add SPI clkdev support
  ARM: S3C64XX: Add SPI clkdev support
  spi/s3c64xx: Use bus clocks created using clkdev
  mmc: sdhci-s3c: Use generic clock names for sdhci bus clock options
  ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
  ARM: SAMSUNG: Remove SDHCI bus clocks from platform data
  ARM: SAMSUNG: Use kmemdup rather than duplicating its implementation
  ARM: EXYNOS: remove exynos4_scu_enable()

7 files changed, 182 insertions, 285 deletions

diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 381586c7b1b2..e42e26d7fd38 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -78,6 +78,11 @@ config S3C64XX_SETUP_SDHCI_GPIO
         help
           Common setup code for S3C64XX SDHCI GPIO configurations
 
+config S3C64XX_SETUP_SPI
+        bool
+        help
+         Common setup code for SPI GPIO configurations
+
 # S36400 Macchine support
 
 config MACH_SMDK6400
@@ -277,6 +282,7 @@ config MACH_WLF_CRAGG_6410
         select S3C64XX_SETUP_IDE
         select S3C64XX_SETUP_FB_24BPP
         select S3C64XX_SETUP_KEYPAD
+        select S3C64XX_SETUP_SPI
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_KEYPAD
         select S3C_DEV_USB_HOST
@@ -287,7 +293,7 @@ config MACH_WLF_CRAGG_6410
         select S3C_DEV_I2C1
         select S3C_DEV_WDT
         select S3C_DEV_RTC
-        select S3C64XX_DEV_SPI
+        select S3C64XX_DEV_SPI0
         select S3C24XX_GPIO_EXTRA128
         select I2C
         help
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index f37016cebbe3..1822ac2eba31 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -40,8 +40,8 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0)	+= setup-i2c0.o
 obj-$(CONFIG_S3C64XX_SETUP_I2C1)        += setup-i2c1.o
 obj-$(CONFIG_S3C64XX_SETUP_IDE)         += setup-ide.o
 obj-$(CONFIG_S3C64XX_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_S3C64XX_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_S3C64XX_SETUP_SPI)         += setup-spi.o
 
 # Machine support
 
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index a3aafb6768c9..31bb27dc4aeb 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = s3c64xx_pclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
         }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.0",
-                .parent         = &clk_48m,
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
-        }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.1",
-                .parent         = &clk_48m,
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
-        }, {
                 .name           = "48m",
                 .devname        = "s3c-sdhci.0",
                 .parent         = &clk_48m,
@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = {
         },
 };
 
+static struct clk clk_48m_spi0 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.0",
+        .parent         = &clk_48m,
+        .enable         = s3c64xx_sclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
+};
+
+static struct clk clk_48m_spi1 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.1",
+        .parent         = &clk_48m,
+        .enable         = s3c64xx_sclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
+};
+
 static struct clk init_clocks[] = {
         {
                 .name           = "lcd",
@@ -243,24 +247,6 @@ static struct clk init_clocks[] = {
                 .enable         = s3c64xx_hclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
         }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
-        }, {
                 .name           = "otg",
                 .parent         = &clk_h,
                 .enable         = s3c64xx_hclk_ctrl,
@@ -310,6 +296,29 @@ static struct clk init_clocks[] = {
         }
 };
 
+static struct clk clk_hsmmc0 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.0",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
+};
+
+static struct clk clk_hsmmc1 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
+};
+
+static struct clk clk_hsmmc2 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.2",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
+};
 
 static struct clk clk_fout_apll = {
         .name           = "fout_apll",
@@ -578,36 +587,6 @@ static struct clksrc_sources clkset_camif = {
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
                         .name           = "usb-bus-host",
                         .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
                         .enable         = s3c64xx_sclk_ctrl,
@@ -617,25 +596,6 @@ static struct clksrc_clk clksrcs[] = {
                 .sources        = &clkset_uhost,
         }, {
                 .clk    = {
-                        .name           = "spi-bus",
-                        .devname        = "s3c64xx-spi.0",
-                        .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "spi-bus",
-                        .devname        = "s3c64xx-spi.1",
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
                         .name           = "audio-bus",
                         .devname        = "samsung-i2s.0",
                         .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
@@ -697,6 +657,66 @@ static struct clksrc_clk clk_sclk_uclk = {
         .sources        = &clkset_uart,
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "spi-bus",
+                .devname        = "s3c64xx-spi.0",
+                .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
+        .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
+        .sources = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "spi-bus",
+                .devname        = "s3c64xx-spi.1",
+                .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
+        .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
+        .sources = &clkset_spi_mmc,
+};
+
 /* Clock initialisation code */
 
 static struct clksrc_clk *init_parents[] = {
@@ -707,11 +727,35 @@ static struct clksrc_clk *init_parents[] = {
 
 static struct clksrc_clk *clksrc_cdev[] = {
         &clk_sclk_uclk,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+};
+
+static struct clk *clk_cdev[] = {
+        &clk_hsmmc0,
+        &clk_hsmmc1,
+        &clk_hsmmc2,
+        &clk_48m_spi0,
+        &clk_48m_spi1,
 };
 
 static struct clk_lookup s3c64xx_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
 };
 
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -834,6 +878,10 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
+                s3c_disable_clocks(clk_cdev[cnt], 1);
+
         s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
deleted file mode 100644
index 3341fd118723..000000000000
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/dev-spi.c
- *
- * Copyright (C) 2009 Samsung Electronics Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/spi-clocks.h>
-#include <mach/irqs.h>
-
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-
-static char *spi_src_clks[] = {
-        [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
-        [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
-        [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
-};
-
-/* SPI Controller platform_devices */
-
-/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
-{
-        unsigned int base;
-
-        switch (pdev->id) {
-        case 0:
-                base = S3C64XX_GPC(0);
-                break;
-
-        case 1:
-                base = S3C64XX_GPC(4);
-                break;
-
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-
-        s3c_gpio_cfgall_range(base, 3,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-
-        return 0;
-}
-
-static struct resource s3c64xx_spi0_resource[] = {
-        [0] = {
-                .start = S3C64XX_PA_SPI0,
-                .end   = S3C64XX_PA_SPI0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI0_TX,
-                .end   = DMACH_SPI0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI0_RX,
-                .end   = DMACH_SPI0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI0,
-                .end   = IRQ_SPI0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
-        .cfg_gpio = s3c64xx_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .tx_st_done = 21,
-};
-
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s3c64xx_device_spi0 = {
-        .name             = "s3c64xx-spi",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s3c64xx_spi0_resource),
-        .resource         = s3c64xx_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s3c64xx_spi0_pdata,
-        },
-};
-EXPORT_SYMBOL(s3c64xx_device_spi0);
-
-static struct resource s3c64xx_spi1_resource[] = {
-        [0] = {
-                .start = S3C64XX_PA_SPI1,
-                .end   = S3C64XX_PA_SPI1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI1_TX,
-                .end   = DMACH_SPI1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI1_RX,
-                .end   = DMACH_SPI1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI1,
-                .end   = IRQ_SPI1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
-        .cfg_gpio = s3c64xx_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .tx_st_done = 21,
-};
-
-struct platform_device s3c64xx_device_spi1 = {
-        .name             = "s3c64xx-spi",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s3c64xx_spi1_resource),
-        .resource         = s3c64xx_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s3c64xx_spi1_pdata,
-        },
-};
-EXPORT_SYMBOL(s3c64xx_device_spi1);
-
-void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-
-        switch (cntrlr) {
-        case 0:
-                pd = &s3c64xx_spi0_pdata;
-                break;
-        case 1:
-                pd = &s3c64xx_spi1_pdata;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 23a1d71e4d53..8e2097bb208a 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -115,6 +115,8 @@
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
 #define S3C_PA_RTC              S3C64XX_PA_RTC
 #define S3C_PA_WDT              S3C64XX_PA_WATCHDOG
+#define S3C_PA_SPI0             S3C64XX_PA_SPI0
+#define S3C_PA_SPI1             S3C64XX_PA_SPI1
 
 #define SAMSUNG_PA_ADC          S3C64XX_PA_ADC
 #define SAMSUNG_PA_CFCON        S3C64XX_PA_CFCON
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
deleted file mode 100644
index c75a71b21165..000000000000
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
- *
- * Copyright 2008 Simtec Electronics
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s3c64xx_hsmmc_clksrcs[4] = {
-        [0] = "hsmmc",
-        [1] = "hsmmc",
-        [2] = "mmc_bus",
-        /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
new file mode 100644
index 000000000000..d9592ad7a825
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -0,0 +1,45 @@
+/* linux/arch/arm/mach-s3c64xx/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .tx_st_done     = 21,
+};
+
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .tx_st_done     = 21,
+};
+
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif