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authorBen Dooks <ben-linux@fluff.org>2010-01-25 20:45:40 -0500
committerBen Dooks <ben-linux@fluff.org>2010-02-20 17:31:17 -0500
commit3501c9ae9fc5414d09c9a8d3a5452d2b167db916 (patch)
tree200146af3989c0c07b0a66bff96ac959602d1b1e /arch/arm/mach-s3c64xx
parent2f6c2ac1d945ffc2e343103bdcfccbdb2e2de805 (diff)
ARM: S3C64XX: Move headers into machine include directory
Move the register and GPIO definition files from plat-s3c64xx into the machine include direcotry as they are unlikely to be reused outside mach-s3c64xx. This move includes removing the empty <mach/regs-clock.h> and replacing it with the <plat/regs-clock.h> implementation. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c64xx')
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h48
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h60
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h53
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h49
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h44
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h71
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h42
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h74
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h40
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h36
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h54
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h70
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h69
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h46
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-clock.h148
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h25
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-gpio.h187
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-modem.h31
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-srom.h59
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-sys.h28
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h116
-rw-r--r--arch/arm/mach-s3c64xx/mach-anw6410.c4
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c8
-rw-r--r--arch/arm/mach-s3c64xx/s3c6400.c2
-rw-r--r--arch/arm/mach-s3c64xx/s3c6410.c2
25 files changed, 1354 insertions, 12 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
new file mode 100644
index 000000000000..34212e1a7e81
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
@@ -0,0 +1,48 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank A register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00)
16#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04)
17#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08)
18#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c)
19#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10)
20
21#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0)
26#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0)
27
28#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4)
29#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4)
30
31#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8)
32#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8)
33
34#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12)
35#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12)
36
37#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16)
38#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16)
39
40#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20)
41#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20)
42
43#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24)
44#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24)
45
46#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28)
47#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28)
48
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
new file mode 100644
index 000000000000..7232c037e642
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
@@ -0,0 +1,60 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank B register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00)
16#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04)
17#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08)
18#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c)
19#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10)
20
21#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0)
26#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0)
27#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0)
28#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0)
29#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0)
30
31#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4)
32#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4)
33#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4)
34#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4)
35#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4)
36
37#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8)
38#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8)
39#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8)
40#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8)
41#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8)
42#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8)
43
44#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12)
45#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12)
46#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12)
47#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12)
48#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12)
49
50#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16)
51#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16)
52#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16)
53#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16)
54
55#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20)
56#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20)
57
58#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24)
59#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24)
60
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
new file mode 100644
index 000000000000..db189ab1639a
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
@@ -0,0 +1,53 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank C register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00)
16#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04)
17#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08)
18#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c)
19#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10)
20
21#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0)
26#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0)
27
28#define S3C64XX_GPC1_SPI_CLKO (0x02 << 4)
29#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4)
30
31#define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8)
32#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8)
33
34#define S3C64XX_GPC3_SPI_nCSO (0x02 << 12)
35#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12)
36
37#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16)
38#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16)
39#define S3C64XX_GPC4_I2S_V40_DO0 (0x05 << 16)
40#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16)
41
42#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20)
43#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20)
44#define S3C64XX_GPC5_I2S_V40_DO1 (0x05 << 20)
45#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20)
46
47#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24)
48#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24)
49
50#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28)
51#define S3C64XX_GPC7_I2S_V40_DO2 (0x05 << 28)
52#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28)
53
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
new file mode 100644
index 000000000000..1a01cee7aca3
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
@@ -0,0 +1,49 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank D register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00)
16#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04)
17#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08)
18#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c)
19#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10)
20
21#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0)
26#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0)
27#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0)
28#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0)
29
30#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4)
31#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4)
32#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4)
33#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4)
34
35#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8)
36#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8)
37#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8)
38#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8)
39
40#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12)
41#define S3C64XX_GPD3_I2S0_DI (0x03 << 12)
42#define S3C64XX_GPD3_AC97_SDI (0x04 << 12)
43#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12)
44
45#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16)
46#define S3C64XX_GPD4_I2S0_D0 (0x03 << 16)
47#define S3C64XX_GPD4_AC97_SDO (0x04 << 16)
48#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16)
49
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
new file mode 100644
index 000000000000..f057adb627dd
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
@@ -0,0 +1,44 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank E register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00)
16#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04)
17#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08)
18#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c)
19#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10)
20
21#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0)
26#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0)
27#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0)
28
29#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4)
30#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4)
31#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4)
32
33#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8)
34#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8)
35#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8)
36
37#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12)
38#define S3C64XX_GPE3_I2S1_DI (0x03 << 12)
39#define S3C64XX_GPE3_AC97_SDI (0x04 << 12)
40
41#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16)
42#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16)
43#define S3C64XX_GPE4_AC97_SDO (0x04 << 16)
44
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
new file mode 100644
index 000000000000..62ab8f5e7835
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
@@ -0,0 +1,71 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank F register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00)
16#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04)
17#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08)
18#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c)
19#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10)
20
21#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0)
26#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0)
27
28#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2)
29#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2)
30
31#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4)
32#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4)
33
34#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6)
35#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6)
36
37#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8)
38#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8)
39
40#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10)
41#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10)
42
43#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12)
44#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12)
45
46#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14)
47#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14)
48
49#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16)
50#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16)
51
52#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18)
53#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18)
54
55#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20)
56#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20)
57
58#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22)
59#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22)
60
61#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24)
62#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24)
63
64#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26)
65#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26)
66
67#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28)
68#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28)
69
70#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30)
71
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
new file mode 100644
index 000000000000..b94954af1598
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
@@ -0,0 +1,42 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank G register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00)
16#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04)
17#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08)
18#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c)
19#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10)
20
21#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0)
26#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0)
27
28#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4)
29#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4)
30
31#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8)
32#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8)
33
34#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12)
35#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12)
36
37#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16)
38#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16)
39
40#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20)
41#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20)
42
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
new file mode 100644
index 000000000000..5d75aaad865e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
@@ -0,0 +1,74 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank H register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00)
16#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04)
17#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08)
18#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c)
19#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10)
20#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14)
21
22#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4))
23#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4))
24#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
25
26#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0)
27#define S3C64XX_GPH0_KP_COL0 (0x04 << 0)
28#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0)
29
30#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4)
31#define S3C64XX_GPH1_KP_COL1 (0x04 << 4)
32#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4)
33
34#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8)
35#define S3C64XX_GPH2_KP_COL2 (0x04 << 8)
36#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8)
37
38#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12)
39#define S3C64XX_GPH3_KP_COL3 (0x04 << 12)
40#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12)
41
42#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16)
43#define S3C64XX_GPH4_KP_COL4 (0x04 << 16)
44#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16)
45
46#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20)
47#define S3C64XX_GPH5_KP_COL5 (0x04 << 20)
48#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20)
49
50#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24)
51#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24)
52#define S3C64XX_GPH6_KP_COL6 (0x04 << 24)
53#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24)
54#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24)
55#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24)
56
57#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28)
58#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28)
59#define S3C64XX_GPH7_KP_COL7 (0x04 << 28)
60#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28)
61#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
62#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
63
64#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 0)
65#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 0)
66#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 0)
67#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 0)
68#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 0)
69
70#define S3C64XX_GPH9_OUTPUT (0x01 << 4)
71#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 4)
72#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 4)
73#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 4)
74#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 4)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
new file mode 100644
index 000000000000..4ceaa6098bc7
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
@@ -0,0 +1,40 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank I register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00)
16#define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04)
17#define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08)
18#define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c)
19#define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10)
20
21#define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPI0_VD0 (0x02 << 0)
26#define S3C64XX_GPI1_VD1 (0x02 << 2)
27#define S3C64XX_GPI2_VD2 (0x02 << 4)
28#define S3C64XX_GPI3_VD3 (0x02 << 6)
29#define S3C64XX_GPI4_VD4 (0x02 << 8)
30#define S3C64XX_GPI5_VD5 (0x02 << 10)
31#define S3C64XX_GPI6_VD6 (0x02 << 12)
32#define S3C64XX_GPI7_VD7 (0x02 << 14)
33#define S3C64XX_GPI8_VD8 (0x02 << 16)
34#define S3C64XX_GPI9_VD9 (0x02 << 18)
35#define S3C64XX_GPI10_VD10 (0x02 << 20)
36#define S3C64XX_GPI11_VD11 (0x02 << 22)
37#define S3C64XX_GPI12_VD12 (0x02 << 24)
38#define S3C64XX_GPI13_VD13 (0x02 << 26)
39#define S3C64XX_GPI14_VD14 (0x02 << 28)
40#define S3C64XX_GPI15_VD15 (0x02 << 30)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
new file mode 100644
index 000000000000..6f25cd079a40
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
@@ -0,0 +1,36 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank J register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00)
16#define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04)
17#define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08)
18#define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c)
19#define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10)
20
21#define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPJ0_VD16 (0x02 << 0)
26#define S3C64XX_GPJ1_VD17 (0x02 << 2)
27#define S3C64XX_GPJ2_VD18 (0x02 << 4)
28#define S3C64XX_GPJ3_VD19 (0x02 << 6)
29#define S3C64XX_GPJ4_VD20 (0x02 << 8)
30#define S3C64XX_GPJ5_VD21 (0x02 << 10)
31#define S3C64XX_GPJ6_VD22 (0x02 << 12)
32#define S3C64XX_GPJ7_VD23 (0x02 << 14)
33#define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16)
34#define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18)
35#define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20)
36#define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
new file mode 100644
index 000000000000..d0aeda1cd9de
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
@@ -0,0 +1,54 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank N register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
16#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
17#define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08)
18
19#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
20#define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2))
21#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
22
23#define S3C64XX_GPN0_EINT0 (0x02 << 0)
24#define S3C64XX_GPN0_KP_ROW0 (0x03 << 0)
25
26#define S3C64XX_GPN1_EINT1 (0x02 << 2)
27#define S3C64XX_GPN1_KP_ROW1 (0x03 << 2)
28
29#define S3C64XX_GPN2_EINT2 (0x02 << 4)
30#define S3C64XX_GPN2_KP_ROW2 (0x03 << 4)
31
32#define S3C64XX_GPN3_EINT3 (0x02 << 6)
33#define S3C64XX_GPN3_KP_ROW3 (0x03 << 6)
34
35#define S3C64XX_GPN4_EINT4 (0x02 << 8)
36#define S3C64XX_GPN4_KP_ROW4 (0x03 << 8)
37
38#define S3C64XX_GPN5_EINT5 (0x02 << 10)
39#define S3C64XX_GPN5_KP_ROW5 (0x03 << 10)
40
41#define S3C64XX_GPN6_EINT6 (0x02 << 12)
42#define S3C64XX_GPN6_KP_ROW6 (0x03 << 12)
43
44#define S3C64XX_GPN7_EINT7 (0x02 << 14)
45#define S3C64XX_GPN7_KP_ROW7 (0x03 << 14)
46
47#define S3C64XX_GPN8_EINT8 (0x02 << 16)
48#define S3C64XX_GPN9_EINT9 (0x02 << 18)
49#define S3C64XX_GPN10_EINT10 (0x02 << 20)
50#define S3C64XX_GPN11_EINT11 (0x02 << 22)
51#define S3C64XX_GPN12_EINT12 (0x02 << 24)
52#define S3C64XX_GPN13_EINT13 (0x02 << 26)
53#define S3C64XX_GPN14_EINT14 (0x02 << 28)
54#define S3C64XX_GPN15_EINT15 (0x02 << 30)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
new file mode 100644
index 000000000000..21868fa102d0
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
@@ -0,0 +1,70 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank O register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00)
16#define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04)
17#define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08)
18#define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c)
19#define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10)
20
21#define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0)
26#define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0)
27
28#define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2)
29#define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2)
30
31#define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4)
32#define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4)
33
34#define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6)
35#define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6)
36
37#define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8)
38
39#define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10)
40
41#define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12)
42#define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12)
43
44#define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14)
45#define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14)
46
47#define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16)
48#define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16)
49
50#define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18)
51#define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18)
52
53#define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20)
54#define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20)
55
56#define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22)
57#define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22)
58
59#define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24)
60#define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24)
61
62#define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26)
63#define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26)
64
65#define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28)
66#define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28)
67
68#define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30)
69#define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30)
70
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
new file mode 100644
index 000000000000..46bcfb63b8de
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
@@ -0,0 +1,69 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank P register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00)
16#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04)
17#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08)
18#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c)
19#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10)
20
21#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0)
26#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0)
27
28#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2)
29#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2)
30
31#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4)
32#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4)
33
34#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6)
35#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6)
36
37#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8)
38#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8)
39
40#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10)
41#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10)
42
43#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12)
44#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12)
45
46#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14)
47#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14)
48
49#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16)
50#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16)
51
52#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18)
53#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18)
54
55#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20)
56#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20)
57
58#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22)
59#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22)
60
61#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24)
62#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24)
63
64#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26)
65#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26)
66
67#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28)
68#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28)
69
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
new file mode 100644
index 000000000000..1712223487b0
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
@@ -0,0 +1,46 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank Q register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00)
16#define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04)
17#define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08)
18#define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c)
19#define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10)
20
21#define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0)
26#define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0)
27
28#define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2)
29#define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2)
30
31#define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4)
32
33#define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6)
34
35#define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8)
36
37#define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10)
38
39#define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12)
40
41#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14)
42#define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14)
43
44#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16)
45#define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16)
46
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
index a6c7f4eb3a1b..3ef62741e5d1 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
@@ -1,16 +1,156 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h 1/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
2 * 2 *
3 * Copyright 2008 Openmoko, Inc. 3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics 4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 * 7 *
8 * S3C64XX - clock register compatibility with s3c24xx 8 * S3C64XX clock register definitions
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13*/ 13*/
14 14
15#include <plat/regs-clock.h> 15#ifndef __PLAT_REGS_CLOCK_H
16#define __PLAT_REGS_CLOCK_H __FILE__
17
18#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S3C_APLL_LOCK S3C_CLKREG(0x00)
21#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
22#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
23#define S3C_APLL_CON S3C_CLKREG(0x0C)
24#define S3C_MPLL_CON S3C_CLKREG(0x10)
25#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
26#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
27#define S3C_CLK_SRC S3C_CLKREG(0x1C)
28#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
29#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
30#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
31#define S3C_CLK_OUT S3C_CLKREG(0x2C)
32#define S3C_HCLK_GATE S3C_CLKREG(0x30)
33#define S3C_PCLK_GATE S3C_CLKREG(0x34)
34#define S3C_SCLK_GATE S3C_CLKREG(0x38)
35#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
36
37/* CLKDIV0 */
38#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
39#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
40#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
41#define S3C6400_CLKDIV0_HCLK2_SHIFT (9)
42#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8)
43#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
44#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
45#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
46
47#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0)
48#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0)
49#define S3C6400_CLKDIV0_ARM_SHIFT (0)
50
51/* HCLK GATE Registers */
52#define S3C_CLKCON_HCLK_3DSE (1<<31)
53#define S3C_CLKCON_HCLK_UHOST (1<<29)
54#define S3C_CLKCON_HCLK_SECUR (1<<28)
55#define S3C_CLKCON_HCLK_SDMA1 (1<<27)
56#define S3C_CLKCON_HCLK_SDMA0 (1<<26)
57#define S3C_CLKCON_HCLK_IROM (1<<25)
58#define S3C_CLKCON_HCLK_DDR1 (1<<24)
59#define S3C_CLKCON_HCLK_DDR0 (1<<23)
60#define S3C_CLKCON_HCLK_MEM1 (1<<22)
61#define S3C_CLKCON_HCLK_MEM0 (1<<21)
62#define S3C_CLKCON_HCLK_USB (1<<20)
63#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
64#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
65#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
66#define S3C_CLKCON_HCLK_MDP (1<<16)
67#define S3C_CLKCON_HCLK_DHOST (1<<15)
68#define S3C_CLKCON_HCLK_IHOST (1<<14)
69#define S3C_CLKCON_HCLK_DMA1 (1<<13)
70#define S3C_CLKCON_HCLK_DMA0 (1<<12)
71#define S3C_CLKCON_HCLK_JPEG (1<<11)
72#define S3C_CLKCON_HCLK_CAMIF (1<<10)
73#define S3C_CLKCON_HCLK_SCALER (1<<9)
74#define S3C_CLKCON_HCLK_2D (1<<8)
75#define S3C_CLKCON_HCLK_TV (1<<7)
76#define S3C_CLKCON_HCLK_POST0 (1<<5)
77#define S3C_CLKCON_HCLK_ROT (1<<4)
78#define S3C_CLKCON_HCLK_LCD (1<<3)
79#define S3C_CLKCON_HCLK_TZIC (1<<2)
80#define S3C_CLKCON_HCLK_INTC (1<<1)
81#define S3C_CLKCON_HCLK_MFC (1<<0)
82
83/* PCLK GATE Registers */
84#define S3C6410_CLKCON_PCLK_I2C1 (1<<27)
85#define S3C6410_CLKCON_PCLK_IIS2 (1<<26)
86#define S3C_CLKCON_PCLK_SKEY (1<<24)
87#define S3C_CLKCON_PCLK_CHIPID (1<<23)
88#define S3C_CLKCON_PCLK_SPI1 (1<<22)
89#define S3C_CLKCON_PCLK_SPI0 (1<<21)
90#define S3C_CLKCON_PCLK_HSIRX (1<<20)
91#define S3C_CLKCON_PCLK_HSITX (1<<19)
92#define S3C_CLKCON_PCLK_GPIO (1<<18)
93#define S3C_CLKCON_PCLK_IIC (1<<17)
94#define S3C_CLKCON_PCLK_IIS1 (1<<16)
95#define S3C_CLKCON_PCLK_IIS0 (1<<15)
96#define S3C_CLKCON_PCLK_AC97 (1<<14)
97#define S3C_CLKCON_PCLK_TZPC (1<<13)
98#define S3C_CLKCON_PCLK_TSADC (1<<12)
99#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
100#define S3C_CLKCON_PCLK_IRDA (1<<10)
101#define S3C_CLKCON_PCLK_PCM1 (1<<9)
102#define S3C_CLKCON_PCLK_PCM0 (1<<8)
103#define S3C_CLKCON_PCLK_PWM (1<<7)
104#define S3C_CLKCON_PCLK_RTC (1<<6)
105#define S3C_CLKCON_PCLK_WDT (1<<5)
106#define S3C_CLKCON_PCLK_UART3 (1<<4)
107#define S3C_CLKCON_PCLK_UART2 (1<<3)
108#define S3C_CLKCON_PCLK_UART1 (1<<2)
109#define S3C_CLKCON_PCLK_UART0 (1<<1)
110#define S3C_CLKCON_PCLK_MFC (1<<0)
111
112/* SCLK GATE Registers */
113#define S3C_CLKCON_SCLK_UHOST (1<<30)
114#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
115#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
116#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
117#define S3C_CLKCON_SCLK_MMC2 (1<<26)
118#define S3C_CLKCON_SCLK_MMC1 (1<<25)
119#define S3C_CLKCON_SCLK_MMC0 (1<<24)
120#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
121#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
122#define S3C_CLKCON_SCLK_SPI1 (1<<21)
123#define S3C_CLKCON_SCLK_SPI0 (1<<20)
124#define S3C_CLKCON_SCLK_DAC27 (1<<19)
125#define S3C_CLKCON_SCLK_TV27 (1<<18)
126#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
127#define S3C_CLKCON_SCLK_SCALER (1<<16)
128#define S3C_CLKCON_SCLK_LCD27 (1<<15)
129#define S3C_CLKCON_SCLK_LCD (1<<14)
130#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13)
131#define S3C6410_CLKCON_FIMC (1<<13)
132#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
133#define S3C6400_CLKCON_SCLK_POST1 (1<<11)
134#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11)
135#define S3C_CLKCON_SCLK_POST0 (1<<10)
136#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
137#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
138#define S3C_CLKCON_SCLK_SECUR (1<<7)
139#define S3C_CLKCON_SCLK_IRDA (1<<6)
140#define S3C_CLKCON_SCLK_UART (1<<5)
141#define S3C_CLKCON_SCLK_ONENAND (1<<4)
142#define S3C_CLKCON_SCLK_MFC (1<<3)
143#define S3C_CLKCON_SCLK_CAM (1<<2)
144#define S3C_CLKCON_SCLK_JPEG (1<<1)
145
146/* CLKSRC */
147
148#define S3C6400_CLKSRC_APLL_MOUT (1 << 0)
149#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1)
150#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2)
151#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
152#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
153#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
154#define S3C6400_CLKSRC_MFC (1 << 4)
16 155
156#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h b/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h
new file mode 100644
index 000000000000..82342f6fd27d
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h
@@ -0,0 +1,25 @@
1/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIO memory port register definitions
9 */
10
11#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
12#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
13
14#define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
15#define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
16
17#define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)
18#define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)
19#define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)
20
21#define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
22#define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
23
24#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
25
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..81f7f6e6832e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h
@@ -0,0 +1,187 @@
1/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIO register definitions
9 */
10
11#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
12#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
13
14/* Base addresses for each of the banks */
15
16#define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg))
17
18#define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)
19#define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)
20#define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)
21#define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)
22#define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)
23#define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)
24#define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)
25#define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)
26#define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)
27#define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)
28#define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800)
29#define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810)
30#define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820)
31#define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830)
32#define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140)
33#define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160)
34#define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180)
35
36/* SPCON */
37
38#define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0)
39
40#define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30)
41#define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30)
42#define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30)
43#define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30)
44#define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30)
45#define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30)
46
47#define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28)
48#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28)
49#define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28)
50#define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28)
51#define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28)
52#define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28)
53
54#define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26)
55#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26)
56#define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26)
57#define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26)
58#define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26)
59#define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26)
60
61#define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24)
62#define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24)
63#define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24)
64#define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24)
65#define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24)
66#define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24)
67
68#define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22)
69#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22)
70#define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22)
71#define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22)
72#define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22)
73#define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22)
74
75#define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21)
76
77#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18)
78#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18)
79#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18)
80#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18)
81#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18)
82#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18)
83
84#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16)
85#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16)
86#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16)
87#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16)
88#define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16)
89
90#define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14)
91#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14)
92#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14)
93#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14)
94#define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14)
95
96#define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12)
97#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12)
98#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12)
99#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12)
100#define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12)
101
102#define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8)
103#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8)
104#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8)
105#define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8)
106#define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8)
107
108#define S3C64XX_SPCON_USBH_DMPD (1 << 7)
109#define S3C64XX_SPCON_USBH_DPPD (1 << 6)
110#define S3C64XX_SPCON_USBH_PUSW2 (1 << 5)
111#define S3C64XX_SPCON_USBH_PUSW1 (1 << 4)
112#define S3C64XX_SPCON_USBH_SUSPND (1 << 3)
113
114#define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0)
115#define S3C64XX_SPCON_LCD_SEL_SHIFT (0)
116#define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0)
117#define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0)
118#define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0)
119
120
121/* External interrupt registers */
122
123#define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200)
124#define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204)
125#define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208)
126#define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C)
127#define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210)
128
129#define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220)
130#define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224)
131#define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228)
132#define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C)
133#define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230)
134
135#define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240)
136#define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244)
137#define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248)
138#define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C)
139#define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250)
140
141#define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260)
142#define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264)
143#define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268)
144#define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C)
145#define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270)
146
147#define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280)
148#define S3C64XX_PRIORITY_ARB(x) (1 << (x))
149
150#define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284)
151#define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288)
152
153#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
154#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
155#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
156#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
157#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
158#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
159
160#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
161#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
162
163/* GPIO sleep configuration */
164
165#define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880)
166
167#define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14)
168#define S3C64XX_SPCONSLP_CKE1INIT (1 << 5)
169
170#define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12)
171#define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12)
172#define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12)
173#define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12)
174
175#define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0)
176#define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0)
177#define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0)
178#define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0)
179
180
181#define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930)
182
183#define S3C64XX_SLPEN_USE_xSLP (1 << 0)
184#define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1)
185
186#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
187
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-modem.h b/arch/arm/mach-s3c64xx/include/mach/regs-modem.h
new file mode 100644
index 000000000000..49f7759dedfa
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-modem.h
@@ -0,0 +1,31 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - modem block registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_MODEM_H
16#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
17
18#define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x))
19
20#define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0)
21#define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4)
22#define S3C64XX_MODEM_MIFCON S3C64XX_MODEMREG(0x8)
23#define S3C64XX_MODEM_MIFPCON S3C64XX_MODEMREG(0xC)
24#define S3C64XX_MODEM_INTCLR S3C64XX_MODEMREG(0x10)
25#define S3C64XX_MODEM_DMA_TXADDR S3C64XX_MODEMREG(0x14)
26#define S3C64XX_MODEM_DMA_RXADDR S3C64XX_MODEMREG(0x18)
27
28#define MIFPCON_INT2M_LEVEL (1 << 4)
29#define MIFPCON_LCD_BYPASS (1 << 3)
30
31#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-srom.h b/arch/arm/mach-s3c64xx/include/mach/regs-srom.h
new file mode 100644
index 000000000000..756731b36297
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-srom.h
@@ -0,0 +1,59 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
2 *
3 * Copyright 2009 Andy Green <andy@warmcat.com>
4 *
5 * S3C64XX SROM definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __PLAT_REGS_SROM_H
13#define __PLAT_REGS_SROM_H __FILE__
14
15#define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x))
16
17#define S3C64XX_SROM_BW S3C64XX_SROMREG(0)
18#define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4)
19#define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8)
20#define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc)
21#define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10)
22#define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14)
23#define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18)
24
25/*
26 * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
27 */
28
29#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0
30#define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2
31#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3
32#define S3C64XX_SROM_BW__CS_MASK 0xf
33
34#define S3C64XX_SROM_BW__NCS0__SHIFT 0
35#define S3C64XX_SROM_BW__NCS1__SHIFT 4
36#define S3C64XX_SROM_BW__NCS2__SHIFT 8
37#define S3C64XX_SROM_BW__NCS3__SHIFT 0xc
38#define S3C64XX_SROM_BW__NCS4__SHIFT 0x10
39
40/*
41 * applies to same to BCS0 - BCS4
42 */
43
44#define S3C64XX_SROM_BCX__PMC__SHIFT 0
45#define S3C64XX_SROM_BCX__PMC__MASK 3
46#define S3C64XX_SROM_BCX__TACP__SHIFT 4
47#define S3C64XX_SROM_BCX__TACP__MASK 0xf
48#define S3C64XX_SROM_BCX__TCAH__SHIFT 8
49#define S3C64XX_SROM_BCX__TCAH__MASK 0xf
50#define S3C64XX_SROM_BCX__TCOH__SHIFT 12
51#define S3C64XX_SROM_BCX__TCOH__MASK 0xf
52#define S3C64XX_SROM_BCX__TACC__SHIFT 16
53#define S3C64XX_SROM_BCX__TACC__MASK 0x1f
54#define S3C64XX_SROM_BCX__TCOS__SHIFT 24
55#define S3C64XX_SROM_BCX__TCOS__MASK 0xf
56#define S3C64XX_SROM_BCX__TACS__SHIFT 28
57#define S3C64XX_SROM_BCX__TACS__MASK 0xf
58
59#endif /* _PLAT_REGS_SROM_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
new file mode 100644
index 000000000000..69b78d9f83b8
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
@@ -0,0 +1,28 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX system register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_REGS_SYS_H
16#define __PLAT_REGS_SYS_H __FILE__
17
18#define S3C_SYSREG(x) (S3C_VA_SYS + (x))
19
20#define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
21#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
22#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
23
24#define S3C64XX_OTHERS S3C_SYSREG(0x900)
25
26#define S3C64XX_OTHERS_USBMASK (1 << 16)
27
28#endif /* _PLAT_REGS_SYS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h b/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h
new file mode 100644
index 000000000000..270d96ac9705
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h
@@ -0,0 +1,116 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - syscon power and sleep control registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
16#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
17
18#define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
19
20#define S3C64XX_PWRCFG_OSC_OTG_DISABLE (1 << 17)
21#define S3C64XX_PWRCFG_MMC2_DISABLE (1 << 16)
22#define S3C64XX_PWRCFG_MMC1_DISABLE (1 << 15)
23#define S3C64XX_PWRCFG_MMC0_DISABLE (1 << 14)
24#define S3C64XX_PWRCFG_HSI_DISABLE (1 << 13)
25#define S3C64XX_PWRCFG_TS_DISABLE (1 << 12)
26#define S3C64XX_PWRCFG_RTC_TICK_DISABLE (1 << 11)
27#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE (1 << 10)
28#define S3C64XX_PWRCFG_MSM_DISABLE (1 << 9)
29#define S3C64XX_PWRCFG_KEY_DISABLE (1 << 8)
30#define S3C64XX_PWRCFG_BATF_DISABLE (1 << 7)
31
32#define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5)
33#define S3C64XX_PWRCFG_CFG_WFI_SHIFT (5)
34#define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5)
35#define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5)
36#define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5)
37#define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5)
38
39#define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3)
40#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT (3)
41#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3)
42#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3)
43#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3)
44
45#define S3C64XX_PWRCFG_CFG_BAT_WAKE (1 << 2)
46#define S3C64XX_PWRCFG_OSC27_EN (1 << 0)
47
48#define S3C64XX_EINT_MASK S3C_SYSREG(0x808)
49
50#define S3C64XX_NORMAL_CFG S3C_SYSREG(0x810)
51
52#define S3C64XX_NORMALCFG_IROM_ON (1 << 30)
53#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON (1 << 16)
54#define S3C64XX_NORMALCFG_DOMAIN_S_ON (1 << 15)
55#define S3C64XX_NORMALCFG_DOMAIN_F_ON (1 << 14)
56#define S3C64XX_NORMALCFG_DOMAIN_P_ON (1 << 13)
57#define S3C64XX_NORMALCFG_DOMAIN_I_ON (1 << 12)
58#define S3C64XX_NORMALCFG_DOMAIN_G_ON (1 << 10)
59#define S3C64XX_NORMALCFG_DOMAIN_V_ON (1 << 9)
60
61#define S3C64XX_STOP_CFG S3C_SYSREG(0x814)
62
63#define S3C64XX_STOPCFG_MEMORY_ARM_ON (1 << 29)
64#define S3C64XX_STOPCFG_TOP_MEMORY_ON (1 << 20)
65#define S3C64XX_STOPCFG_ARM_LOGIC_ON (1 << 17)
66#define S3C64XX_STOPCFG_TOP_LOGIC_ON (1 << 8)
67#define S3C64XX_STOPCFG_OSC_EN (1 << 0)
68
69#define S3C64XX_SLEEP_CFG S3C_SYSREG(0x818)
70
71#define S3C64XX_SLEEPCFG_OSC_EN (1 << 0)
72
73#define S3C64XX_STOP_MEM_CFG S3C_SYSREG(0x81c)
74
75#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN (1 << 6)
76#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN (1 << 5)
77#define S3C64XX_STOPMEMCFG_OTG_RETAIN (1 << 4)
78#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN (1 << 3)
79#define S3C64XX_STOPMEMCFG_IROM_RETAIN (1 << 2)
80#define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1)
81#define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0)
82
83#define S3C64XX_OSC_STABLE S3C_SYSREG(0x824)
84#define S3C64XX_PWR_STABLE S3C_SYSREG(0x828)
85
86#define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908)
87
88#define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11)
89#define S3C64XX_WAKEUPSTAT_MMC1 (1 << 10)
90#define S3C64XX_WAKEUPSTAT_MMC0 (1 << 9)
91#define S3C64XX_WAKEUPSTAT_HSI (1 << 8)
92#define S3C64XX_WAKEUPSTAT_BATFLT (1 << 6)
93#define S3C64XX_WAKEUPSTAT_MSM (1 << 5)
94#define S3C64XX_WAKEUPSTAT_KEY (1 << 4)
95#define S3C64XX_WAKEUPSTAT_TS (1 << 3)
96#define S3C64XX_WAKEUPSTAT_RTC_TICK (1 << 2)
97#define S3C64XX_WAKEUPSTAT_RTC_ALARM (1 << 1)
98#define S3C64XX_WAKEUPSTAT_EINT (1 << 0)
99
100#define S3C64XX_BLK_PWR_STAT S3C_SYSREG(0x90c)
101
102#define S3C64XX_BLKPWRSTAT_G (1 << 7)
103#define S3C64XX_BLKPWRSTAT_ETM (1 << 6)
104#define S3C64XX_BLKPWRSTAT_S (1 << 5)
105#define S3C64XX_BLKPWRSTAT_F (1 << 4)
106#define S3C64XX_BLKPWRSTAT_P (1 << 3)
107#define S3C64XX_BLKPWRSTAT_I (1 << 2)
108#define S3C64XX_BLKPWRSTAT_V (1 << 1)
109#define S3C64XX_BLKPWRSTAT_TOP (1 << 0)
110
111#define S3C64XX_INFORM0 S3C_SYSREG(0xA00)
112#define S3C64XX_INFORM1 S3C_SYSREG(0xA04)
113#define S3C64XX_INFORM2 S3C_SYSREG(0xA08)
114#define S3C64XX_INFORM3 S3C_SYSREG(0xA0C)
115
116#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 49032a85f6f8..06d8fe579e10 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -49,8 +49,8 @@
49#include <plat/clock.h> 49#include <plat/clock.h>
50#include <plat/devs.h> 50#include <plat/devs.h>
51#include <plat/cpu.h> 51#include <plat/cpu.h>
52#include <plat/regs-gpio.h> 52#include <mach/regs-gpio.h>
53#include <plat/regs-modem.h> 53#include <mach/regs-modem.h>
54 54
55/* DM9000 */ 55/* DM9000 */
56#define ANW6410_PA_DM9000 (0x18000000) 56#define ANW6410_PA_DM9000 (0x18000000)
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 6e6ff354da42..021670e39d3e 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -46,10 +46,10 @@
46#include <asm/mach-types.h> 46#include <asm/mach-types.h>
47 47
48#include <plat/regs-serial.h> 48#include <plat/regs-serial.h>
49#include <plat/regs-modem.h> 49#include <mach/regs-modem.h>
50#include <plat/regs-gpio.h> 50#include <mach/regs-gpio.h>
51#include <plat/regs-sys.h> 51#include <mach/regs-sys.h>
52#include <plat/regs-srom.h> 52#include <mach/regs-srom.h>
53#include <plat/iic.h> 53#include <plat/iic.h>
54#include <plat/fb.h> 54#include <plat/fb.h>
55#include <plat/gpio-cfg.h> 55#include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 884858a78d49..2fba1b263fed 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -30,7 +30,7 @@
30 30
31#include <plat/cpu-freq.h> 31#include <plat/cpu-freq.h>
32#include <plat/regs-serial.h> 32#include <plat/regs-serial.h>
33#include <plat/regs-clock.h> 33#include <mach/regs-clock.h>
34 34
35#include <plat/cpu.h> 35#include <plat/cpu.h>
36#include <plat/devs.h> 36#include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 185f15cbb701..b881d6a50b11 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -31,7 +31,7 @@
31 31
32#include <plat/cpu-freq.h> 32#include <plat/cpu-freq.h>
33#include <plat/regs-serial.h> 33#include <plat/regs-serial.h>
34#include <plat/regs-clock.h> 34#include <mach/regs-clock.h>
35 35
36#include <plat/cpu.h> 36#include <plat/cpu.h>
37#include <plat/devs.h> 37#include <plat/devs.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 00:52:57 -0500