diff options
author | Ben Dooks <ben-linux@fluff.org> | 2010-10-01 03:39:15 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-22 22:50:05 -0400 |
commit | dab30d7f80d7a81ac736c590a81249d2fd323c62 (patch) | |
tree | d8262114fb998451b933615859d2389a11060179 /arch/arm/mach-s3c64xx/setup-sdhci-gpio.c | |
parent | 5459148b098e3bbdc24376f1865045189a80a0af (diff) |
ARM: S3C64XX: Change to using s3c_gpio_cfgall_range()
Change the code setting a range of GPIO pins' configuration and
pull state to use the recently introduced s3c_gpio_cfgall_range().
Mop up a few missed s3c_gpio_cfgpin_range() changes.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
[kgene.kim@samsung.com: Fix small comments]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c64xx/setup-sdhci-gpio.c')
-rw-r--r-- | arch/arm/mach-s3c64xx/setup-sdhci-gpio.c | 45 |
1 files changed, 12 insertions, 33 deletions
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c index 0655c7a9bd34..4262f78a93ca 100644 --- a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c +++ b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c | |||
@@ -24,16 +24,10 @@ | |||
24 | void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) | 24 | void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) |
25 | { | 25 | { |
26 | struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; | 26 | struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; |
27 | unsigned int gpio; | ||
28 | unsigned int end; | ||
29 | 27 | ||
30 | end = S3C64XX_GPG(2 + width); | 28 | /* Set all the necessary GPG pins to special-function 2 */ |
31 | 29 | s3c_gpio_cfgall_range(S3C64XX_GPG(0), 2 + width, | |
32 | /* Set all the necessary GPG pins to special-function 0 */ | 30 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); |
33 | s3c_gpio_cfgpin_range(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2)); | ||
34 | for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) { | ||
35 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
36 | } | ||
37 | 31 | ||
38 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { | 32 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { |
39 | s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); | 33 | s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); |
@@ -44,16 +38,10 @@ void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) | |||
44 | void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) | 38 | void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) |
45 | { | 39 | { |
46 | struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; | 40 | struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; |
47 | unsigned int gpio; | ||
48 | unsigned int end; | ||
49 | 41 | ||
50 | end = S3C64XX_GPH(2 + width); | 42 | /* Set all the necessary GPH pins to special-function 2 */ |
51 | 43 | s3c_gpio_cfgall_range(S3C64XX_GPH(0), 2 + width, | |
52 | /* Set all the necessary GPG pins to special-function 0 */ | 44 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); |
53 | s3c_gpio_cfgpin_range(S3C64XX_GPH(0), 2 + width, S3C_GPIO_SFN(2)); | ||
54 | for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { | ||
55 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
56 | } | ||
57 | 45 | ||
58 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { | 46 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { |
59 | s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); | 47 | s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); |
@@ -63,20 +51,11 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) | |||
63 | 51 | ||
64 | void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) | 52 | void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) |
65 | { | 53 | { |
66 | unsigned int gpio; | 54 | /* Set all the necessary GPH pins to special-function 3 */ |
67 | unsigned int end; | 55 | s3c_gpio_cfgall_range(S3C64XX_GPH(6), width, |
56 | S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE); | ||
68 | 57 | ||
69 | end = S3C64XX_GPH(6 + width); | 58 | /* Set all the necessary GPC pins to special-function 3 */ |
70 | 59 | s3c_gpio_cfgall_range(S3C64XX_GPC(4), 2, | |
71 | /* Set all the necessary GPH pins to special-function 1 */ | 60 | S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE); |
72 | s3c_gpio_cfgpin_range(S3C64XX_GPH(6), width, S3C_GPIO_SFN(3)); | ||
73 | for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) { | ||
74 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
75 | } | ||
76 | |||
77 | /* Set all the necessary GPC pins to special-function 1 */ | ||
78 | s3c_gpio_cfgpin_range(S3C64XX_GPC(4), 2, S3C_GPIO_SFN(3)); | ||
79 | for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) { | ||
80 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
81 | } | ||
82 | } | 61 | } |