aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s3c24xx
diff options
context:
space:
mode:
authorKukjin Kim <kgene.kim@samsung.com>2012-02-05 23:21:03 -0500
committerKukjin Kim <kgene.kim@samsung.com>2012-03-02 18:55:54 -0500
commit84c028b9cebd928cf434b27093fa65f7b4b81cfe (patch)
tree9451edaa92cf44112e80d6bf5dc057d913122163 /arch/arm/mach-s3c24xx
parentdd6f01b5ccba602cf0790bc44cc4429013373719 (diff)
ARM: S3C2443: move mach-s3c2443/* into mach-s3c24xx/
This patch moves S3C2443 stuff into mach-s3c24xx/ directory so that we can merge the s3c24 series' directories to the just one mach-s3c24xx/ directory. Cc: Ben Dooks <ben-linux@fluff.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c24xx')
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig29
-rw-r--r--arch/arm/mach-s3c24xx/Makefile5
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2443.c222
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2443.c155
-rw-r--r--arch/arm/mach-s3c24xx/irq-s3c2443.c280
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2443.c149
-rw-r--r--arch/arm/mach-s3c24xx/s3c2443.c114
7 files changed, 954 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index d8d156c0881c..44b2a3212d29 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -70,6 +70,17 @@ config CPU_S3C244X
70 def_bool y 70 def_bool y
71 depends on CPU_S3C2440 || CPU_S3C2442 71 depends on CPU_S3C2440 || CPU_S3C2442
72 72
73config CPU_S3C2443
74 bool "SAMSUNG S3C2443"
75 depends on ARCH_S3C24XX
76 select CPU_ARM920T
77 select CPU_LLSERIAL_S3C2440
78 select SAMSUNG_CLKSRC
79 select S3C2443_CLOCK
80 select S3C2443_DMA if S3C24XX_DMA
81 help
82 Support for the S3C2443 SoC from the S3C24XX line
83
73if CPU_S3C2410 84if CPU_S3C2410
74 85
75config S3C2410_DMA 86config S3C2410_DMA
@@ -460,6 +471,24 @@ config SMDK2440_CPU2442
460 471
461endif # CPU_S3C2440 472endif # CPU_S3C2440
462 473
474if CPU_S3C2443
475
476config S3C2443_DMA
477 bool
478 help
479 Internal config node for S3C2443 DMA support
480
481comment "S3C2443 Boards"
482
483config MACH_SMDK2443
484 bool "SMDK2443"
485 select MACH_SMDK
486 select S3C_DEV_HSMMC1
487 help
488 Say Y here if you are using an SMDK2443
489
490endif # CPU_S3C2443
491
463endmenu # SAMSUNG S3C24XX SoCs Support 492endmenu # SAMSUNG S3C24XX SoCs Support
464 493
465endif # ARCH_S3C24XX 494endif # ARCH_S3C24XX
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index f458cf2e1dd8..08b44a3ab858 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -31,6 +31,9 @@ obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
31obj-$(CONFIG_CPU_S3C244X) += s3c244x.o irq-s3c244x.o clock-s3c244x.o 31obj-$(CONFIG_CPU_S3C244X) += s3c244x.o irq-s3c244x.o clock-s3c244x.o
32obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o 32obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o
33 33
34obj-$(CONFIG_CPU_S3C2443) += s3c2443.o irq-s3c2443.o clock-s3c2443.o
35obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o
36
34# 37#
35# machine support 38# machine support
36# following is ordered alphabetically by option text. 39# following is ordered alphabetically by option text.
@@ -66,6 +69,8 @@ obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
66obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o 69obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
67obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o 70obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o
68 71
72obj-$(CONFIG_MACH_SMDK2443) += mach-smdk2443.o
73
69# common bits of machine support 74# common bits of machine support
70 75
71obj-$(CONFIG_SIMTEC_NOR) += nor-simtec.o 76obj-$(CONFIG_SIMTEC_NOR) += nor-simtec.o
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
new file mode 100644
index 000000000000..6dde2696f8f0
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -0,0 +1,222 @@
1/* linux/arch/arm/mach-s3c2443/clock.c
2 *
3 * Copyright (c) 2007, 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/clk.h>
32#include <linux/mutex.h>
33#include <linux/serial_core.h>
34#include <linux/io.h>
35
36#include <asm/mach/map.h>
37
38#include <mach/hardware.h>
39
40#include <mach/regs-s3c2443-clock.h>
41
42#include <plat/cpu-freq.h>
43
44#include <plat/s3c2443.h>
45#include <plat/clock.h>
46#include <plat/clock-clksrc.h>
47#include <plat/cpu.h>
48
49/* We currently have to assume that the system is running
50 * from the XTPll input, and that all ***REFCLKs are being
51 * fed from it, as we cannot read the state of OM[4] from
52 * software.
53 *
54 * It would be possible for each board initialisation to
55 * set the correct muxing at initialisation
56*/
57
58/* clock selections */
59
60/* armdiv
61 *
62 * this clock is sourced from msysclk and can have a number of
63 * divider values applied to it to then be fed into armclk.
64 * The real clock definition is done in s3c2443-clock.c,
65 * only the armdiv divisor table must be defined here.
66*/
67
68static unsigned int armdiv[16] = {
69 [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
70 [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
71 [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
72 [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
73 [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
74 [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
75 [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
76 [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
77};
78
79/* hsspi
80 *
81 * high-speed spi clock, sourced from esysclk
82*/
83
84static struct clksrc_clk clk_hsspi = {
85 .clk = {
86 .name = "hsspi-if",
87 .parent = &clk_esysclk.clk,
88 .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
89 .enable = s3c2443_clkcon_enable_s,
90 },
91 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
92};
93
94
95/* clk_hsmcc_div
96 *
97 * this clock is sourced from epll, and is fed through a divider,
98 * to a mux controlled by sclkcon where either it or a extclk can
99 * be fed to the hsmmc block
100*/
101
102static struct clksrc_clk clk_hsmmc_div = {
103 .clk = {
104 .name = "hsmmc-div",
105 .devname = "s3c-sdhci.1",
106 .parent = &clk_esysclk.clk,
107 },
108 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
109};
110
111static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
112{
113 unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
114
115 clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
116 S3C2443_SCLKCON_HSMMCCLK_EPLL);
117
118 if (parent == &clk_epll)
119 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
120 else if (parent == &clk_ext)
121 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
122 else
123 return -EINVAL;
124
125 if (clk->usage > 0) {
126 __raw_writel(clksrc, S3C2443_SCLKCON);
127 }
128
129 clk->parent = parent;
130 return 0;
131}
132
133static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
134{
135 return s3c2443_setparent_hsmmc(clk, clk->parent);
136}
137
138static struct clk clk_hsmmc = {
139 .name = "hsmmc-if",
140 .devname = "s3c-sdhci.1",
141 .parent = &clk_hsmmc_div.clk,
142 .enable = s3c2443_enable_hsmmc,
143 .ops = &(struct clk_ops) {
144 .set_parent = s3c2443_setparent_hsmmc,
145 },
146};
147
148/* standard clock definitions */
149
150static struct clk init_clocks_off[] = {
151 {
152 .name = "sdi",
153 .parent = &clk_p,
154 .enable = s3c2443_clkcon_enable_p,
155 .ctrlbit = S3C2443_PCLKCON_SDI,
156 }, {
157 .name = "spi",
158 .devname = "s3c2410-spi.0",
159 .parent = &clk_p,
160 .enable = s3c2443_clkcon_enable_p,
161 .ctrlbit = S3C2443_PCLKCON_SPI0,
162 }, {
163 .name = "spi",
164 .devname = "s3c2410-spi.1",
165 .parent = &clk_p,
166 .enable = s3c2443_clkcon_enable_p,
167 .ctrlbit = S3C2443_PCLKCON_SPI1,
168 }
169};
170
171/* clocks to add straight away */
172
173static struct clksrc_clk *clksrcs[] __initdata = {
174 &clk_hsspi,
175 &clk_hsmmc_div,
176};
177
178static struct clk *clks[] __initdata = {
179 &clk_hsmmc,
180};
181
182void __init_or_cpufreq s3c2443_setup_clocks(void)
183{
184 s3c2443_common_setup_clocks(s3c2443_get_mpll);
185}
186
187void __init s3c2443_init_clocks(int xtal)
188{
189 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
190 int ptr;
191
192 clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
193 clk_epll.parent = &clk_epllref.clk;
194
195 s3c2443_common_init_clocks(xtal, s3c2443_get_mpll,
196 armdiv, ARRAY_SIZE(armdiv),
197 S3C2443_CLKDIV0_ARMDIV_MASK);
198
199 s3c2443_setup_clocks();
200
201 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
202
203 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
204 s3c_register_clksrc(clksrcs[ptr], 1);
205
206 /* We must be careful disabling the clocks we are not intending to
207 * be using at boot time, as subsystems such as the LCD which do
208 * their own DMA requests to the bus can cause the system to lockup
209 * if they where in the middle of requesting bus access.
210 *
211 * Disabling the LCD clock if the LCD is active is very dangerous,
212 * and therefore the bootloader should be careful to not enable
213 * the LCD clock if it is not needed.
214 */
215
216 /* install (and disable) the clocks we do not need immediately */
217
218 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
219 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
220
221 s3c_pwmclk_init();
222}
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
new file mode 100644
index 000000000000..de6b4a23c9ed
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -0,0 +1,155 @@
1/* linux/arch/arm/mach-s3c2443/dma.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/serial_core.h>
19#include <linux/io.h>
20
21#include <mach/dma.h>
22
23#include <plat/dma-s3c24xx.h>
24#include <plat/cpu.h>
25
26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h>
34#include <plat/regs-spi.h>
35
36#define MAP(x) { \
37 [0] = (x) | DMA_CH_VALID, \
38 [1] = (x) | DMA_CH_VALID, \
39 [2] = (x) | DMA_CH_VALID, \
40 [3] = (x) | DMA_CH_VALID, \
41 [4] = (x) | DMA_CH_VALID, \
42 [5] = (x) | DMA_CH_VALID, \
43 }
44
45static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
46 [DMACH_XD0] = {
47 .name = "xdreq0",
48 .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
49 },
50 [DMACH_XD1] = {
51 .name = "xdreq1",
52 .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
53 },
54 [DMACH_SDI] = {
55 .name = "sdi",
56 .channels = MAP(S3C2443_DMAREQSEL_SDI),
57 },
58 [DMACH_SPI0] = {
59 .name = "spi0",
60 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
61 },
62 [DMACH_SPI1] = {
63 .name = "spi1",
64 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
65 },
66 [DMACH_UART0] = {
67 .name = "uart0",
68 .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
69 },
70 [DMACH_UART1] = {
71 .name = "uart1",
72 .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
73 },
74 [DMACH_UART2] = {
75 .name = "uart2",
76 .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
77 },
78 [DMACH_UART3] = {
79 .name = "uart3",
80 .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
81 },
82 [DMACH_UART0_SRC2] = {
83 .name = "uart0",
84 .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
85 },
86 [DMACH_UART1_SRC2] = {
87 .name = "uart1",
88 .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
89 },
90 [DMACH_UART2_SRC2] = {
91 .name = "uart2",
92 .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
93 },
94 [DMACH_UART3_SRC2] = {
95 .name = "uart3",
96 .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
97 },
98 [DMACH_TIMER] = {
99 .name = "timer",
100 .channels = MAP(S3C2443_DMAREQSEL_TIMER),
101 },
102 [DMACH_I2S_IN] = {
103 .name = "i2s-sdi",
104 .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
105 },
106 [DMACH_I2S_OUT] = {
107 .name = "i2s-sdo",
108 .channels = MAP(S3C2443_DMAREQSEL_I2STX),
109 },
110 [DMACH_PCM_IN] = {
111 .name = "pcm-in",
112 .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
113 },
114 [DMACH_PCM_OUT] = {
115 .name = "pcm-out",
116 .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
117 },
118 [DMACH_MIC_IN] = {
119 .name = "mic-in",
120 .channels = MAP(S3C2443_DMAREQSEL_MICIN),
121 },
122};
123
124static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
125 struct s3c24xx_dma_map *map)
126{
127 writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
128 chan->regs + S3C2443_DMA_DMAREQSEL);
129}
130
131static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
132 .select = s3c2443_dma_select,
133 .dcon_mask = 0,
134 .map = s3c2443_dma_mappings,
135 .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
136};
137
138static int __init s3c2443_dma_add(struct device *dev)
139{
140 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
141 return s3c24xx_dma_init_map(&s3c2443_dma_sel);
142}
143
144static struct subsys_interface s3c2443_dma_interface = {
145 .name = "s3c2443_dma",
146 .subsys = &s3c2443_subsys,
147 .add_dev = s3c2443_dma_add,
148};
149
150static int __init s3c2443_dma_init(void)
151{
152 return subsys_interface_register(&s3c2443_dma_interface);
153}
154
155arch_initcall(s3c2443_dma_init);
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
new file mode 100644
index 000000000000..35e4ff24fb43
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/irq-s3c2443.c
@@ -0,0 +1,280 @@
1/* linux/arch/arm/mach-s3c2443/irq.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/device.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h>
36
37#include <plat/cpu.h>
38#include <plat/pm.h>
39#include <plat/irq.h>
40
41#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
42
43static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
44{
45 unsigned int subsrc, submsk;
46 unsigned int end;
47
48 /* read the current pending interrupts, and the mask
49 * for what it is available */
50
51 subsrc = __raw_readl(S3C2410_SUBSRCPND);
52 submsk = __raw_readl(S3C2410_INTSUBMSK);
53
54 subsrc &= ~submsk;
55 subsrc >>= (irq - S3C2410_IRQSUB(0));
56 subsrc &= (1 << len)-1;
57
58 end = len + irq;
59
60 for (; irq < end && subsrc; irq++) {
61 if (subsrc & 1)
62 generic_handle_irq(irq);
63
64 subsrc >>= 1;
65 }
66}
67
68/* WDT/AC97 sub interrupts */
69
70static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
71{
72 s3c2443_irq_demux(IRQ_S3C2443_WDT, 4);
73}
74
75#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
76#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
77
78static void s3c2443_irq_wdtac97_mask(struct irq_data *data)
79{
80 s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
81}
82
83static void s3c2443_irq_wdtac97_unmask(struct irq_data *data)
84{
85 s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
86}
87
88static void s3c2443_irq_wdtac97_ack(struct irq_data *data)
89{
90 s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
91}
92
93static struct irq_chip s3c2443_irq_wdtac97 = {
94 .irq_mask = s3c2443_irq_wdtac97_mask,
95 .irq_unmask = s3c2443_irq_wdtac97_unmask,
96 .irq_ack = s3c2443_irq_wdtac97_ack,
97};
98
99/* LCD sub interrupts */
100
101static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
102{
103 s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4);
104}
105
106#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
107#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
108
109static void s3c2443_irq_lcd_mask(struct irq_data *data)
110{
111 s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
112}
113
114static void s3c2443_irq_lcd_unmask(struct irq_data *data)
115{
116 s3c_irqsub_unmask(data->irq, INTMSK_LCD);
117}
118
119static void s3c2443_irq_lcd_ack(struct irq_data *data)
120{
121 s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
122}
123
124static struct irq_chip s3c2443_irq_lcd = {
125 .irq_mask = s3c2443_irq_lcd_mask,
126 .irq_unmask = s3c2443_irq_lcd_unmask,
127 .irq_ack = s3c2443_irq_lcd_ack,
128};
129
130/* DMA sub interrupts */
131
132static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
133{
134 s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6);
135}
136
137#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
138#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
139
140static void s3c2443_irq_dma_mask(struct irq_data *data)
141{
142 s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
143}
144
145static void s3c2443_irq_dma_unmask(struct irq_data *data)
146{
147 s3c_irqsub_unmask(data->irq, INTMSK_DMA);
148}
149
150static void s3c2443_irq_dma_ack(struct irq_data *data)
151{
152 s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
153}
154
155static struct irq_chip s3c2443_irq_dma = {
156 .irq_mask = s3c2443_irq_dma_mask,
157 .irq_unmask = s3c2443_irq_dma_unmask,
158 .irq_ack = s3c2443_irq_dma_ack,
159};
160
161/* UART3 sub interrupts */
162
163static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
164{
165 s3c2443_irq_demux(IRQ_S3C2443_RX3, 3);
166}
167
168#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
169#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
170
171static void s3c2443_irq_uart3_mask(struct irq_data *data)
172{
173 s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
174}
175
176static void s3c2443_irq_uart3_unmask(struct irq_data *data)
177{
178 s3c_irqsub_unmask(data->irq, INTMSK_UART3);
179}
180
181static void s3c2443_irq_uart3_ack(struct irq_data *data)
182{
183 s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
184}
185
186static struct irq_chip s3c2443_irq_uart3 = {
187 .irq_mask = s3c2443_irq_uart3_mask,
188 .irq_unmask = s3c2443_irq_uart3_unmask,
189 .irq_ack = s3c2443_irq_uart3_ack,
190};
191
192/* CAM sub interrupts */
193
194static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
195{
196 s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4);
197}
198
199#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
200#define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
201
202static void s3c2443_irq_cam_mask(struct irq_data *data)
203{
204 s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM);
205}
206
207static void s3c2443_irq_cam_unmask(struct irq_data *data)
208{
209 s3c_irqsub_unmask(data->irq, INTMSK_CAM);
210}
211
212static void s3c2443_irq_cam_ack(struct irq_data *data)
213{
214 s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM);
215}
216
217static struct irq_chip s3c2443_irq_cam = {
218 .irq_mask = s3c2443_irq_cam_mask,
219 .irq_unmask = s3c2443_irq_cam_unmask,
220 .irq_ack = s3c2443_irq_cam_ack,
221};
222
223/* IRQ initialisation code */
224
225static int __init s3c2443_add_sub(unsigned int base,
226 void (*demux)(unsigned int,
227 struct irq_desc *),
228 struct irq_chip *chip,
229 unsigned int start, unsigned int end)
230{
231 unsigned int irqno;
232
233 irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
234 irq_set_chained_handler(base, demux);
235
236 for (irqno = start; irqno <= end; irqno++) {
237 irq_set_chip_and_handler(irqno, chip, handle_level_irq);
238 set_irq_flags(irqno, IRQF_VALID);
239 }
240
241 return 0;
242}
243
244static int __init s3c2443_irq_add(struct device *dev)
245{
246 printk("S3C2443: IRQ Support\n");
247
248 s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam,
249 IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P);
250
251 s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd,
252 IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4);
253
254 s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma,
255 &s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
256
257 s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3,
258 &s3c2443_irq_uart3,
259 IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
260
261 s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97,
262 &s3c2443_irq_wdtac97,
263 IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
264
265 return 0;
266}
267
268static struct subsys_interface s3c2443_irq_interface = {
269 .name = "s3c2443_irq",
270 .subsys = &s3c2443_subsys,
271 .add_dev = s3c2443_irq_add,
272};
273
274static int __init s3c2443_irq_init(void)
275{
276 return subsys_interface_register(&s3c2443_irq_interface);
277}
278
279arch_initcall(s3c2443_irq_init);
280
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
new file mode 100644
index 000000000000..209236956222
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -0,0 +1,149 @@
1/* linux/arch/arm/mach-s3c2443/mach-smdk2443.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.fluff.org/ben/smdk2443/
7 *
8 * Thanks to Samsung for the loan of an SMDK2443
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <asm/irq.h>
32#include <asm/mach-types.h>
33
34#include <plat/regs-serial.h>
35#include <mach/regs-gpio.h>
36#include <mach/regs-lcd.h>
37
38#include <mach/idle.h>
39#include <mach/fb.h>
40#include <plat/iic.h>
41
42#include <plat/s3c2410.h>
43#include <plat/s3c2443.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47
48#include <plat/common-smdk.h>
49
50static struct map_desc smdk2443_iodesc[] __initdata = {
51 /* ISA IO Space map (memory space selected by A24) */
52
53 {
54 .virtual = (u32)S3C24XX_VA_ISA_WORD,
55 .pfn = __phys_to_pfn(S3C2410_CS2),
56 .length = 0x10000,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
60 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
61 .length = SZ_4M,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
65 .pfn = __phys_to_pfn(S3C2410_CS2),
66 .length = 0x10000,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
70 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
71 .length = SZ_4M,
72 .type = MT_DEVICE,
73 }
74};
75
76#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
77#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
78#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
79
80static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
81 [0] = {
82 .hwport = 0,
83 .flags = 0,
84 .ucon = 0x3c5,
85 .ulcon = 0x03,
86 .ufcon = 0x51,
87 },
88 [1] = {
89 .hwport = 1,
90 .flags = 0,
91 .ucon = 0x3c5,
92 .ulcon = 0x03,
93 .ufcon = 0x51,
94 },
95 /* IR port */
96 [2] = {
97 .hwport = 2,
98 .flags = 0,
99 .ucon = 0x3c5,
100 .ulcon = 0x43,
101 .ufcon = 0x51,
102 },
103 [3] = {
104 .hwport = 3,
105 .flags = 0,
106 .ucon = 0x3c5,
107 .ulcon = 0x03,
108 .ufcon = 0x51,
109 }
110};
111
112static struct platform_device *smdk2443_devices[] __initdata = {
113 &s3c_device_wdt,
114 &s3c_device_i2c0,
115 &s3c_device_hsmmc1,
116#ifdef CONFIG_SND_SOC_SMDK2443_WM9710
117 &s3c_device_ac97,
118#endif
119};
120
121static void __init smdk2443_map_io(void)
122{
123 s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
124 s3c24xx_init_clocks(12000000);
125 s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
126}
127
128static void __init smdk2443_machine_init(void)
129{
130 s3c_i2c0_set_platdata(NULL);
131
132#ifdef CONFIG_SND_SOC_SMDK2443_WM9710
133 s3c24xx_ac97_setup_gpio(S3C24XX_AC97_GPE0);
134#endif
135
136 platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
137 smdk_machine_init();
138}
139
140MACHINE_START(SMDK2443, "SMDK2443")
141 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
142 .atag_offset = 0x100,
143
144 .init_irq = s3c24xx_init_irq,
145 .map_io = smdk2443_map_io,
146 .init_machine = smdk2443_machine_init,
147 .timer = &s3c24xx_timer,
148 .restart = s3c2443_restart,
149MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
new file mode 100644
index 000000000000..b9deaeb0dfff
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -0,0 +1,114 @@
1/* linux/arch/arm/mach-s3c2443/s3c2443.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2443 Mobile CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/gpio.h>
20#include <linux/platform_device.h>
21#include <linux/serial_core.h>
22#include <linux/device.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <asm/irq.h>
32
33#include <mach/regs-s3c2443-clock.h>
34
35#include <plat/gpio-core.h>
36#include <plat/gpio-cfg.h>
37#include <plat/gpio-cfg-helpers.h>
38#include <plat/s3c2443.h>
39#include <plat/devs.h>
40#include <plat/cpu.h>
41#include <plat/fb-core.h>
42#include <plat/nand-core.h>
43#include <plat/adc-core.h>
44
45static struct map_desc s3c2443_iodesc[] __initdata = {
46 IODESC_ENT(WATCHDOG),
47 IODESC_ENT(CLKPWR),
48 IODESC_ENT(TIMER),
49};
50
51struct bus_type s3c2443_subsys = {
52 .name = "s3c2443-core",
53 .dev_name = "s3c2443-core",
54};
55
56static struct device s3c2443_dev = {
57 .bus = &s3c2443_subsys,
58};
59
60void s3c2443_restart(char mode, const char *cmd)
61{
62 if (mode == 's')
63 soft_restart(0);
64
65 __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
66}
67
68int __init s3c2443_init(void)
69{
70 printk("S3C2443: Initialising architecture\n");
71
72 s3c_nand_setname("s3c2412-nand");
73 s3c_fb_setname("s3c2443-fb");
74
75 s3c_adc_setname("s3c2443-adc");
76
77 /* change WDT IRQ number */
78 s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
79 s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
80
81 return device_register(&s3c2443_dev);
82}
83
84void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
85{
86 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
87}
88
89/* s3c2443_map_io
90 *
91 * register the standard cpu IO areas, and any passed in from the
92 * machine specific initialisation.
93 */
94
95void __init s3c2443_map_io(void)
96{
97 s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull;
98 s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull;
99
100 iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
101}
102
103/* need to register the subsystem before we actually register the device, and
104 * we also need to ensure that it has been initialised before any of the
105 * drivers even try to use it (even if not on an s3c2443 based system)
106 * as a driver which may support both 2443 and 2440 may try and use it.
107*/
108
109static int __init s3c2443_core_init(void)
110{
111 return subsys_system_register(&s3c2443_subsys, NULL);
112}
113
114core_initcall(s3c2443_core_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 06:41:18 -0500