aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s3c24xx
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-04 15:31:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-04 15:31:18 -0400
commit6fa52ed33bea997374a88dbacbba5bf8c7ac4fef (patch)
treea0904b78d66c9b99d6acf944cf58bcaa0cffc511 /arch/arm/mach-s3c24xx
parent1db772216f48978d5146b858586f6178433aad38 (diff)
parentbc8fd900c4d460b4e4bf785bb48bfced0ac9941b (diff)
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson: "This is a rather large set of patches for device drivers that for one reason or another the subsystem maintainer preferred to get merged through the arm-soc tree. There are both new drivers as well as existing drivers that are getting converted from platform-specific code into standalone drivers using the appropriate subsystem specific interfaces. In particular, we can now have pinctrl, clk, clksource and irqchip drivers in one file per driver, without the need to call into platform specific interface, or to get called from platform specific code, as long as all information about the hardware is provided through a device tree. Most of the drivers we touch this time are for clocksource. Since now most of them are part of drivers/clocksource, I expect that we won't have to touch these again from arm-soc and can let the clocksource maintainers take care of these in the future. Another larger part of this series is specific to the exynos platform, which is seeing some significant effort in upstreaming and modernization of its device drivers this time around, which unfortunately is also the cause for the churn and a lot of the merge conflicts. There is one new subsystem that gets merged as part of this series: the reset controller interface, which is a very simple interface for taking devices on the SoC out of reset or back into reset. Patches to use this interface on i.MX follow later in this merge window, and we are going to have other platforms (at least tegra and sirf) get converted in 3.11. This will let us get rid of platform specific callbacks in a number of platform independent device drivers." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits) irqchip: s3c24xx: add missing __init annotations ARM: dts: Disable the RTC by default on exynos5 clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3} ARM: exynos: restore mach/regs-clock.h for exynos5 clocksource: exynos_mct: fix build error on non-DT pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register() irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure reset: NULL deref on allocation failure reset: Add reset controller API dt: describe base reset signal binding ARM: EXYNOS: Add arm-pmu DT binding for exynos421x ARM: EXYNOS: Add arm-pmu DT binding for exynos5250 ARM: EXYNOS: Enable PMUs for exynos4 irqchip: exynos-combiner: Correct combined IRQs for exynos4 irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq ARM: EXYNOS: fix compilation error introduced due to common clock migration clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} clk: exynos4: export clocks required for fimc-is clk: samsung: Fix compilation error clk: tegra: fix enum tegra114_clk to match binding ...
Diffstat (limited to 'arch/arm/mach-s3c24xx')
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig7
-rw-r--r--arch/arm/mach-s3c24xx/Makefile8
-rw-r--r--arch/arm/mach-s3c24xx/common.h4
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/entry-macro.S70
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/irqs.h58
-rw-r--r--arch/arm/mach-s3c24xx/irq-s3c2412.c215
-rw-r--r--arch/arm/mach-s3c24xx/irq-s3c2440.c128
-rw-r--r--arch/arm/mach-s3c24xx/irq-s3c244x.c142
-rw-r--r--arch/arm/mach-s3c24xx/irq.c821
-rw-r--r--arch/arm/mach-s3c24xx/mach-amlm5900.c7
-rw-r--r--arch/arm/mach-s3c24xx/mach-anubis.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-at2440evb.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-bast.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-gta02.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-h1940.c12
-rw-r--r--arch/arm/mach-s3c24xx/mach-jive.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-mini2440.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-n30.c10
-rw-r--r--arch/arm/mach-s3c24xx/mach-nexcoder.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-osiris.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-otom.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-qt2410.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-rx1950.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-rx3715.c11
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2410.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2413.c14
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2416.c4
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2440.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2443.c4
-rw-r--r--arch/arm/mach-s3c24xx/mach-tct_hammer.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-vr1000.c6
-rw-r--r--arch/arm/mach-s3c24xx/mach-vstms.c6
-rw-r--r--arch/arm/mach-s3c24xx/pm-s3c2412.c8
33 files changed, 151 insertions, 1468 deletions
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 8d5fa6ece014..f2f7088bfd22 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -30,6 +30,7 @@ config CPU_S3C2410
30 select S3C2410_CLOCK 30 select S3C2410_CLOCK
31 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX 31 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
32 select S3C2410_PM if PM 32 select S3C2410_PM if PM
33 select SAMSUNG_HRT
33 help 34 help
34 Support for S3C2410 and S3C2410A family from the S3C24XX line 35 Support for S3C2410 and S3C2410A family from the S3C24XX line
35 of Samsung Mobile CPUs. 36 of Samsung Mobile CPUs.
@@ -40,6 +41,7 @@ config CPU_S3C2412
40 select CPU_LLSERIAL_S3C2440 41 select CPU_LLSERIAL_S3C2440
41 select S3C2412_DMA if S3C24XX_DMA 42 select S3C2412_DMA if S3C24XX_DMA
42 select S3C2412_PM if PM 43 select S3C2412_PM if PM
44 select SAMSUNG_HRT
43 help 45 help
44 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line 46 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
45 47
@@ -51,6 +53,7 @@ config CPU_S3C2416
51 select S3C2443_COMMON 53 select S3C2443_COMMON
52 select S3C2443_DMA if S3C24XX_DMA 54 select S3C2443_DMA if S3C24XX_DMA
53 select SAMSUNG_CLKSRC 55 select SAMSUNG_CLKSRC
56 select SAMSUNG_HRT
54 help 57 help
55 Support for the S3C2416 SoC from the S3C24XX line 58 Support for the S3C2416 SoC from the S3C24XX line
56 59
@@ -61,6 +64,7 @@ config CPU_S3C2440
61 select S3C2410_CLOCK 64 select S3C2410_CLOCK
62 select S3C2410_PM if PM 65 select S3C2410_PM if PM
63 select S3C2440_DMA if S3C24XX_DMA 66 select S3C2440_DMA if S3C24XX_DMA
67 select SAMSUNG_HRT
64 help 68 help
65 Support for S3C2440 Samsung Mobile CPU based systems. 69 Support for S3C2440 Samsung Mobile CPU based systems.
66 70
@@ -70,6 +74,7 @@ config CPU_S3C2442
70 select CPU_LLSERIAL_S3C2440 74 select CPU_LLSERIAL_S3C2440
71 select S3C2410_CLOCK 75 select S3C2410_CLOCK
72 select S3C2410_PM if PM 76 select S3C2410_PM if PM
77 select SAMSUNG_HRT
73 help 78 help
74 Support for S3C2442 Samsung Mobile CPU based systems. 79 Support for S3C2442 Samsung Mobile CPU based systems.
75 80
@@ -84,6 +89,7 @@ config CPU_S3C2443
84 select S3C2443_COMMON 89 select S3C2443_COMMON
85 select S3C2443_DMA if S3C24XX_DMA 90 select S3C2443_DMA if S3C24XX_DMA
86 select SAMSUNG_CLKSRC 91 select SAMSUNG_CLKSRC
92 select SAMSUNG_HRT
87 help 93 help
88 Support for the S3C2443 SoC from the S3C24XX line 94 Support for the S3C2443 SoC from the S3C24XX line
89 95
@@ -395,6 +401,7 @@ config S3C2412_DMA
395config S3C2412_PM 401config S3C2412_PM
396 bool 402 bool
397 select S3C2412_PM_SLEEP 403 select S3C2412_PM_SLEEP
404 select SAMSUNG_WAKEMASK
398 help 405 help
399 Internal config node to apply S3C2412 power management 406 Internal config node to apply S3C2412 power management
400 407
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index af53d27d5c36..6f46ecfc8396 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,7 +14,7 @@ obj- :=
14 14
15# core 15# core
16 16
17obj-y += common.o irq.o 17obj-y += common.o
18 18
19obj-$(CONFIG_CPU_S3C2410) += s3c2410.o 19obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
20obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o 20obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o
@@ -22,7 +22,7 @@ obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o
22obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o 22obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
23obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o 23obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o
24 24
25obj-$(CONFIG_CPU_S3C2412) += s3c2412.o irq-s3c2412.o clock-s3c2412.o 25obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o
26obj-$(CONFIG_S3C2412_CPUFREQ) += cpufreq-s3c2412.o 26obj-$(CONFIG_S3C2412_CPUFREQ) += cpufreq-s3c2412.o
27obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o 27obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
28obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o 28obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
@@ -31,9 +31,9 @@ obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
31obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock-s3c2416.o 31obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock-s3c2416.o
32obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o 32obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o
33 33
34obj-$(CONFIG_CPU_S3C2440) += s3c2440.o irq-s3c2440.o clock-s3c2440.o 34obj-$(CONFIG_CPU_S3C2440) += s3c2440.o clock-s3c2440.o
35obj-$(CONFIG_CPU_S3C2442) += s3c2442.o 35obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
36obj-$(CONFIG_CPU_S3C244X) += s3c244x.o irq-s3c244x.o clock-s3c244x.o 36obj-$(CONFIG_CPU_S3C244X) += s3c244x.o clock-s3c244x.o
37obj-$(CONFIG_S3C2440_CPUFREQ) += cpufreq-s3c2440.o 37obj-$(CONFIG_S3C2440_CPUFREQ) += cpufreq-s3c2440.o
38obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o 38obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o
39obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o 39obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 8a2b4137ddb6..307c3714be55 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -21,6 +21,7 @@ extern void s3c2410_map_io(void);
21extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); 21extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
22extern void s3c2410_init_clocks(int xtal); 22extern void s3c2410_init_clocks(int xtal);
23extern void s3c2410_restart(char mode, const char *cmd); 23extern void s3c2410_restart(char mode, const char *cmd);
24extern void s3c2410_init_irq(void);
24#else 25#else
25#define s3c2410_init_clocks NULL 26#define s3c2410_init_clocks NULL
26#define s3c2410_init_uarts NULL 27#define s3c2410_init_uarts NULL
@@ -36,6 +37,7 @@ extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
36extern void s3c2412_init_clocks(int xtal); 37extern void s3c2412_init_clocks(int xtal);
37extern int s3c2412_baseclk_add(void); 38extern int s3c2412_baseclk_add(void);
38extern void s3c2412_restart(char mode, const char *cmd); 39extern void s3c2412_restart(char mode, const char *cmd);
40extern void s3c2412_init_irq(void);
39#else 41#else
40#define s3c2412_init_clocks NULL 42#define s3c2412_init_clocks NULL
41#define s3c2412_init_uarts NULL 43#define s3c2412_init_uarts NULL
@@ -73,6 +75,7 @@ extern void s3c244x_restart(char mode, const char *cmd);
73#ifdef CONFIG_CPU_S3C2440 75#ifdef CONFIG_CPU_S3C2440
74extern int s3c2440_init(void); 76extern int s3c2440_init(void);
75extern void s3c2440_map_io(void); 77extern void s3c2440_map_io(void);
78extern void s3c2440_init_irq(void);
76#else 79#else
77#define s3c2440_init NULL 80#define s3c2440_init NULL
78#define s3c2440_map_io NULL 81#define s3c2440_map_io NULL
@@ -81,6 +84,7 @@ extern void s3c2440_map_io(void);
81#ifdef CONFIG_CPU_S3C2442 84#ifdef CONFIG_CPU_S3C2442
82extern int s3c2442_init(void); 85extern int s3c2442_init(void);
83extern void s3c2442_map_io(void); 86extern void s3c2442_map_io(void);
87extern void s3c2442_init_irq(void);
84#else 88#else
85#define s3c2442_init NULL 89#define s3c2442_init NULL
86#define s3c2442_map_io NULL 90#define s3c2442_map_io NULL
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
deleted file mode 100644
index 6a21beeba1da..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * arch/arm/mach-s3c2410/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for S3C2410-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9*/
10
11/* We have a problem that the INTOFFSET register does not always
12 * show one interrupt. Occasionally we get two interrupts through
13 * the prioritiser, and this causes the INTOFFSET register to show
14 * what looks like the logical-or of the two interrupt numbers.
15 *
16 * Thanks to Klaus, Shannon, et al for helping to debug this problem
17*/
18
19#define INTPND (0x10)
20#define INTOFFSET (0x14)
21
22#include <mach/hardware.h>
23#include <asm/irq.h>
24
25 .macro get_irqnr_preamble, base, tmp
26 .endm
27
28 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
29
30 mov \base, #S3C24XX_VA_IRQ
31
32 @@ try the interrupt offset register, since it is there
33
34 ldr \irqstat, [\base, #INTPND ]
35 teq \irqstat, #0
36 beq 1002f
37 ldr \irqnr, [\base, #INTOFFSET ]
38 mov \tmp, #1
39 tst \irqstat, \tmp, lsl \irqnr
40 bne 1001f
41
42 @@ the number specified is not a valid irq, so try
43 @@ and work it out for ourselves
44
45 mov \irqnr, #0 @@ start here
46
47 @@ work out which irq (if any) we got
48
49 movs \tmp, \irqstat, lsl#16
50 addeq \irqnr, \irqnr, #16
51 moveq \irqstat, \irqstat, lsr#16
52 tst \irqstat, #0xff
53 addeq \irqnr, \irqnr, #8
54 moveq \irqstat, \irqstat, lsr#8
55 tst \irqstat, #0xf
56 addeq \irqnr, \irqnr, #4
57 moveq \irqstat, \irqstat, lsr#4
58 tst \irqstat, #0x3
59 addeq \irqnr, \irqnr, #2
60 moveq \irqstat, \irqstat, lsr#2
61 tst \irqstat, #0x1
62 addeq \irqnr, \irqnr, #1
63
64 @@ we have the value
651001:
66 adds \irqnr, \irqnr, #IRQ_EINT0
671002:
68 @@ exit here, Z flag unset if IRQ
69
70 .endm
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index 1e73f5fa8659..b6dd4cb5a2ec 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -59,49 +59,53 @@
59#define IRQ_ADCPARENT S3C2410_IRQ(31) 59#define IRQ_ADCPARENT S3C2410_IRQ(31)
60 60
61/* interrupts generated from the external interrupts sources */ 61/* interrupts generated from the external interrupts sources */
62#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ 62#define IRQ_EINT0_2412 S3C2410_IRQ(32)
63#define IRQ_EINT5 S3C2410_IRQ(33) 63#define IRQ_EINT1_2412 S3C2410_IRQ(33)
64#define IRQ_EINT6 S3C2410_IRQ(34) 64#define IRQ_EINT2_2412 S3C2410_IRQ(34)
65#define IRQ_EINT7 S3C2410_IRQ(35) 65#define IRQ_EINT3_2412 S3C2410_IRQ(35)
66#define IRQ_EINT8 S3C2410_IRQ(36) 66#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */
67#define IRQ_EINT9 S3C2410_IRQ(37) 67#define IRQ_EINT5 S3C2410_IRQ(37)
68#define IRQ_EINT10 S3C2410_IRQ(38) 68#define IRQ_EINT6 S3C2410_IRQ(38)
69#define IRQ_EINT11 S3C2410_IRQ(39) 69#define IRQ_EINT7 S3C2410_IRQ(39)
70#define IRQ_EINT12 S3C2410_IRQ(40) 70#define IRQ_EINT8 S3C2410_IRQ(40)
71#define IRQ_EINT13 S3C2410_IRQ(41) 71#define IRQ_EINT9 S3C2410_IRQ(41)
72#define IRQ_EINT14 S3C2410_IRQ(42) 72#define IRQ_EINT10 S3C2410_IRQ(42)
73#define IRQ_EINT15 S3C2410_IRQ(43) 73#define IRQ_EINT11 S3C2410_IRQ(43)
74#define IRQ_EINT16 S3C2410_IRQ(44) 74#define IRQ_EINT12 S3C2410_IRQ(44)
75#define IRQ_EINT17 S3C2410_IRQ(45) 75#define IRQ_EINT13 S3C2410_IRQ(45)
76#define IRQ_EINT18 S3C2410_IRQ(46) 76#define IRQ_EINT14 S3C2410_IRQ(46)
77#define IRQ_EINT19 S3C2410_IRQ(47) 77#define IRQ_EINT15 S3C2410_IRQ(47)
78#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ 78#define IRQ_EINT16 S3C2410_IRQ(48)
79#define IRQ_EINT21 S3C2410_IRQ(49) 79#define IRQ_EINT17 S3C2410_IRQ(49)
80#define IRQ_EINT22 S3C2410_IRQ(50) 80#define IRQ_EINT18 S3C2410_IRQ(50)
81#define IRQ_EINT23 S3C2410_IRQ(51) 81#define IRQ_EINT19 S3C2410_IRQ(51)
82#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */
83#define IRQ_EINT21 S3C2410_IRQ(53)
84#define IRQ_EINT22 S3C2410_IRQ(54)
85#define IRQ_EINT23 S3C2410_IRQ(55)
82 86
83#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) 87#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
84#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) 88#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
85 89
86#define IRQ_LCD_FIFO S3C2410_IRQ(52) 90#define IRQ_LCD_FIFO S3C2410_IRQ(56)
87#define IRQ_LCD_FRAME S3C2410_IRQ(53) 91#define IRQ_LCD_FRAME S3C2410_IRQ(57)
88 92
89/* IRQs for the interal UARTs, and ADC 93/* IRQs for the interal UARTs, and ADC
90 * these need to be ordered in number of appearance in the 94 * these need to be ordered in number of appearance in the
91 * SUBSRC mask register 95 * SUBSRC mask register
92*/ 96*/
93 97
94#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) 98#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58)
95 99
96#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ 100#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */
97#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) 101#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
98#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) 102#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
99 103
100#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ 104#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */
101#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) 105#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
102#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) 106#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
103 107
104#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ 108#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */
105#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) 109#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
106#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) 110#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
107 111
@@ -136,7 +140,7 @@
136 140
137/* second interrupt-register of s3c2416/s3c2450 */ 141/* second interrupt-register of s3c2416/s3c2450 */
138 142
139#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 54 + 29) 143#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29)
140#define IRQ_S3C2416_2D S3C2416_IRQ(0) 144#define IRQ_S3C2416_2D S3C2416_IRQ(0)
141#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) 145#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
142#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) 146#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2412.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
deleted file mode 100644
index 67d763178d3f..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2412.c
+++ /dev/null
@@ -1,215 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/irq.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/device.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h>
36
37#include <plat/cpu.h>
38#include <plat/irq.h>
39#include <plat/pm.h>
40
41#include "s3c2412-power.h"
42
43#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
44#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
45
46/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
47 * having them turn up in both the INT* and the EINT* registers. Whilst
48 * both show the status, they both now need to be acked when the IRQs
49 * go off.
50*/
51
52static void
53s3c2412_irq_mask(struct irq_data *data)
54{
55 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
56 unsigned long mask;
57
58 mask = __raw_readl(S3C2410_INTMSK);
59 __raw_writel(mask | bitval, S3C2410_INTMSK);
60
61 mask = __raw_readl(S3C2412_EINTMASK);
62 __raw_writel(mask | bitval, S3C2412_EINTMASK);
63}
64
65static inline void
66s3c2412_irq_ack(struct irq_data *data)
67{
68 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
69
70 __raw_writel(bitval, S3C2412_EINTPEND);
71 __raw_writel(bitval, S3C2410_SRCPND);
72 __raw_writel(bitval, S3C2410_INTPND);
73}
74
75static inline void
76s3c2412_irq_maskack(struct irq_data *data)
77{
78 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
79 unsigned long mask;
80
81 mask = __raw_readl(S3C2410_INTMSK);
82 __raw_writel(mask|bitval, S3C2410_INTMSK);
83
84 mask = __raw_readl(S3C2412_EINTMASK);
85 __raw_writel(mask | bitval, S3C2412_EINTMASK);
86
87 __raw_writel(bitval, S3C2412_EINTPEND);
88 __raw_writel(bitval, S3C2410_SRCPND);
89 __raw_writel(bitval, S3C2410_INTPND);
90}
91
92static void
93s3c2412_irq_unmask(struct irq_data *data)
94{
95 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
96 unsigned long mask;
97
98 mask = __raw_readl(S3C2412_EINTMASK);
99 __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
100
101 mask = __raw_readl(S3C2410_INTMSK);
102 __raw_writel(mask & ~bitval, S3C2410_INTMSK);
103}
104
105static struct irq_chip s3c2412_irq_eint0t4 = {
106 .irq_ack = s3c2412_irq_ack,
107 .irq_mask = s3c2412_irq_mask,
108 .irq_unmask = s3c2412_irq_unmask,
109 .irq_set_wake = s3c_irq_wake,
110 .irq_set_type = s3c_irqext_type,
111};
112
113#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0)))
114
115/* CF and SDI sub interrupts */
116
117static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
118{
119 unsigned int subsrc, submsk;
120
121 subsrc = __raw_readl(S3C2410_SUBSRCPND);
122 submsk = __raw_readl(S3C2410_INTSUBMSK);
123
124 subsrc &= ~submsk;
125
126 if (subsrc & INTBIT(IRQ_S3C2412_SDI))
127 generic_handle_irq(IRQ_S3C2412_SDI);
128
129 if (subsrc & INTBIT(IRQ_S3C2412_CF))
130 generic_handle_irq(IRQ_S3C2412_CF);
131}
132
133#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
134#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
135
136static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
137{
138 s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
139}
140
141static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
142{
143 s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
144}
145
146static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
147{
148 s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
149}
150
151static struct irq_chip s3c2412_irq_cfsdi = {
152 .name = "s3c2412-cfsdi",
153 .irq_ack = s3c2412_irq_cfsdi_ack,
154 .irq_mask = s3c2412_irq_cfsdi_mask,
155 .irq_unmask = s3c2412_irq_cfsdi_unmask,
156};
157
158static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
159{
160 unsigned long pwrcfg;
161
162 pwrcfg = __raw_readl(S3C2412_PWRCFG);
163 if (state)
164 pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
165 else
166 pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
167 __raw_writel(pwrcfg, S3C2412_PWRCFG);
168
169 return s3c_irq_chip.irq_set_wake(data, state);
170}
171
172static struct irq_chip s3c2412_irq_rtc_chip;
173
174static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
175{
176 unsigned int irqno;
177
178 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
179 irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
180 handle_edge_irq);
181 set_irq_flags(irqno, IRQF_VALID);
182 }
183
184 /* add demux support for CF/SDI */
185
186 irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
187
188 for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
189 irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
190 handle_level_irq);
191 set_irq_flags(irqno, IRQF_VALID);
192 }
193
194 /* change RTC IRQ's set wake method */
195
196 s3c2412_irq_rtc_chip = s3c_irq_chip;
197 s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
198
199 irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
200
201 return 0;
202}
203
204static struct subsys_interface s3c2412_irq_interface = {
205 .name = "s3c2412_irq",
206 .subsys = &s3c2412_subsys,
207 .add_dev = s3c2412_irq_add,
208};
209
210static int s3c2412_irq_init(void)
211{
212 return subsys_interface_register(&s3c2412_irq_interface);
213}
214
215arch_initcall(s3c2412_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2440.c b/arch/arm/mach-s3c24xx/irq-s3c2440.c
deleted file mode 100644
index 4a18cde439cc..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2440.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/* linux/arch/arm/mach-s3c2440/irq.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/device.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h>
36
37#include <plat/cpu.h>
38#include <plat/pm.h>
39#include <plat/irq.h>
40
41/* WDT/AC97 */
42
43static void s3c_irq_demux_wdtac97(unsigned int irq,
44 struct irq_desc *desc)
45{
46 unsigned int subsrc, submsk;
47
48 /* read the current pending interrupts, and the mask
49 * for what it is available */
50
51 subsrc = __raw_readl(S3C2410_SUBSRCPND);
52 submsk = __raw_readl(S3C2410_INTSUBMSK);
53
54 subsrc &= ~submsk;
55 subsrc >>= 13;
56 subsrc &= 3;
57
58 if (subsrc != 0) {
59 if (subsrc & 1) {
60 generic_handle_irq(IRQ_S3C2440_WDT);
61 }
62 if (subsrc & 2) {
63 generic_handle_irq(IRQ_S3C2440_AC97);
64 }
65 }
66}
67
68
69#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
70
71static void
72s3c_irq_wdtac97_mask(struct irq_data *data)
73{
74 s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13);
75}
76
77static void
78s3c_irq_wdtac97_unmask(struct irq_data *data)
79{
80 s3c_irqsub_unmask(data->irq, INTMSK_WDT);
81}
82
83static void
84s3c_irq_wdtac97_ack(struct irq_data *data)
85{
86 s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13);
87}
88
89static struct irq_chip s3c_irq_wdtac97 = {
90 .irq_mask = s3c_irq_wdtac97_mask,
91 .irq_unmask = s3c_irq_wdtac97_unmask,
92 .irq_ack = s3c_irq_wdtac97_ack,
93};
94
95static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif)
96{
97 unsigned int irqno;
98
99 printk("S3C2440: IRQ Support\n");
100
101 /* add new chained handler for wdt, ac7 */
102
103 irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
104 handle_level_irq);
105 irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
106
107 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
108 irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
109 handle_level_irq);
110 set_irq_flags(irqno, IRQF_VALID);
111 }
112
113 return 0;
114}
115
116static struct subsys_interface s3c2440_irq_interface = {
117 .name = "s3c2440_irq",
118 .subsys = &s3c2440_subsys,
119 .add_dev = s3c2440_irq_add,
120};
121
122static int s3c2440_irq_init(void)
123{
124 return subsys_interface_register(&s3c2440_irq_interface);
125}
126
127arch_initcall(s3c2440_irq_init);
128
diff --git a/arch/arm/mach-s3c24xx/irq-s3c244x.c b/arch/arm/mach-s3c24xx/irq-s3c244x.c
deleted file mode 100644
index 5fe8e58d3afd..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c244x.c
+++ /dev/null
@@ -1,142 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/device.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h>
36
37#include <plat/cpu.h>
38#include <plat/pm.h>
39#include <plat/irq.h>
40
41/* camera irq */
42
43static void s3c_irq_demux_cam(unsigned int irq,
44 struct irq_desc *desc)
45{
46 unsigned int subsrc, submsk;
47
48 /* read the current pending interrupts, and the mask
49 * for what it is available */
50
51 subsrc = __raw_readl(S3C2410_SUBSRCPND);
52 submsk = __raw_readl(S3C2410_INTSUBMSK);
53
54 subsrc &= ~submsk;
55 subsrc >>= 11;
56 subsrc &= 3;
57
58 if (subsrc != 0) {
59 if (subsrc & 1) {
60 generic_handle_irq(IRQ_S3C2440_CAM_C);
61 }
62 if (subsrc & 2) {
63 generic_handle_irq(IRQ_S3C2440_CAM_P);
64 }
65 }
66}
67
68#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
69
70static void
71s3c_irq_cam_mask(struct irq_data *data)
72{
73 s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
74}
75
76static void
77s3c_irq_cam_unmask(struct irq_data *data)
78{
79 s3c_irqsub_unmask(data->irq, INTMSK_CAM);
80}
81
82static void
83s3c_irq_cam_ack(struct irq_data *data)
84{
85 s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
86}
87
88static struct irq_chip s3c_irq_cam = {
89 .irq_mask = s3c_irq_cam_mask,
90 .irq_unmask = s3c_irq_cam_unmask,
91 .irq_ack = s3c_irq_cam_ack,
92};
93
94static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
95{
96 unsigned int irqno;
97
98 irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
99 handle_level_irq);
100 set_irq_flags(IRQ_NFCON, IRQF_VALID);
101
102 /* add chained handler for camera */
103
104 irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
105 handle_level_irq);
106 irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
107
108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
109 irq_set_chip_and_handler(irqno, &s3c_irq_cam,
110 handle_level_irq);
111 set_irq_flags(irqno, IRQF_VALID);
112 }
113
114 return 0;
115}
116
117static struct subsys_interface s3c2440_irq_interface = {
118 .name = "s3c2440_irq",
119 .subsys = &s3c2440_subsys,
120 .add_dev = s3c244x_irq_add,
121};
122
123static int s3c2440_irq_init(void)
124{
125 return subsys_interface_register(&s3c2440_irq_interface);
126}
127
128arch_initcall(s3c2440_irq_init);
129
130static struct subsys_interface s3c2442_irq_interface = {
131 .name = "s3c2442_irq",
132 .subsys = &s3c2442_subsys,
133 .add_dev = s3c244x_irq_add,
134};
135
136
137static int s3c2442_irq_init(void)
138{
139 return subsys_interface_register(&s3c2442_irq_interface);
140}
141
142arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
deleted file mode 100644
index b41c2cb7af4a..000000000000
--- a/arch/arm/mach-s3c24xx/irq.c
+++ /dev/null
@@ -1,821 +0,0 @@
1/*
2 * S3C24XX IRQ handling
3 *
4 * Copyright (c) 2003-2004 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17*/
18
19#include <linux/init.h>
20#include <linux/slab.h>
21#include <linux/module.h>
22#include <linux/io.h>
23#include <linux/err.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/device.h>
27#include <linux/irqdomain.h>
28#include <linux/irqchip/chained_irq.h>
29
30#include <asm/mach/irq.h>
31
32#include <mach/regs-irq.h>
33#include <mach/regs-gpio.h>
34
35#include <plat/cpu.h>
36#include <plat/regs-irqtype.h>
37#include <plat/pm.h>
38
39#define S3C_IRQTYPE_NONE 0
40#define S3C_IRQTYPE_EINT 1
41#define S3C_IRQTYPE_EDGE 2
42#define S3C_IRQTYPE_LEVEL 3
43
44struct s3c_irq_data {
45 unsigned int type;
46 unsigned long parent_irq;
47
48 /* data gets filled during init */
49 struct s3c_irq_intc *intc;
50 unsigned long sub_bits;
51 struct s3c_irq_intc *sub_intc;
52};
53
54/*
55 * Sructure holding the controller data
56 * @reg_pending register holding pending irqs
57 * @reg_intpnd special register intpnd in main intc
58 * @reg_mask mask register
59 * @domain irq_domain of the controller
60 * @parent parent controller for ext and sub irqs
61 * @irqs irq-data, always s3c_irq_data[32]
62 */
63struct s3c_irq_intc {
64 void __iomem *reg_pending;
65 void __iomem *reg_intpnd;
66 void __iomem *reg_mask;
67 struct irq_domain *domain;
68 struct s3c_irq_intc *parent;
69 struct s3c_irq_data *irqs;
70};
71
72static void s3c_irq_mask(struct irq_data *data)
73{
74 struct s3c_irq_intc *intc = data->domain->host_data;
75 struct s3c_irq_intc *parent_intc = intc->parent;
76 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
77 struct s3c_irq_data *parent_data;
78 unsigned long mask;
79 unsigned int irqno;
80
81 mask = __raw_readl(intc->reg_mask);
82 mask |= (1UL << data->hwirq);
83 __raw_writel(mask, intc->reg_mask);
84
85 if (parent_intc && irq_data->parent_irq) {
86 parent_data = &parent_intc->irqs[irq_data->parent_irq];
87
88 /* check to see if we need to mask the parent IRQ */
89 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
90 irqno = irq_find_mapping(parent_intc->domain,
91 irq_data->parent_irq);
92 s3c_irq_mask(irq_get_irq_data(irqno));
93 }
94 }
95}
96
97static void s3c_irq_unmask(struct irq_data *data)
98{
99 struct s3c_irq_intc *intc = data->domain->host_data;
100 struct s3c_irq_intc *parent_intc = intc->parent;
101 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
102 unsigned long mask;
103 unsigned int irqno;
104
105 mask = __raw_readl(intc->reg_mask);
106 mask &= ~(1UL << data->hwirq);
107 __raw_writel(mask, intc->reg_mask);
108
109 if (parent_intc && irq_data->parent_irq) {
110 irqno = irq_find_mapping(parent_intc->domain,
111 irq_data->parent_irq);
112 s3c_irq_unmask(irq_get_irq_data(irqno));
113 }
114}
115
116static inline void s3c_irq_ack(struct irq_data *data)
117{
118 struct s3c_irq_intc *intc = data->domain->host_data;
119 unsigned long bitval = 1UL << data->hwirq;
120
121 __raw_writel(bitval, intc->reg_pending);
122 if (intc->reg_intpnd)
123 __raw_writel(bitval, intc->reg_intpnd);
124}
125
126static int s3c_irqext_type_set(void __iomem *gpcon_reg,
127 void __iomem *extint_reg,
128 unsigned long gpcon_offset,
129 unsigned long extint_offset,
130 unsigned int type)
131{
132 unsigned long newvalue = 0, value;
133
134 /* Set the GPIO to external interrupt mode */
135 value = __raw_readl(gpcon_reg);
136 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
137 __raw_writel(value, gpcon_reg);
138
139 /* Set the external interrupt to pointed trigger type */
140 switch (type)
141 {
142 case IRQ_TYPE_NONE:
143 pr_warn("No edge setting!\n");
144 break;
145
146 case IRQ_TYPE_EDGE_RISING:
147 newvalue = S3C2410_EXTINT_RISEEDGE;
148 break;
149
150 case IRQ_TYPE_EDGE_FALLING:
151 newvalue = S3C2410_EXTINT_FALLEDGE;
152 break;
153
154 case IRQ_TYPE_EDGE_BOTH:
155 newvalue = S3C2410_EXTINT_BOTHEDGE;
156 break;
157
158 case IRQ_TYPE_LEVEL_LOW:
159 newvalue = S3C2410_EXTINT_LOWLEV;
160 break;
161
162 case IRQ_TYPE_LEVEL_HIGH:
163 newvalue = S3C2410_EXTINT_HILEV;
164 break;
165
166 default:
167 pr_err("No such irq type %d", type);
168 return -EINVAL;
169 }
170
171 value = __raw_readl(extint_reg);
172 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
173 __raw_writel(value, extint_reg);
174
175 return 0;
176}
177
178static int s3c_irqext_type(struct irq_data *data, unsigned int type)
179{
180 void __iomem *extint_reg;
181 void __iomem *gpcon_reg;
182 unsigned long gpcon_offset, extint_offset;
183
184 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
185 gpcon_reg = S3C2410_GPFCON;
186 extint_reg = S3C24XX_EXTINT0;
187 gpcon_offset = (data->hwirq) * 2;
188 extint_offset = (data->hwirq) * 4;
189 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
190 gpcon_reg = S3C2410_GPGCON;
191 extint_reg = S3C24XX_EXTINT1;
192 gpcon_offset = (data->hwirq - 8) * 2;
193 extint_offset = (data->hwirq - 8) * 4;
194 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
195 gpcon_reg = S3C2410_GPGCON;
196 extint_reg = S3C24XX_EXTINT2;
197 gpcon_offset = (data->hwirq - 8) * 2;
198 extint_offset = (data->hwirq - 16) * 4;
199 } else {
200 return -EINVAL;
201 }
202
203 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
204 extint_offset, type);
205}
206
207static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
208{
209 void __iomem *extint_reg;
210 void __iomem *gpcon_reg;
211 unsigned long gpcon_offset, extint_offset;
212
213 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
214 gpcon_reg = S3C2410_GPFCON;
215 extint_reg = S3C24XX_EXTINT0;
216 gpcon_offset = (data->hwirq) * 2;
217 extint_offset = (data->hwirq) * 4;
218 } else {
219 return -EINVAL;
220 }
221
222 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
223 extint_offset, type);
224}
225
226static struct irq_chip s3c_irq_chip = {
227 .name = "s3c",
228 .irq_ack = s3c_irq_ack,
229 .irq_mask = s3c_irq_mask,
230 .irq_unmask = s3c_irq_unmask,
231 .irq_set_wake = s3c_irq_wake
232};
233
234static struct irq_chip s3c_irq_level_chip = {
235 .name = "s3c-level",
236 .irq_mask = s3c_irq_mask,
237 .irq_unmask = s3c_irq_unmask,
238 .irq_ack = s3c_irq_ack,
239};
240
241static struct irq_chip s3c_irqext_chip = {
242 .name = "s3c-ext",
243 .irq_mask = s3c_irq_mask,
244 .irq_unmask = s3c_irq_unmask,
245 .irq_ack = s3c_irq_ack,
246 .irq_set_type = s3c_irqext_type,
247 .irq_set_wake = s3c_irqext_wake
248};
249
250static struct irq_chip s3c_irq_eint0t4 = {
251 .name = "s3c-ext0",
252 .irq_ack = s3c_irq_ack,
253 .irq_mask = s3c_irq_mask,
254 .irq_unmask = s3c_irq_unmask,
255 .irq_set_wake = s3c_irq_wake,
256 .irq_set_type = s3c_irqext0_type,
257};
258
259static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
260{
261 struct irq_chip *chip = irq_desc_get_chip(desc);
262 struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
263 struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
264 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
265 unsigned long src;
266 unsigned long msk;
267 unsigned int n;
268
269 chained_irq_enter(chip, desc);
270
271 src = __raw_readl(sub_intc->reg_pending);
272 msk = __raw_readl(sub_intc->reg_mask);
273
274 src &= ~msk;
275 src &= irq_data->sub_bits;
276
277 while (src) {
278 n = __ffs(src);
279 src &= ~(1 << n);
280 generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
281 }
282
283 chained_irq_exit(chip, desc);
284}
285
286#ifdef CONFIG_FIQ
287/**
288 * s3c24xx_set_fiq - set the FIQ routing
289 * @irq: IRQ number to route to FIQ on processor.
290 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
291 *
292 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
293 * @on is true, the @irq is checked to see if it can be routed and the
294 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
295 * routing is cleared, regardless of which @irq is specified.
296 */
297int s3c24xx_set_fiq(unsigned int irq, bool on)
298{
299 u32 intmod;
300 unsigned offs;
301
302 if (on) {
303 offs = irq - FIQ_START;
304 if (offs > 31)
305 return -EINVAL;
306
307 intmod = 1 << offs;
308 } else {
309 intmod = 0;
310 }
311
312 __raw_writel(intmod, S3C2410_INTMOD);
313 return 0;
314}
315
316EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
317#endif
318
319static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
320 irq_hw_number_t hw)
321{
322 struct s3c_irq_intc *intc = h->host_data;
323 struct s3c_irq_data *irq_data = &intc->irqs[hw];
324 struct s3c_irq_intc *parent_intc;
325 struct s3c_irq_data *parent_irq_data;
326 unsigned int irqno;
327
328 if (!intc) {
329 pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
330 return -EINVAL;
331 }
332
333 if (!irq_data) {
334 pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
335 return -EINVAL;
336 }
337
338 /* attach controller pointer to irq_data */
339 irq_data->intc = intc;
340
341 /* set handler and flags */
342 switch (irq_data->type) {
343 case S3C_IRQTYPE_NONE:
344 return 0;
345 case S3C_IRQTYPE_EINT:
346 if (irq_data->parent_irq)
347 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
348 handle_edge_irq);
349 else
350 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
351 handle_edge_irq);
352 break;
353 case S3C_IRQTYPE_EDGE:
354 if (irq_data->parent_irq ||
355 intc->reg_pending == S3C2416_SRCPND2)
356 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
357 handle_edge_irq);
358 else
359 irq_set_chip_and_handler(virq, &s3c_irq_chip,
360 handle_edge_irq);
361 break;
362 case S3C_IRQTYPE_LEVEL:
363 if (irq_data->parent_irq)
364 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
365 handle_level_irq);
366 else
367 irq_set_chip_and_handler(virq, &s3c_irq_chip,
368 handle_level_irq);
369 break;
370 default:
371 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
372 return -EINVAL;
373 }
374 set_irq_flags(virq, IRQF_VALID);
375
376 if (irq_data->parent_irq) {
377 parent_intc = intc->parent;
378 if (!parent_intc) {
379 pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
380 hw);
381 goto err;
382 }
383
384 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
385 if (!irq_data) {
386 pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
387 hw);
388 goto err;
389 }
390
391 parent_irq_data->sub_intc = intc;
392 parent_irq_data->sub_bits |= (1UL << hw);
393
394 /* attach the demuxer to the parent irq */
395 irqno = irq_find_mapping(parent_intc->domain,
396 irq_data->parent_irq);
397 if (!irqno) {
398 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
399 irq_data->parent_irq);
400 goto err;
401 }
402 irq_set_chained_handler(irqno, s3c_irq_demux);
403 }
404
405 return 0;
406
407err:
408 set_irq_flags(virq, 0);
409
410 /* the only error can result from bad mapping data*/
411 return -EINVAL;
412}
413
414static struct irq_domain_ops s3c24xx_irq_ops = {
415 .map = s3c24xx_irq_map,
416 .xlate = irq_domain_xlate_twocell,
417};
418
419static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
420{
421 void __iomem *reg_source;
422 unsigned long pend;
423 unsigned long last;
424 int i;
425
426 /* if intpnd is set, read the next pending irq from there */
427 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
428
429 last = 0;
430 for (i = 0; i < 4; i++) {
431 pend = __raw_readl(reg_source);
432
433 if (pend == 0 || pend == last)
434 break;
435
436 __raw_writel(pend, intc->reg_pending);
437 if (intc->reg_intpnd)
438 __raw_writel(pend, intc->reg_intpnd);
439
440 pr_info("irq: clearing pending status %08x\n", (int)pend);
441 last = pend;
442 }
443}
444
445struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
446 struct s3c_irq_data *irq_data,
447 struct s3c_irq_intc *parent,
448 unsigned long address)
449{
450 struct s3c_irq_intc *intc;
451 void __iomem *base = (void *)0xf6000000; /* static mapping */
452 int irq_num;
453 int irq_start;
454 int irq_offset;
455 int ret;
456
457 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
458 if (!intc)
459 return ERR_PTR(-ENOMEM);
460
461 intc->irqs = irq_data;
462
463 if (parent)
464 intc->parent = parent;
465
466 /* select the correct data for the controller.
467 * Need to hard code the irq num start and offset
468 * to preserve the static mapping for now
469 */
470 switch (address) {
471 case 0x4a000000:
472 pr_debug("irq: found main intc\n");
473 intc->reg_pending = base;
474 intc->reg_mask = base + 0x08;
475 intc->reg_intpnd = base + 0x10;
476 irq_num = 32;
477 irq_start = S3C2410_IRQ(0);
478 irq_offset = 0;
479 break;
480 case 0x4a000018:
481 pr_debug("irq: found subintc\n");
482 intc->reg_pending = base + 0x18;
483 intc->reg_mask = base + 0x1c;
484 irq_num = 29;
485 irq_start = S3C2410_IRQSUB(0);
486 irq_offset = 0;
487 break;
488 case 0x4a000040:
489 pr_debug("irq: found intc2\n");
490 intc->reg_pending = base + 0x40;
491 intc->reg_mask = base + 0x48;
492 intc->reg_intpnd = base + 0x50;
493 irq_num = 8;
494 irq_start = S3C2416_IRQ(0);
495 irq_offset = 0;
496 break;
497 case 0x560000a4:
498 pr_debug("irq: found eintc\n");
499 base = (void *)0xfd000000;
500
501 intc->reg_mask = base + 0xa4;
502 intc->reg_pending = base + 0xa8;
503 irq_num = 20;
504 irq_start = S3C2410_IRQ(32);
505 irq_offset = 4;
506 break;
507 default:
508 pr_err("irq: unsupported controller address\n");
509 ret = -EINVAL;
510 goto err;
511 }
512
513 /* now that all the data is complete, init the irq-domain */
514 s3c24xx_clear_intc(intc);
515 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
516 irq_offset, &s3c24xx_irq_ops,
517 intc);
518 if (!intc->domain) {
519 pr_err("irq: could not create irq-domain\n");
520 ret = -EINVAL;
521 goto err;
522 }
523
524 return intc;
525
526err:
527 kfree(intc);
528 return ERR_PTR(ret);
529}
530
531/* s3c24xx_init_irq
532 *
533 * Initialise S3C2410 IRQ system
534*/
535
536static struct s3c_irq_data init_base[32] = {
537 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
538 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
539 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
540 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
541 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
542 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
543 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
544 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
545 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
546 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
547 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
548 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
549 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
550 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
551 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
552 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
553 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
554 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
555 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
556 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
557 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
558 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
559 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
560 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
561 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
562 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
563 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
564 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
565 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
566 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
567 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
568 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
569};
570
571static struct s3c_irq_data init_eint[32] = {
572 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
573 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
574 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
575 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
576 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
577 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
578 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
579 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
580 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
581 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
582 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
583 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
584 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
585 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
586 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
587 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
588 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
589 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
590 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
591 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
592 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
593 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
594 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
595 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
596};
597
598static struct s3c_irq_data init_subint[32] = {
599 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
600 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
601 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
602 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
603 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
604 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
605 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
606 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
607 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
608 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
609 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
610};
611
612void __init s3c24xx_init_irq(void)
613{
614 struct s3c_irq_intc *main_intc;
615
616#ifdef CONFIG_FIQ
617 init_FIQ(FIQ_START);
618#endif
619
620 main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
621 if (IS_ERR(main_intc)) {
622 pr_err("irq: could not create main interrupt controller\n");
623 return;
624 }
625
626 s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
627 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
628}
629
630#ifdef CONFIG_CPU_S3C2416
631static struct s3c_irq_data init_s3c2416base[32] = {
632 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
633 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
634 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
635 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
636 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
637 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
638 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
639 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
640 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
641 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
642 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
643 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
644 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
645 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
646 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
647 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
648 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
649 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
650 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
651 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
652 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
653 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
654 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
655 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
656 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
657 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
658 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
659 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
660 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
661 { .type = S3C_IRQTYPE_NONE, },
662 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
663 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
664};
665
666static struct s3c_irq_data init_s3c2416subint[32] = {
667 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
668 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
669 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
670 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
671 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
676 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
677 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
678 { .type = S3C_IRQTYPE_NONE }, /* reserved */
679 { .type = S3C_IRQTYPE_NONE }, /* reserved */
680 { .type = S3C_IRQTYPE_NONE }, /* reserved */
681 { .type = S3C_IRQTYPE_NONE }, /* reserved */
682 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
683 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
684 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
685 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
686 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
687 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
688 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
689 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
690 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
691 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
692 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
693 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
694 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
695 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
696};
697
698static struct s3c_irq_data init_s3c2416_second[32] = {
699 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
700 { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
701 { .type = S3C_IRQTYPE_NONE }, /* reserved */
702 { .type = S3C_IRQTYPE_NONE }, /* reserved */
703 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
704 { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
705 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
706 { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
707};
708
709void __init s3c2416_init_irq(void)
710{
711 struct s3c_irq_intc *main_intc;
712
713 pr_info("S3C2416: IRQ Support\n");
714
715#ifdef CONFIG_FIQ
716 init_FIQ(FIQ_START);
717#endif
718
719 main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
720 if (IS_ERR(main_intc)) {
721 pr_err("irq: could not create main interrupt controller\n");
722 return;
723 }
724
725 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
726 s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
727
728 s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
729}
730
731#endif
732
733#ifdef CONFIG_CPU_S3C2443
734static struct s3c_irq_data init_s3c2443base[32] = {
735 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
736 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
737 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
738 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
739 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
740 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
741 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
742 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
743 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
744 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
745 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
746 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
747 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
748 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
749 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
750 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
751 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
752 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
753 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
754 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
755 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
756 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
757 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
758 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
759 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
760 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
761 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
762 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
763 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
764 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
765 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
766 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
767};
768
769
770static struct s3c_irq_data init_s3c2443subint[32] = {
771 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
776 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
777 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
778 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
779 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
780 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
781 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
782 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
783 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
784 { .type = S3C_IRQTYPE_NONE }, /* reserved */
785 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
786 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
787 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
788 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
789 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
790 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
791 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
792 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
793 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
794 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
795 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
796 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
797 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
798 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
799 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
800};
801
802void __init s3c2443_init_irq(void)
803{
804 struct s3c_irq_intc *main_intc;
805
806 pr_info("S3C2443: IRQ Support\n");
807
808#ifdef CONFIG_FIQ
809 init_FIQ(FIQ_START);
810#endif
811
812 main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
813 if (IS_ERR(main_intc)) {
814 pr_err("irq: could not create main interrupt controller\n");
815 return;
816 }
817
818 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
819 s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
820}
821#endif
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 0e0279e79150..e27b5c91b3db 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -63,6 +63,8 @@
63#include <linux/mtd/map.h> 63#include <linux/mtd/map.h>
64#include <linux/mtd/physmap.h> 64#include <linux/mtd/physmap.h>
65 65
66#include <plat/samsung-time.h>
67
66#include "common.h" 68#include "common.h"
67 69
68static struct resource amlm5900_nor_resource = 70static struct resource amlm5900_nor_resource =
@@ -160,6 +162,7 @@ static void __init amlm5900_map_io(void)
160 s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc)); 162 s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
161 s3c24xx_init_clocks(0); 163 s3c24xx_init_clocks(0);
162 s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs)); 164 s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
165 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
163} 166}
164 167
165#ifdef CONFIG_FB_S3C2410 168#ifdef CONFIG_FB_S3C2410
@@ -235,8 +238,8 @@ static void __init amlm5900_init(void)
235MACHINE_START(AML_M5900, "AML_M5900") 238MACHINE_START(AML_M5900, "AML_M5900")
236 .atag_offset = 0x100, 239 .atag_offset = 0x100,
237 .map_io = amlm5900_map_io, 240 .map_io = amlm5900_map_io,
238 .init_irq = s3c24xx_init_irq, 241 .init_irq = s3c2410_init_irq,
239 .init_machine = amlm5900_init, 242 .init_machine = amlm5900_init,
240 .init_time = s3c24xx_timer_init, 243 .init_time = samsung_timer_init,
241 .restart = s3c2410_restart, 244 .restart = s3c2410_restart,
242MACHINE_END 245MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index bb595f15ce36..c1fb6c37867f 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -49,6 +49,7 @@
49#include <plat/devs.h> 49#include <plat/devs.h>
50#include <plat/cpu.h> 50#include <plat/cpu.h>
51#include <linux/platform_data/asoc-s3c24xx_simtec.h> 51#include <linux/platform_data/asoc-s3c24xx_simtec.h>
52#include <plat/samsung-time.h>
52 53
53#include "anubis.h" 54#include "anubis.h"
54#include "common.h" 55#include "common.h"
@@ -410,6 +411,7 @@ static void __init anubis_map_io(void)
410 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); 411 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
411 s3c24xx_init_clocks(0); 412 s3c24xx_init_clocks(0);
412 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); 413 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
414 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
413 415
414 /* check for the newer revision boards with large page nand */ 416 /* check for the newer revision boards with large page nand */
415 417
@@ -443,7 +445,7 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
443 .atag_offset = 0x100, 445 .atag_offset = 0x100,
444 .map_io = anubis_map_io, 446 .map_io = anubis_map_io,
445 .init_machine = anubis_init, 447 .init_machine = anubis_init,
446 .init_irq = s3c24xx_init_irq, 448 .init_irq = s3c2440_init_irq,
447 .init_time = s3c24xx_timer_init, 449 .init_time = samsung_timer_init,
448 .restart = s3c244x_restart, 450 .restart = s3c244x_restart,
449MACHINE_END 451MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index b4bc60c78ebb..6dfeeb7ef469 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -48,6 +48,7 @@
48#include <plat/devs.h> 48#include <plat/devs.h>
49#include <plat/cpu.h> 49#include <plat/cpu.h>
50#include <linux/platform_data/mmc-s3cmci.h> 50#include <linux/platform_data/mmc-s3cmci.h>
51#include <plat/samsung-time.h>
51 52
52#include "common.h" 53#include "common.h"
53 54
@@ -192,6 +193,7 @@ static void __init at2440evb_map_io(void)
192 s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); 193 s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
193 s3c24xx_init_clocks(16934400); 194 s3c24xx_init_clocks(16934400);
194 s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); 195 s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
196 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
195} 197}
196 198
197static void __init at2440evb_init(void) 199static void __init at2440evb_init(void)
@@ -209,7 +211,7 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
209 .atag_offset = 0x100, 211 .atag_offset = 0x100,
210 .map_io = at2440evb_map_io, 212 .map_io = at2440evb_map_io,
211 .init_machine = at2440evb_init, 213 .init_machine = at2440evb_init,
212 .init_irq = s3c24xx_init_irq, 214 .init_irq = s3c2440_init_irq,
213 .init_time = s3c24xx_timer_init, 215 .init_time = samsung_timer_init,
214 .restart = s3c244x_restart, 216 .restart = s3c244x_restart,
215MACHINE_END 217MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index ca6618081041..22d6ae926d91 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -55,6 +55,7 @@
55#include <plat/devs.h> 55#include <plat/devs.h>
56#include <plat/gpio-cfg.h> 56#include <plat/gpio-cfg.h>
57#include <plat/regs-serial.h> 57#include <plat/regs-serial.h>
58#include <plat/samsung-time.h>
58 59
59#include "bast.h" 60#include "bast.h"
60#include "common.h" 61#include "common.h"
@@ -576,6 +577,7 @@ static void __init bast_map_io(void)
576 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); 577 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
577 s3c24xx_init_clocks(0); 578 s3c24xx_init_clocks(0);
578 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); 579 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
580 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
579} 581}
580 582
581static void __init bast_init(void) 583static void __init bast_init(void)
@@ -603,8 +605,8 @@ MACHINE_START(BAST, "Simtec-BAST")
603 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 605 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
604 .atag_offset = 0x100, 606 .atag_offset = 0x100,
605 .map_io = bast_map_io, 607 .map_io = bast_map_io,
606 .init_irq = s3c24xx_init_irq, 608 .init_irq = s3c2410_init_irq,
607 .init_machine = bast_init, 609 .init_machine = bast_init,
608 .init_time = s3c24xx_timer_init, 610 .init_time = samsung_timer_init,
609 .restart = s3c2410_restart, 611 .restart = s3c2410_restart,
610MACHINE_END 612MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index a25e8c5a7b4c..13d8d073675a 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -81,6 +81,7 @@
81#include <plat/gpio-cfg.h> 81#include <plat/gpio-cfg.h>
82#include <plat/pm.h> 82#include <plat/pm.h>
83#include <plat/regs-serial.h> 83#include <plat/regs-serial.h>
84#include <plat/samsung-time.h>
84 85
85#include "common.h" 86#include "common.h"
86#include "gta02.h" 87#include "gta02.h"
@@ -501,6 +502,7 @@ static void __init gta02_map_io(void)
501 s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); 502 s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
502 s3c24xx_init_clocks(12000000); 503 s3c24xx_init_clocks(12000000);
503 s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs)); 504 s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
505 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
504} 506}
505 507
506 508
@@ -587,8 +589,8 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
587 /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */ 589 /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
588 .atag_offset = 0x100, 590 .atag_offset = 0x100,
589 .map_io = gta02_map_io, 591 .map_io = gta02_map_io,
590 .init_irq = s3c24xx_init_irq, 592 .init_irq = s3c2442_init_irq,
591 .init_machine = gta02_machine_init, 593 .init_machine = gta02_machine_init,
592 .init_time = s3c24xx_timer_init, 594 .init_time = samsung_timer_init,
593 .restart = s3c244x_restart, 595 .restart = s3c244x_restart,
594MACHINE_END 596MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 79bc0830d740..af4334d6b4d5 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -62,7 +62,7 @@
62#include <plat/pll.h> 62#include <plat/pll.h>
63#include <plat/pm.h> 63#include <plat/pm.h>
64#include <plat/regs-serial.h> 64#include <plat/regs-serial.h>
65 65#include <plat/samsung-time.h>
66 66
67#include "common.h" 67#include "common.h"
68#include "h1940.h" 68#include "h1940.h"
@@ -646,6 +646,7 @@ static void __init h1940_map_io(void)
646 s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc)); 646 s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
647 s3c24xx_init_clocks(0); 647 s3c24xx_init_clocks(0);
648 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); 648 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
649 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
649 650
650 /* setup PM */ 651 /* setup PM */
651 652
@@ -666,11 +667,6 @@ static void __init h1940_reserve(void)
666 memblock_reserve(0x30081000, 0x1000); 667 memblock_reserve(0x30081000, 0x1000);
667} 668}
668 669
669static void __init h1940_init_irq(void)
670{
671 s3c24xx_init_irq();
672}
673
674static void __init h1940_init(void) 670static void __init h1940_init(void)
675{ 671{
676 u32 tmp; 672 u32 tmp;
@@ -739,8 +735,8 @@ MACHINE_START(H1940, "IPAQ-H1940")
739 .atag_offset = 0x100, 735 .atag_offset = 0x100,
740 .map_io = h1940_map_io, 736 .map_io = h1940_map_io,
741 .reserve = h1940_reserve, 737 .reserve = h1940_reserve,
742 .init_irq = h1940_init_irq, 738 .init_irq = s3c2410_init_irq,
743 .init_machine = h1940_init, 739 .init_machine = h1940_init,
744 .init_time = s3c24xx_timer_init, 740 .init_time = samsung_timer_init,
745 .restart = s3c2410_restart, 741 .restart = s3c2410_restart,
746MACHINE_END 742MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index ca08d7df07f7..a45fcd8ccf79 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -52,6 +52,7 @@
52#include <plat/cpu.h> 52#include <plat/cpu.h>
53#include <plat/pm.h> 53#include <plat/pm.h>
54#include <linux/platform_data/usb-s3c2410_udc.h> 54#include <linux/platform_data/usb-s3c2410_udc.h>
55#include <plat/samsung-time.h>
55 56
56#include "common.h" 57#include "common.h"
57#include "s3c2412-power.h" 58#include "s3c2412-power.h"
@@ -506,6 +507,7 @@ static void __init jive_map_io(void)
506 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); 507 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
507 s3c24xx_init_clocks(12000000); 508 s3c24xx_init_clocks(12000000);
508 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs)); 509 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
510 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
509} 511}
510 512
511static void jive_power_off(void) 513static void jive_power_off(void)
@@ -658,9 +660,9 @@ MACHINE_START(JIVE, "JIVE")
658 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 660 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
659 .atag_offset = 0x100, 661 .atag_offset = 0x100,
660 662
661 .init_irq = s3c24xx_init_irq, 663 .init_irq = s3c2412_init_irq,
662 .map_io = jive_map_io, 664 .map_io = jive_map_io,
663 .init_machine = jive_machine_init, 665 .init_machine = jive_machine_init,
664 .init_time = s3c24xx_timer_init, 666 .init_time = samsung_timer_init,
665 .restart = s3c2412_restart, 667 .restart = s3c2412_restart,
666MACHINE_END 668MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 2865e5919f2c..a83db46320bc 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -56,6 +56,7 @@
56#include <plat/clock.h> 56#include <plat/clock.h>
57#include <plat/devs.h> 57#include <plat/devs.h>
58#include <plat/cpu.h> 58#include <plat/cpu.h>
59#include <plat/samsung-time.h>
59 60
60#include <sound/s3c24xx_uda134x.h> 61#include <sound/s3c24xx_uda134x.h>
61 62
@@ -525,6 +526,7 @@ static void __init mini2440_map_io(void)
525 s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); 526 s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
526 s3c24xx_init_clocks(12000000); 527 s3c24xx_init_clocks(12000000);
527 s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); 528 s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
529 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
528} 530}
529 531
530/* 532/*
@@ -686,7 +688,7 @@ MACHINE_START(MINI2440, "MINI2440")
686 .atag_offset = 0x100, 688 .atag_offset = 0x100,
687 .map_io = mini2440_map_io, 689 .map_io = mini2440_map_io,
688 .init_machine = mini2440_init, 690 .init_machine = mini2440_init,
689 .init_irq = s3c24xx_init_irq, 691 .init_irq = s3c2440_init_irq,
690 .init_time = s3c24xx_timer_init, 692 .init_time = samsung_timer_init,
691 .restart = s3c244x_restart, 693 .restart = s3c244x_restart,
692MACHINE_END 694MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 8017c0fc1729..2cb46c37c920 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -49,6 +49,7 @@
49#include <plat/devs.h> 49#include <plat/devs.h>
50#include <linux/platform_data/mmc-s3cmci.h> 50#include <linux/platform_data/mmc-s3cmci.h>
51#include <linux/platform_data/usb-s3c2410_udc.h> 51#include <linux/platform_data/usb-s3c2410_udc.h>
52#include <plat/samsung-time.h>
52 53
53#include "common.h" 54#include "common.h"
54 55
@@ -535,6 +536,7 @@ static void __init n30_map_io(void)
535 n30_hwinit(); 536 n30_hwinit();
536 s3c24xx_init_clocks(0); 537 s3c24xx_init_clocks(0);
537 s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); 538 s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
539 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
538} 540}
539 541
540/* GPB3 is the line that controls the pull-up for the USB D+ line */ 542/* GPB3 is the line that controls the pull-up for the USB D+ line */
@@ -588,9 +590,9 @@ MACHINE_START(N30, "Acer-N30")
588 Ben Dooks <ben-linux@fluff.org> 590 Ben Dooks <ben-linux@fluff.org>
589 */ 591 */
590 .atag_offset = 0x100, 592 .atag_offset = 0x100,
591 .init_time = s3c24xx_timer_init, 593 .init_time = samsung_timer_init,
592 .init_machine = n30_init, 594 .init_machine = n30_init,
593 .init_irq = s3c24xx_init_irq, 595 .init_irq = s3c2410_init_irq,
594 .map_io = n30_map_io, 596 .map_io = n30_map_io,
595 .restart = s3c2410_restart, 597 .restart = s3c2410_restart,
596MACHINE_END 598MACHINE_END
@@ -599,9 +601,9 @@ MACHINE_START(N35, "Acer-N35")
599 /* Maintainer: Christer Weinigel <christer@weinigel.se> 601 /* Maintainer: Christer Weinigel <christer@weinigel.se>
600 */ 602 */
601 .atag_offset = 0x100, 603 .atag_offset = 0x100,
602 .init_time = s3c24xx_timer_init, 604 .init_time = samsung_timer_init,
603 .init_machine = n30_init, 605 .init_machine = n30_init,
604 .init_irq = s3c24xx_init_irq, 606 .init_irq = s3c2410_init_irq,
605 .map_io = n30_map_io, 607 .map_io = n30_map_io,
606 .restart = s3c2410_restart, 608 .restart = s3c2410_restart,
607MACHINE_END 609MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 144b9f80c4a5..01f4354206f9 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -44,6 +44,7 @@
44#include <plat/clock.h> 44#include <plat/clock.h>
45#include <plat/devs.h> 45#include <plat/devs.h>
46#include <plat/cpu.h> 46#include <plat/cpu.h>
47#include <plat/samsung-time.h>
47 48
48#include "common.h" 49#include "common.h"
49 50
@@ -135,6 +136,7 @@ static void __init nexcoder_map_io(void)
135 s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc)); 136 s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
136 s3c24xx_init_clocks(0); 137 s3c24xx_init_clocks(0);
137 s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs)); 138 s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
139 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
138 140
139 nexcoder_sensorboard_init(); 141 nexcoder_sensorboard_init();
140} 142}
@@ -150,7 +152,7 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
150 .atag_offset = 0x100, 152 .atag_offset = 0x100,
151 .map_io = nexcoder_map_io, 153 .map_io = nexcoder_map_io,
152 .init_machine = nexcoder_init, 154 .init_machine = nexcoder_init,
153 .init_irq = s3c24xx_init_irq, 155 .init_irq = s3c2440_init_irq,
154 .init_time = s3c24xx_timer_init, 156 .init_time = samsung_timer_init,
155 .restart = s3c244x_restart, 157 .restart = s3c244x_restart,
156MACHINE_END 158MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index ae2cbdf3e3ca..58d6fbe5bf1f 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -45,6 +45,7 @@
45#include <plat/devs.h> 45#include <plat/devs.h>
46#include <plat/gpio-cfg.h> 46#include <plat/gpio-cfg.h>
47#include <plat/regs-serial.h> 47#include <plat/regs-serial.h>
48#include <plat/samsung-time.h>
48 49
49#include <mach/hardware.h> 50#include <mach/hardware.h>
50#include <mach/regs-gpio.h> 51#include <mach/regs-gpio.h>
@@ -384,6 +385,7 @@ static void __init osiris_map_io(void)
384 s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); 385 s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
385 s3c24xx_init_clocks(0); 386 s3c24xx_init_clocks(0);
386 s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); 387 s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
388 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
387 389
388 /* check for the newer revision boards with large page nand */ 390 /* check for the newer revision boards with large page nand */
389 391
@@ -424,8 +426,8 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
424 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 426 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
425 .atag_offset = 0x100, 427 .atag_offset = 0x100,
426 .map_io = osiris_map_io, 428 .map_io = osiris_map_io,
427 .init_irq = s3c24xx_init_irq, 429 .init_irq = s3c2440_init_irq,
428 .init_machine = osiris_init, 430 .init_machine = osiris_init,
429 .init_time = s3c24xx_timer_init, 431 .init_time = samsung_timer_init,
430 .restart = s3c244x_restart, 432 .restart = s3c244x_restart,
431MACHINE_END 433MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index deb0ace585b0..7e16b0740ec1 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -33,6 +33,7 @@
33#include <plat/cpu.h> 33#include <plat/cpu.h>
34#include <plat/devs.h> 34#include <plat/devs.h>
35#include <plat/regs-serial.h> 35#include <plat/regs-serial.h>
36#include <plat/samsung-time.h>
36 37
37#include "common.h" 38#include "common.h"
38#include "otom.h" 39#include "otom.h"
@@ -101,6 +102,7 @@ static void __init otom11_map_io(void)
101 s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc)); 102 s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
102 s3c24xx_init_clocks(0); 103 s3c24xx_init_clocks(0);
103 s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs)); 104 s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
105 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
104} 106}
105 107
106static void __init otom11_init(void) 108static void __init otom11_init(void)
@@ -114,7 +116,7 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
114 .atag_offset = 0x100, 116 .atag_offset = 0x100,
115 .map_io = otom11_map_io, 117 .map_io = otom11_map_io,
116 .init_machine = otom11_init, 118 .init_machine = otom11_init,
117 .init_irq = s3c24xx_init_irq, 119 .init_irq = s3c2410_init_irq,
118 .init_time = s3c24xx_timer_init, 120 .init_time = samsung_timer_init,
119 .restart = s3c2410_restart, 121 .restart = s3c2410_restart,
120MACHINE_END 122MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 84c541602661..f8feaeadb55a 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -59,6 +59,7 @@
59#include <plat/devs.h> 59#include <plat/devs.h>
60#include <plat/cpu.h> 60#include <plat/cpu.h>
61#include <plat/pm.h> 61#include <plat/pm.h>
62#include <plat/samsung-time.h>
62 63
63#include "common.h" 64#include "common.h"
64#include "common-smdk.h" 65#include "common-smdk.h"
@@ -304,6 +305,7 @@ static void __init qt2410_map_io(void)
304 s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc)); 305 s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
305 s3c24xx_init_clocks(12*1000*1000); 306 s3c24xx_init_clocks(12*1000*1000);
306 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); 307 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
308 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
307} 309}
308 310
309static void __init qt2410_machine_init(void) 311static void __init qt2410_machine_init(void)
@@ -341,8 +343,8 @@ static void __init qt2410_machine_init(void)
341MACHINE_START(QT2410, "QT2410") 343MACHINE_START(QT2410, "QT2410")
342 .atag_offset = 0x100, 344 .atag_offset = 0x100,
343 .map_io = qt2410_map_io, 345 .map_io = qt2410_map_io,
344 .init_irq = s3c24xx_init_irq, 346 .init_irq = s3c2410_init_irq,
345 .init_machine = qt2410_machine_init, 347 .init_machine = qt2410_machine_init,
346 .init_time = s3c24xx_timer_init, 348 .init_time = samsung_timer_init,
347 .restart = s3c2410_restart, 349 .restart = s3c2410_restart,
348MACHINE_END 350MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 43f3ac5a1c7a..44ca018e1f96 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -57,6 +57,7 @@
57#include <plat/devs.h> 57#include <plat/devs.h>
58#include <plat/pm.h> 58#include <plat/pm.h>
59#include <plat/regs-serial.h> 59#include <plat/regs-serial.h>
60#include <plat/samsung-time.h>
60 61
61#include "common.h" 62#include "common.h"
62#include "h1940.h" 63#include "h1940.h"
@@ -740,6 +741,7 @@ static void __init rx1950_map_io(void)
740 s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc)); 741 s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
741 s3c24xx_init_clocks(16934000); 742 s3c24xx_init_clocks(16934000);
742 s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs)); 743 s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
744 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
743 745
744 /* setup PM */ 746 /* setup PM */
745 747
@@ -810,8 +812,8 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
810 .atag_offset = 0x100, 812 .atag_offset = 0x100,
811 .map_io = rx1950_map_io, 813 .map_io = rx1950_map_io,
812 .reserve = rx1950_reserve, 814 .reserve = rx1950_reserve,
813 .init_irq = s3c24xx_init_irq, 815 .init_irq = s3c2442_init_irq,
814 .init_machine = rx1950_init_machine, 816 .init_machine = rx1950_init_machine,
815 .init_time = s3c24xx_timer_init, 817 .init_time = samsung_timer_init,
816 .restart = s3c244x_restart, 818 .restart = s3c244x_restart,
817MACHINE_END 819MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index f20418a2fb1b..3bc6231d0a1f 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -49,6 +49,7 @@
49#include <plat/devs.h> 49#include <plat/devs.h>
50#include <plat/pm.h> 50#include <plat/pm.h>
51#include <plat/regs-serial.h> 51#include <plat/regs-serial.h>
52#include <plat/samsung-time.h>
52 53
53#include "common.h" 54#include "common.h"
54#include "h1940.h" 55#include "h1940.h"
@@ -179,6 +180,7 @@ static void __init rx3715_map_io(void)
179 s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); 180 s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
180 s3c24xx_init_clocks(16934000); 181 s3c24xx_init_clocks(16934000);
181 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); 182 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
183 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
182} 184}
183 185
184/* H1940 and RX3715 need to reserve this for suspend */ 186/* H1940 and RX3715 need to reserve this for suspend */
@@ -188,11 +190,6 @@ static void __init rx3715_reserve(void)
188 memblock_reserve(0x30081000, 0x1000); 190 memblock_reserve(0x30081000, 0x1000);
189} 191}
190 192
191static void __init rx3715_init_irq(void)
192{
193 s3c24xx_init_irq();
194}
195
196static void __init rx3715_init_machine(void) 193static void __init rx3715_init_machine(void)
197{ 194{
198#ifdef CONFIG_PM_H1940 195#ifdef CONFIG_PM_H1940
@@ -210,8 +207,8 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
210 .atag_offset = 0x100, 207 .atag_offset = 0x100,
211 .map_io = rx3715_map_io, 208 .map_io = rx3715_map_io,
212 .reserve = rx3715_reserve, 209 .reserve = rx3715_reserve,
213 .init_irq = rx3715_init_irq, 210 .init_irq = s3c2440_init_irq,
214 .init_machine = rx3715_init_machine, 211 .init_machine = rx3715_init_machine,
215 .init_time = s3c24xx_timer_init, 212 .init_time = samsung_timer_init,
216 .restart = s3c244x_restart, 213 .restart = s3c244x_restart,
217MACHINE_END 214MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index cd0b1635c47e..a773789e4f38 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -51,6 +51,7 @@
51 51
52#include <plat/devs.h> 52#include <plat/devs.h>
53#include <plat/cpu.h> 53#include <plat/cpu.h>
54#include <plat/samsung-time.h>
54 55
55#include "common.h" 56#include "common.h"
56#include "common-smdk.h" 57#include "common-smdk.h"
@@ -100,6 +101,7 @@ static void __init smdk2410_map_io(void)
100 s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc)); 101 s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
101 s3c24xx_init_clocks(0); 102 s3c24xx_init_clocks(0);
102 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); 103 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
104 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
103} 105}
104 106
105static void __init smdk2410_init(void) 107static void __init smdk2410_init(void)
@@ -114,8 +116,8 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
114 /* Maintainer: Jonas Dietsche */ 116 /* Maintainer: Jonas Dietsche */
115 .atag_offset = 0x100, 117 .atag_offset = 0x100,
116 .map_io = smdk2410_map_io, 118 .map_io = smdk2410_map_io,
117 .init_irq = s3c24xx_init_irq, 119 .init_irq = s3c2410_init_irq,
118 .init_machine = smdk2410_init, 120 .init_machine = smdk2410_init,
119 .init_time = s3c24xx_timer_init, 121 .init_time = samsung_timer_init,
120 .restart = s3c2410_restart, 122 .restart = s3c2410_restart,
121MACHINE_END 123MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 79485907950f..8146e920f10d 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -44,6 +44,7 @@
44#include <plat/clock.h> 44#include <plat/clock.h>
45#include <plat/devs.h> 45#include <plat/devs.h>
46#include <plat/cpu.h> 46#include <plat/cpu.h>
47#include <plat/samsung-time.h>
47 48
48#include "common.h" 49#include "common.h"
49#include "common-smdk.h" 50#include "common-smdk.h"
@@ -105,6 +106,7 @@ static void __init smdk2413_map_io(void)
105 s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc)); 106 s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
106 s3c24xx_init_clocks(12000000); 107 s3c24xx_init_clocks(12000000);
107 s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs)); 108 s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
109 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
108} 110}
109 111
110static void __init smdk2413_machine_init(void) 112static void __init smdk2413_machine_init(void)
@@ -128,10 +130,10 @@ MACHINE_START(S3C2413, "S3C2413")
128 .atag_offset = 0x100, 130 .atag_offset = 0x100,
129 131
130 .fixup = smdk2413_fixup, 132 .fixup = smdk2413_fixup,
131 .init_irq = s3c24xx_init_irq, 133 .init_irq = s3c2412_init_irq,
132 .map_io = smdk2413_map_io, 134 .map_io = smdk2413_map_io,
133 .init_machine = smdk2413_machine_init, 135 .init_machine = smdk2413_machine_init,
134 .init_time = s3c24xx_timer_init, 136 .init_time = samsung_timer_init,
135 .restart = s3c2412_restart, 137 .restart = s3c2412_restart,
136MACHINE_END 138MACHINE_END
137 139
@@ -140,10 +142,10 @@ MACHINE_START(SMDK2412, "SMDK2412")
140 .atag_offset = 0x100, 142 .atag_offset = 0x100,
141 143
142 .fixup = smdk2413_fixup, 144 .fixup = smdk2413_fixup,
143 .init_irq = s3c24xx_init_irq, 145 .init_irq = s3c2412_init_irq,
144 .map_io = smdk2413_map_io, 146 .map_io = smdk2413_map_io,
145 .init_machine = smdk2413_machine_init, 147 .init_machine = smdk2413_machine_init,
146 .init_time = s3c24xx_timer_init, 148 .init_time = samsung_timer_init,
147 .restart = s3c2412_restart, 149 .restart = s3c2412_restart,
148MACHINE_END 150MACHINE_END
149 151
@@ -152,9 +154,9 @@ MACHINE_START(SMDK2413, "SMDK2413")
152 .atag_offset = 0x100, 154 .atag_offset = 0x100,
153 155
154 .fixup = smdk2413_fixup, 156 .fixup = smdk2413_fixup,
155 .init_irq = s3c24xx_init_irq, 157 .init_irq = s3c2412_init_irq,
156 .map_io = smdk2413_map_io, 158 .map_io = smdk2413_map_io,
157 .init_machine = smdk2413_machine_init, 159 .init_machine = smdk2413_machine_init,
158 .init_time = s3c24xx_timer_init, 160 .init_time = samsung_timer_init,
159 .restart = s3c2412_restart, 161 .restart = s3c2412_restart,
160MACHINE_END 162MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index 037a5da343bd..cb46847c66b4 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -50,6 +50,7 @@
50#include <plat/sdhci.h> 50#include <plat/sdhci.h>
51#include <linux/platform_data/usb-s3c2410_udc.h> 51#include <linux/platform_data/usb-s3c2410_udc.h>
52#include <linux/platform_data/s3c-hsudc.h> 52#include <linux/platform_data/s3c-hsudc.h>
53#include <plat/samsung-time.h>
53 54
54#include <plat/fb.h> 55#include <plat/fb.h>
55 56
@@ -221,6 +222,7 @@ static void __init smdk2416_map_io(void)
221 s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); 222 s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
222 s3c24xx_init_clocks(12000000); 223 s3c24xx_init_clocks(12000000);
223 s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); 224 s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
225 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
224} 226}
225 227
226static void __init smdk2416_machine_init(void) 228static void __init smdk2416_machine_init(void)
@@ -253,6 +255,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
253 .init_irq = s3c2416_init_irq, 255 .init_irq = s3c2416_init_irq,
254 .map_io = smdk2416_map_io, 256 .map_io = smdk2416_map_io,
255 .init_machine = smdk2416_machine_init, 257 .init_machine = smdk2416_machine_init,
256 .init_time = s3c24xx_timer_init, 258 .init_time = samsung_timer_init,
257 .restart = s3c2416_restart, 259 .restart = s3c2416_restart,
258MACHINE_END 260MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 29d31314e23c..de2e5d39a847 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -41,6 +41,7 @@
41#include <plat/clock.h> 41#include <plat/clock.h>
42#include <plat/devs.h> 42#include <plat/devs.h>
43#include <plat/cpu.h> 43#include <plat/cpu.h>
44#include <plat/samsung-time.h>
44 45
45#include "common.h" 46#include "common.h"
46#include "common-smdk.h" 47#include "common-smdk.h"
@@ -160,6 +161,7 @@ static void __init smdk2440_map_io(void)
160 s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc)); 161 s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
161 s3c24xx_init_clocks(16934400); 162 s3c24xx_init_clocks(16934400);
162 s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs)); 163 s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
164 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
163} 165}
164 166
165static void __init smdk2440_machine_init(void) 167static void __init smdk2440_machine_init(void)
@@ -175,9 +177,9 @@ MACHINE_START(S3C2440, "SMDK2440")
175 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 177 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
176 .atag_offset = 0x100, 178 .atag_offset = 0x100,
177 179
178 .init_irq = s3c24xx_init_irq, 180 .init_irq = s3c2440_init_irq,
179 .map_io = smdk2440_map_io, 181 .map_io = smdk2440_map_io,
180 .init_machine = smdk2440_machine_init, 182 .init_machine = smdk2440_machine_init,
181 .init_time = s3c24xx_timer_init, 183 .init_time = samsung_timer_init,
182 .restart = s3c244x_restart, 184 .restart = s3c244x_restart,
183MACHINE_END 185MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index b3be4c4dc7bc..9435c3bef18a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -41,6 +41,7 @@
41#include <plat/clock.h> 41#include <plat/clock.h>
42#include <plat/devs.h> 42#include <plat/devs.h>
43#include <plat/cpu.h> 43#include <plat/cpu.h>
44#include <plat/samsung-time.h>
44 45
45#include "common.h" 46#include "common.h"
46#include "common-smdk.h" 47#include "common-smdk.h"
@@ -121,6 +122,7 @@ static void __init smdk2443_map_io(void)
121 s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc)); 122 s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
122 s3c24xx_init_clocks(12000000); 123 s3c24xx_init_clocks(12000000);
123 s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs)); 124 s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
125 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
124} 126}
125 127
126static void __init smdk2443_machine_init(void) 128static void __init smdk2443_machine_init(void)
@@ -142,6 +144,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
142 .init_irq = s3c2443_init_irq, 144 .init_irq = s3c2443_init_irq,
143 .map_io = smdk2443_map_io, 145 .map_io = smdk2443_map_io,
144 .init_machine = smdk2443_machine_init, 146 .init_machine = smdk2443_machine_init,
145 .init_time = s3c24xx_timer_init, 147 .init_time = samsung_timer_init,
146 .restart = s3c2443_restart, 148 .restart = s3c2443_restart,
147MACHINE_END 149MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 24b3d79e7b2c..7fad8f055cab 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -53,6 +53,7 @@
53#include <linux/mtd/partitions.h> 53#include <linux/mtd/partitions.h>
54#include <linux/mtd/map.h> 54#include <linux/mtd/map.h>
55#include <linux/mtd/physmap.h> 55#include <linux/mtd/physmap.h>
56#include <plat/samsung-time.h>
56 57
57#include "common.h" 58#include "common.h"
58 59
@@ -136,6 +137,7 @@ static void __init tct_hammer_map_io(void)
136 s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc)); 137 s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
137 s3c24xx_init_clocks(0); 138 s3c24xx_init_clocks(0);
138 s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs)); 139 s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
140 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
139} 141}
140 142
141static void __init tct_hammer_init(void) 143static void __init tct_hammer_init(void)
@@ -147,8 +149,8 @@ static void __init tct_hammer_init(void)
147MACHINE_START(TCT_HAMMER, "TCT_HAMMER") 149MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
148 .atag_offset = 0x100, 150 .atag_offset = 0x100,
149 .map_io = tct_hammer_map_io, 151 .map_io = tct_hammer_map_io,
150 .init_irq = s3c24xx_init_irq, 152 .init_irq = s3c2410_init_irq,
151 .init_machine = tct_hammer_init, 153 .init_machine = tct_hammer_init,
152 .init_time = s3c24xx_timer_init, 154 .init_time = samsung_timer_init,
153 .restart = s3c2410_restart, 155 .restart = s3c2410_restart,
154MACHINE_END 156MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index ec42d1e4e465..42e7187fed60 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -45,6 +45,7 @@
45#include <plat/cpu.h> 45#include <plat/cpu.h>
46#include <plat/devs.h> 46#include <plat/devs.h>
47#include <plat/regs-serial.h> 47#include <plat/regs-serial.h>
48#include <plat/samsung-time.h>
48 49
49#include "bast.h" 50#include "bast.h"
50#include "common.h" 51#include "common.h"
@@ -332,6 +333,7 @@ static void __init vr1000_map_io(void)
332 s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc)); 333 s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
333 s3c24xx_init_clocks(0); 334 s3c24xx_init_clocks(0);
334 s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs)); 335 s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
336 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
335} 337}
336 338
337static void __init vr1000_init(void) 339static void __init vr1000_init(void)
@@ -353,7 +355,7 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
353 .atag_offset = 0x100, 355 .atag_offset = 0x100,
354 .map_io = vr1000_map_io, 356 .map_io = vr1000_map_io,
355 .init_machine = vr1000_init, 357 .init_machine = vr1000_init,
356 .init_irq = s3c24xx_init_irq, 358 .init_irq = s3c2410_init_irq,
357 .init_time = s3c24xx_timer_init, 359 .init_time = samsung_timer_init,
358 .restart = s3c2410_restart, 360 .restart = s3c2410_restart,
359MACHINE_END 361MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 239129c2d8bc..b66588428ec9 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -44,6 +44,7 @@
44#include <plat/clock.h> 44#include <plat/clock.h>
45#include <plat/devs.h> 45#include <plat/devs.h>
46#include <plat/cpu.h> 46#include <plat/cpu.h>
47#include <plat/samsung-time.h>
47 48
48#include "common.h" 49#include "common.h"
49 50
@@ -142,6 +143,7 @@ static void __init vstms_map_io(void)
142 s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); 143 s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
143 s3c24xx_init_clocks(12000000); 144 s3c24xx_init_clocks(12000000);
144 s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); 145 s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
146 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
145} 147}
146 148
147static void __init vstms_init(void) 149static void __init vstms_init(void)
@@ -156,9 +158,9 @@ MACHINE_START(VSTMS, "VSTMS")
156 .atag_offset = 0x100, 158 .atag_offset = 0x100,
157 159
158 .fixup = vstms_fixup, 160 .fixup = vstms_fixup,
159 .init_irq = s3c24xx_init_irq, 161 .init_irq = s3c2412_init_irq,
160 .init_machine = vstms_init, 162 .init_machine = vstms_init,
161 .map_io = vstms_map_io, 163 .map_io = vstms_map_io,
162 .init_time = s3c24xx_timer_init, 164 .init_time = samsung_timer_init,
163 .restart = s3c2412_restart, 165 .restart = s3c2412_restart,
164MACHINE_END 166MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index 4c4bc1c83b77..d75f95e487ee 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -29,6 +29,7 @@
29 29
30#include <plat/cpu.h> 30#include <plat/cpu.h>
31#include <plat/pm.h> 31#include <plat/pm.h>
32#include <plat/wakeup-mask.h>
32 33
33#include "regs-dsc.h" 34#include "regs-dsc.h"
34#include "s3c2412-power.h" 35#include "s3c2412-power.h"
@@ -51,8 +52,15 @@ static int s3c2412_cpu_suspend(unsigned long arg)
51 return 1; /* Aborting suspend */ 52 return 1; /* Aborting suspend */
52} 53}
53 54
55/* mapping of interrupts to parts of the wakeup mask */
56static struct samsung_wakeup_mask wake_irqs[] = {
57 { .irq = IRQ_RTC, .bit = S3C2412_PWRCFG_RTC_MASKIRQ, },
58};
59
54static void s3c2412_pm_prepare(void) 60static void s3c2412_pm_prepare(void)
55{ 61{
62 samsung_sync_wakemask(S3C2412_PWRCFG,
63 wake_irqs, ARRAY_SIZE(wake_irqs));
56} 64}
57 65
58static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif) 66static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 07:07:39 -0400