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authorKukjin Kim <kgene.kim@samsung.com>2013-01-31 19:54:38 -0500
committerKukjin Kim <kgene.kim@samsung.com>2013-02-03 19:17:10 -0500
commit09ec1d7ea67f6e23b6ef2178fa2ec48fd65477dc (patch)
tree38318b5c98f48754521a288f40e3c77a1fe8a623 /arch/arm/mach-s3c24xx
parentf44ddba3635e35317057e976888d4a12dcb0f842 (diff)
ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/
This patch is for just moving plat-s3c24xx/*.c into mach-s3c24xx/, so that we could remove plat-s3c24xx directory. But since the PLAT_S3C24XX is used in drivers, the statement is not deleted and it will be sorted out next time. Cc: Ben Dooks <ben-linux@fluff.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c24xx')
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig104
-rw-r--r--arch/arm/mach-s3c24xx/Makefile14
-rw-r--r--arch/arm/mach-s3c24xx/clock-dclk.c195
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2410.c252
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-debugfs.c198
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-utils.c63
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq.c715
-rw-r--r--arch/arm/mach-s3c24xx/dma.c1468
-rw-r--r--arch/arm/mach-s3c24xx/iotiming-s3c2410.c477
-rw-r--r--arch/arm/mach-s3c24xx/iotiming-s3c2412.c285
-rw-r--r--arch/arm/mach-s3c24xx/irq.c822
11 files changed, 4592 insertions, 1 deletions
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 67df58bdc096..31eacad5b3e9 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -9,6 +9,15 @@
9 9
10if ARCH_S3C24XX 10if ARCH_S3C24XX
11 11
12config PLAT_S3C24XX
13 def_bool y
14 select ARCH_REQUIRE_GPIOLIB
15 select NO_IOPORT
16 select S3C_DEV_NAND
17 select IRQ_DOMAIN
18 help
19 Base platform code for any Samsung S3C24XX device
20
12menu "SAMSUNG S3C24XX SoCs Support" 21menu "SAMSUNG S3C24XX SoCs Support"
13 22
14comment "S3C24XX SoCs" 23comment "S3C24XX SoCs"
@@ -83,6 +92,17 @@ config CPU_S3C2443
83 92
84# common code 93# common code
85 94
95config S3C2410_CLOCK
96 bool
97 help
98 Clock code for the S3C2410, and similar processors which
99 is currently includes the S3C2410, S3C2440, S3C2442.
100
101config S3C24XX_DCLK
102 bool
103 help
104 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
105
86config S3C24XX_SMDK 106config S3C24XX_SMDK
87 bool 107 bool
88 help 108 help
@@ -111,6 +131,22 @@ config S3C24XX_SETUP_TS
111 help 131 help
112 Compile in platform device definition for Samsung TouchScreen. 132 Compile in platform device definition for Samsung TouchScreen.
113 133
134config S3C24XX_DMA
135 bool "S3C2410 DMA support"
136 depends on ARCH_S3C24XX
137 select S3C_DMA
138 help
139 S3C2410 DMA support. This is needed for drivers like sound which
140 use the S3C2410's DMA system to move data to and from the
141 peripheral blocks.
142
143config S3C2410_DMA_DEBUG
144 bool "S3C2410 DMA support debug"
145 depends on ARCH_S3C24XX && S3C2410_DMA
146 help
147 Enable debugging output for the DMA code. This option sends info
148 to the kernel log, at priority KERN_DEBUG.
149
114config S3C2410_DMA 150config S3C2410_DMA
115 bool 151 bool
116 depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442) 152 depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@@ -123,6 +159,74 @@ config S3C2410_PM
123 help 159 help
124 Power Management code common to S3C2410 and better 160 Power Management code common to S3C2410 and better
125 161
162# low-level serial option nodes
163
164config CPU_LLSERIAL_S3C2410_ONLY
165 bool
166 default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
167
168config CPU_LLSERIAL_S3C2440_ONLY
169 bool
170 default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
171
172config CPU_LLSERIAL_S3C2410
173 bool
174 help
175 Selected if there is an S3C2410 (or register compatible) serial
176 low-level implementation needed
177
178config CPU_LLSERIAL_S3C2440
179 bool
180 help
181 Selected if there is an S3C2440 (or register compatible) serial
182 low-level implementation needed
183
184# gpio configurations
185
186config S3C24XX_GPIO_EXTRA
187 int
188 default 128 if S3C24XX_GPIO_EXTRA128
189 default 64 if S3C24XX_GPIO_EXTRA64
190 default 16 if ARCH_H1940
191 default 0
192
193config S3C24XX_GPIO_EXTRA64
194 bool
195 help
196 Add an extra 64 gpio numbers to the available GPIO pool. This is
197 available for boards that need extra gpios for external devices.
198
199config S3C24XX_GPIO_EXTRA128
200 bool
201 help
202 Add an extra 128 gpio numbers to the available GPIO pool. This is
203 available for boards that need extra gpios for external devices.
204
205# cpu frequency items common between s3c2410 and s3c2440/s3c2442
206
207config S3C2410_IOTIMING
208 bool
209 depends on CPU_FREQ_S3C24XX
210 help
211 Internal node to select io timing code that is common to the s3c2410
212 and s3c2440/s3c2442 cpu frequency support.
213
214config S3C2410_CPUFREQ_UTILS
215 bool
216 depends on CPU_FREQ_S3C24XX
217 help
218 Internal node to select timing code that is common to the s3c2410
219 and s3c2440/s3c244 cpu frequency support.
220
221# cpu frequency support common to s3c2412, s3c2413 and s3c2442
222
223config S3C2412_IOTIMING
224 bool
225 depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
226 help
227 Intel node to select io timing code that is common to the s3c2412
228 and the s3c2443.
229
126# cpu-specific sections 230# cpu-specific sections
127 231
128if CPU_S3C2410 232if CPU_S3C2410
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 1d67582da41a..af53d27d5c36 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,7 +14,7 @@ obj- :=
14 14
15# core 15# core
16 16
17obj-y += common.o 17obj-y += common.o irq.o
18 18
19obj-$(CONFIG_CPU_S3C2410) += s3c2410.o 19obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
20obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o 20obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o
@@ -47,9 +47,21 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
47 47
48# common code 48# common code
49 49
50obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
51obj-$(CONFIG_S3C24XX_DMA) += dma.o
52
53obj-$(CONFIG_S3C2410_CLOCK) += clock-s3c2410.o
54obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
55
56obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
57obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
58
50obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o 59obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o
51obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o 60obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o
52 61
62obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpufreq.o
63obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o
64
53# 65#
54# machine support 66# machine support
55# following is ordered alphabetically by option text. 67# following is ordered alphabetically by option text.
diff --git a/arch/arm/mach-s3c24xx/clock-dclk.c b/arch/arm/mach-s3c24xx/clock-dclk.c
new file mode 100644
index 000000000000..1edd9b2369c5
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/clock-dclk.c
@@ -0,0 +1,195 @@
1/*
2 * Copyright (c) 2004-2008 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C24XX - definitions for DCLK and CLKOUT registers
11 */
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17
18#include <mach/regs-clock.h>
19#include <mach/regs-gpio.h>
20
21#include <plat/clock.h>
22#include <plat/cpu.h>
23
24/* clocks that could be registered by external code */
25
26static int s3c24xx_dclk_enable(struct clk *clk, int enable)
27{
28 unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
29
30 if (enable)
31 dclkcon |= clk->ctrlbit;
32 else
33 dclkcon &= ~clk->ctrlbit;
34
35 __raw_writel(dclkcon, S3C24XX_DCLKCON);
36
37 return 0;
38}
39
40static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
41{
42 unsigned long dclkcon;
43 unsigned int uclk;
44
45 if (parent == &clk_upll)
46 uclk = 1;
47 else if (parent == &clk_p)
48 uclk = 0;
49 else
50 return -EINVAL;
51
52 clk->parent = parent;
53
54 dclkcon = __raw_readl(S3C24XX_DCLKCON);
55
56 if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
57 if (uclk)
58 dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
59 else
60 dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
61 } else {
62 if (uclk)
63 dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
64 else
65 dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
66 }
67
68 __raw_writel(dclkcon, S3C24XX_DCLKCON);
69
70 return 0;
71}
72static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
73{
74 unsigned long div;
75
76 if ((rate == 0) || !clk->parent)
77 return 0;
78
79 div = clk_get_rate(clk->parent) / rate;
80 if (div < 2)
81 div = 2;
82 else if (div > 16)
83 div = 16;
84
85 return div;
86}
87
88static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
89 unsigned long rate)
90{
91 unsigned long div = s3c24xx_calc_div(clk, rate);
92
93 if (div == 0)
94 return 0;
95
96 return clk_get_rate(clk->parent) / div;
97}
98
99static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
100{
101 unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
102
103 if (div == 0)
104 return -EINVAL;
105
106 if (clk == &s3c24xx_dclk0) {
107 mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
108 S3C2410_DCLKCON_DCLK0_CMP_MASK;
109 data = S3C2410_DCLKCON_DCLK0_DIV(div) |
110 S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
111 } else if (clk == &s3c24xx_dclk1) {
112 mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
113 S3C2410_DCLKCON_DCLK1_CMP_MASK;
114 data = S3C2410_DCLKCON_DCLK1_DIV(div) |
115 S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
116 } else
117 return -EINVAL;
118
119 clk->rate = clk_get_rate(clk->parent) / div;
120 __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
121 S3C24XX_DCLKCON);
122 return clk->rate;
123}
124static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
125{
126 unsigned long mask;
127 unsigned long source;
128
129 /* calculate the MISCCR setting for the clock */
130
131 if (parent == &clk_mpll)
132 source = S3C2410_MISCCR_CLK0_MPLL;
133 else if (parent == &clk_upll)
134 source = S3C2410_MISCCR_CLK0_UPLL;
135 else if (parent == &clk_f)
136 source = S3C2410_MISCCR_CLK0_FCLK;
137 else if (parent == &clk_h)
138 source = S3C2410_MISCCR_CLK0_HCLK;
139 else if (parent == &clk_p)
140 source = S3C2410_MISCCR_CLK0_PCLK;
141 else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
142 source = S3C2410_MISCCR_CLK0_DCLK0;
143 else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
144 source = S3C2410_MISCCR_CLK0_DCLK0;
145 else
146 return -EINVAL;
147
148 clk->parent = parent;
149
150 if (clk == &s3c24xx_clkout0)
151 mask = S3C2410_MISCCR_CLK0_MASK;
152 else {
153 source <<= 4;
154 mask = S3C2410_MISCCR_CLK1_MASK;
155 }
156
157 s3c2410_modify_misccr(mask, source);
158 return 0;
159}
160
161/* external clock definitions */
162
163static struct clk_ops dclk_ops = {
164 .set_parent = s3c24xx_dclk_setparent,
165 .set_rate = s3c24xx_set_dclk_rate,
166 .round_rate = s3c24xx_round_dclk_rate,
167};
168
169struct clk s3c24xx_dclk0 = {
170 .name = "dclk0",
171 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
172 .enable = s3c24xx_dclk_enable,
173 .ops = &dclk_ops,
174};
175
176struct clk s3c24xx_dclk1 = {
177 .name = "dclk1",
178 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
179 .enable = s3c24xx_dclk_enable,
180 .ops = &dclk_ops,
181};
182
183static struct clk_ops clkout_ops = {
184 .set_parent = s3c24xx_clkout_setparent,
185};
186
187struct clk s3c24xx_clkout0 = {
188 .name = "clkout0",
189 .ops = &clkout_ops,
190};
191
192struct clk s3c24xx_clkout1 = {
193 .name = "clkout1",
194 .ops = &clkout_ops,
195};
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
new file mode 100644
index 000000000000..641266f3d152
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -0,0 +1,252 @@
1/*
2 * Copyright (c) 2006 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
4 *
5 * S3C2410,S3C2440,S3C2442 Clock control support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/list.h>
26#include <linux/errno.h>
27#include <linux/err.h>
28#include <linux/device.h>
29#include <linux/clk.h>
30#include <linux/mutex.h>
31#include <linux/delay.h>
32#include <linux/serial_core.h>
33#include <linux/io.h>
34
35#include <asm/mach/map.h>
36
37#include <mach/hardware.h>
38
39#include <plat/regs-serial.h>
40#include <mach/regs-clock.h>
41#include <mach/regs-gpio.h>
42
43#include <plat/s3c2410.h>
44#include <plat/clock.h>
45#include <plat/cpu.h>
46
47int s3c2410_clkcon_enable(struct clk *clk, int enable)
48{
49 unsigned int clocks = clk->ctrlbit;
50 unsigned long clkcon;
51
52 clkcon = __raw_readl(S3C2410_CLKCON);
53
54 if (enable)
55 clkcon |= clocks;
56 else
57 clkcon &= ~clocks;
58
59 /* ensure none of the special function bits set */
60 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
61
62 __raw_writel(clkcon, S3C2410_CLKCON);
63
64 return 0;
65}
66
67static int s3c2410_upll_enable(struct clk *clk, int enable)
68{
69 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
70 unsigned long orig = clkslow;
71
72 if (enable)
73 clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
74 else
75 clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
76
77 __raw_writel(clkslow, S3C2410_CLKSLOW);
78
79 /* if we started the UPLL, then allow to settle */
80
81 if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
82 udelay(200);
83
84 return 0;
85}
86
87/* standard clock definitions */
88
89static struct clk init_clocks_off[] = {
90 {
91 .name = "nand",
92 .parent = &clk_h,
93 .enable = s3c2410_clkcon_enable,
94 .ctrlbit = S3C2410_CLKCON_NAND,
95 }, {
96 .name = "sdi",
97 .parent = &clk_p,
98 .enable = s3c2410_clkcon_enable,
99 .ctrlbit = S3C2410_CLKCON_SDI,
100 }, {
101 .name = "adc",
102 .parent = &clk_p,
103 .enable = s3c2410_clkcon_enable,
104 .ctrlbit = S3C2410_CLKCON_ADC,
105 }, {
106 .name = "i2c",
107 .parent = &clk_p,
108 .enable = s3c2410_clkcon_enable,
109 .ctrlbit = S3C2410_CLKCON_IIC,
110 }, {
111 .name = "iis",
112 .parent = &clk_p,
113 .enable = s3c2410_clkcon_enable,
114 .ctrlbit = S3C2410_CLKCON_IIS,
115 }, {
116 .name = "spi",
117 .parent = &clk_p,
118 .enable = s3c2410_clkcon_enable,
119 .ctrlbit = S3C2410_CLKCON_SPI,
120 }
121};
122
123static struct clk init_clocks[] = {
124 {
125 .name = "lcd",
126 .parent = &clk_h,
127 .enable = s3c2410_clkcon_enable,
128 .ctrlbit = S3C2410_CLKCON_LCDC,
129 }, {
130 .name = "gpio",
131 .parent = &clk_p,
132 .enable = s3c2410_clkcon_enable,
133 .ctrlbit = S3C2410_CLKCON_GPIO,
134 }, {
135 .name = "usb-host",
136 .parent = &clk_h,
137 .enable = s3c2410_clkcon_enable,
138 .ctrlbit = S3C2410_CLKCON_USBH,
139 }, {
140 .name = "usb-device",
141 .parent = &clk_h,
142 .enable = s3c2410_clkcon_enable,
143 .ctrlbit = S3C2410_CLKCON_USBD,
144 }, {
145 .name = "timers",
146 .parent = &clk_p,
147 .enable = s3c2410_clkcon_enable,
148 .ctrlbit = S3C2410_CLKCON_PWMT,
149 }, {
150 .name = "uart",
151 .devname = "s3c2410-uart.0",
152 .parent = &clk_p,
153 .enable = s3c2410_clkcon_enable,
154 .ctrlbit = S3C2410_CLKCON_UART0,
155 }, {
156 .name = "uart",
157 .devname = "s3c2410-uart.1",
158 .parent = &clk_p,
159 .enable = s3c2410_clkcon_enable,
160 .ctrlbit = S3C2410_CLKCON_UART1,
161 }, {
162 .name = "uart",
163 .devname = "s3c2410-uart.2",
164 .parent = &clk_p,
165 .enable = s3c2410_clkcon_enable,
166 .ctrlbit = S3C2410_CLKCON_UART2,
167 }, {
168 .name = "rtc",
169 .parent = &clk_p,
170 .enable = s3c2410_clkcon_enable,
171 .ctrlbit = S3C2410_CLKCON_RTC,
172 }, {
173 .name = "watchdog",
174 .parent = &clk_p,
175 .ctrlbit = 0,
176 }, {
177 .name = "usb-bus-host",
178 .parent = &clk_usb_bus,
179 }, {
180 .name = "usb-bus-gadget",
181 .parent = &clk_usb_bus,
182 },
183};
184
185/* s3c2410_baseclk_add()
186 *
187 * Add all the clocks used by the s3c2410 or compatible CPUs
188 * such as the S3C2440 and S3C2442.
189 *
190 * We cannot use a system device as we are needed before any
191 * of the init-calls that initialise the devices are actually
192 * done.
193*/
194
195int __init s3c2410_baseclk_add(void)
196{
197 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
198 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
199 struct clk *clkp;
200 struct clk *xtal;
201 int ret;
202 int ptr;
203
204 clk_upll.enable = s3c2410_upll_enable;
205
206 if (s3c24xx_register_clock(&clk_usb_bus) < 0)
207 printk(KERN_ERR "failed to register usb bus clock\n");
208
209 /* register clocks from clock array */
210
211 clkp = init_clocks;
212 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
213 /* ensure that we note the clock state */
214
215 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
216
217 ret = s3c24xx_register_clock(clkp);
218 if (ret < 0) {
219 printk(KERN_ERR "Failed to register clock %s (%d)\n",
220 clkp->name, ret);
221 }
222 }
223
224 /* We must be careful disabling the clocks we are not intending to
225 * be using at boot time, as subsystems such as the LCD which do
226 * their own DMA requests to the bus can cause the system to lockup
227 * if they where in the middle of requesting bus access.
228 *
229 * Disabling the LCD clock if the LCD is active is very dangerous,
230 * and therefore the bootloader should be careful to not enable
231 * the LCD clock if it is not needed.
232 */
233
234 /* install (and disable) the clocks we do not need immediately */
235
236 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
237 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
238
239 /* show the clock-slow value */
240
241 xtal = clk_get(NULL, "xtal");
242
243 printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
244 print_mhz(clk_get_rate(xtal) /
245 ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
246 (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
247 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
248 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
249
250 s3c_pwmclk_init();
251 return 0;
252}
diff --git a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
new file mode 100644
index 000000000000..9b7b4289d66c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
@@ -0,0 +1,198 @@
1/*
2 * Copyright (c) 2009 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX CPU Frequency scaling - debugfs status support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/export.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/cpufreq.h>
18#include <linux/debugfs.h>
19#include <linux/seq_file.h>
20#include <linux/err.h>
21
22#include <plat/cpu-freq-core.h>
23
24static struct dentry *dbgfs_root;
25static struct dentry *dbgfs_file_io;
26static struct dentry *dbgfs_file_info;
27static struct dentry *dbgfs_file_board;
28
29#define print_ns(x) ((x) / 10), ((x) % 10)
30
31static void show_max(struct seq_file *seq, struct s3c_freq *f)
32{
33 seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n",
34 f->fclk, f->hclk, f->pclk, f->armclk);
35}
36
37static int board_show(struct seq_file *seq, void *p)
38{
39 struct s3c_cpufreq_config *cfg;
40 struct s3c_cpufreq_board *brd;
41
42 cfg = s3c_cpufreq_getconfig();
43 if (!cfg) {
44 seq_printf(seq, "no configuration registered\n");
45 return 0;
46 }
47
48 brd = cfg->board;
49 if (!brd) {
50 seq_printf(seq, "no board definition set?\n");
51 return 0;
52 }
53
54 seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh);
55 seq_printf(seq, "auto_io=%u\n", brd->auto_io);
56 seq_printf(seq, "need_io=%u\n", brd->need_io);
57
58 show_max(seq, &brd->max);
59
60
61 return 0;
62}
63
64static int fops_board_open(struct inode *inode, struct file *file)
65{
66 return single_open(file, board_show, NULL);
67}
68
69static const struct file_operations fops_board = {
70 .open = fops_board_open,
71 .read = seq_read,
72 .llseek = seq_lseek,
73 .release = single_release,
74 .owner = THIS_MODULE,
75};
76
77static int info_show(struct seq_file *seq, void *p)
78{
79 struct s3c_cpufreq_config *cfg;
80
81 cfg = s3c_cpufreq_getconfig();
82 if (!cfg) {
83 seq_printf(seq, "no configuration registered\n");
84 return 0;
85 }
86
87 seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk);
88 seq_printf(seq, " HCLK %ld Hz (%lu.%lu ns)\n",
89 cfg->freq.hclk, print_ns(cfg->freq.hclk_tns));
90 seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk);
91 seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk);
92 seq_printf(seq, "\n");
93
94 show_max(seq, &cfg->max);
95
96 seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n",
97 cfg->divs.h_divisor, cfg->divs.p_divisor,
98 cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off");
99 seq_printf(seq, "\n");
100
101 seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll);
102
103 return 0;
104}
105
106static int fops_info_open(struct inode *inode, struct file *file)
107{
108 return single_open(file, info_show, NULL);
109}
110
111static const struct file_operations fops_info = {
112 .open = fops_info_open,
113 .read = seq_read,
114 .llseek = seq_lseek,
115 .release = single_release,
116 .owner = THIS_MODULE,
117};
118
119static int io_show(struct seq_file *seq, void *p)
120{
121 void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *);
122 struct s3c_cpufreq_config *cfg;
123 struct s3c_iotimings *iot;
124 union s3c_iobank *iob;
125 int bank;
126
127 cfg = s3c_cpufreq_getconfig();
128 if (!cfg) {
129 seq_printf(seq, "no configuration registered\n");
130 return 0;
131 }
132
133 show_bank = cfg->info->debug_io_show;
134 if (!show_bank) {
135 seq_printf(seq, "no code to show bank timing\n");
136 return 0;
137 }
138
139 iot = s3c_cpufreq_getiotimings();
140 if (!iot) {
141 seq_printf(seq, "no io timings registered\n");
142 return 0;
143 }
144
145 seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns));
146
147 for (bank = 0; bank < MAX_BANKS; bank++) {
148 iob = &iot->bank[bank];
149
150 seq_printf(seq, "bank %d: ", bank);
151
152 if (!iob->io_2410) {
153 seq_printf(seq, "nothing set\n");
154 continue;
155 }
156
157 show_bank(seq, cfg, iob);
158 }
159
160 return 0;
161}
162
163static int fops_io_open(struct inode *inode, struct file *file)
164{
165 return single_open(file, io_show, NULL);
166}
167
168static const struct file_operations fops_io = {
169 .open = fops_io_open,
170 .read = seq_read,
171 .llseek = seq_lseek,
172 .release = single_release,
173 .owner = THIS_MODULE,
174};
175
176
177static int __init s3c_freq_debugfs_init(void)
178{
179 dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL);
180 if (IS_ERR(dbgfs_root)) {
181 printk(KERN_ERR "%s: error creating debugfs root\n", __func__);
182 return PTR_ERR(dbgfs_root);
183 }
184
185 dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root,
186 NULL, &fops_io);
187
188 dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root,
189 NULL, &fops_info);
190
191 dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root,
192 NULL, &fops_board);
193
194 return 0;
195}
196
197late_initcall(s3c_freq_debugfs_init);
198
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
new file mode 100644
index 000000000000..89e4e2b7a82e
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright (c) 2009 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/cpufreq.h>
16#include <linux/io.h>
17
18#include <mach/map.h>
19#include <mach/regs-mem.h>
20#include <mach/regs-clock.h>
21
22#include <plat/cpu-freq-core.h>
23
24/**
25 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
26 * @cfg: The frequency configuration
27 *
28 * Set the SDRAM refresh value appropriately for the configured
29 * frequency.
30 */
31void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
32{
33 struct s3c_cpufreq_board *board = cfg->board;
34 unsigned long refresh;
35 unsigned long refval;
36
37 /* Reduce both the refresh time (in ns) and the frequency (in MHz)
38 * down to ensure that we do not overflow 32 bit numbers.
39 *
40 * This should work for HCLK up to 133MHz and refresh period up
41 * to 30usec.
42 */
43
44 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
45 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
46 refresh = (1 << 11) + 1 - refresh;
47
48 s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
49
50 refval = __raw_readl(S3C2410_REFRESH);
51 refval &= ~((1 << 12) - 1);
52 refval |= refresh;
53 __raw_writel(refval, S3C2410_REFRESH);
54}
55
56/**
57 * s3c2410_set_fvco - set the PLL value
58 * @cfg: The frequency configuration
59 */
60void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
61{
62 __raw_writel(cfg->pll.index, S3C2410_MPLLCON);
63}
diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c
new file mode 100644
index 000000000000..5f181e733eee
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq.c
@@ -0,0 +1,715 @@
1/*
2 * Copyright (c) 2006-2008 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX CPU Frequency scaling
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/cpufreq.h>
18#include <linux/cpu.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/io.h>
22#include <linux/device.h>
23#include <linux/sysfs.h>
24#include <linux/slab.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28
29#include <plat/cpu.h>
30#include <plat/clock.h>
31#include <plat/cpu-freq-core.h>
32
33#include <mach/regs-clock.h>
34
35/* note, cpufreq support deals in kHz, no Hz */
36
37static struct cpufreq_driver s3c24xx_driver;
38static struct s3c_cpufreq_config cpu_cur;
39static struct s3c_iotimings s3c24xx_iotiming;
40static struct cpufreq_frequency_table *pll_reg;
41static unsigned int last_target = ~0;
42static unsigned int ftab_size;
43static struct cpufreq_frequency_table *ftab;
44
45static struct clk *_clk_mpll;
46static struct clk *_clk_xtal;
47static struct clk *clk_fclk;
48static struct clk *clk_hclk;
49static struct clk *clk_pclk;
50static struct clk *clk_arm;
51
52#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
53struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
54{
55 return &cpu_cur;
56}
57
58struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
59{
60 return &s3c24xx_iotiming;
61}
62#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */
63
64static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
65{
66 unsigned long fclk, pclk, hclk, armclk;
67
68 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
69 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
70 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
71 cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
72
73 cfg->pll.index = __raw_readl(S3C2410_MPLLCON);
74 cfg->pll.frequency = fclk;
75
76 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
77
78 cfg->divs.h_divisor = fclk / hclk;
79 cfg->divs.p_divisor = fclk / pclk;
80}
81
82static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
83{
84 unsigned long pll = cfg->pll.frequency;
85
86 cfg->freq.fclk = pll;
87 cfg->freq.hclk = pll / cfg->divs.h_divisor;
88 cfg->freq.pclk = pll / cfg->divs.p_divisor;
89
90 /* convert hclk into 10ths of nanoseconds for io calcs */
91 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
92}
93
94static inline int closer(unsigned int target, unsigned int n, unsigned int c)
95{
96 int diff_cur = abs(target - c);
97 int diff_new = abs(target - n);
98
99 return (diff_new < diff_cur);
100}
101
102static void s3c_cpufreq_show(const char *pfx,
103 struct s3c_cpufreq_config *cfg)
104{
105 s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
106 pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
107 cfg->freq.hclk, cfg->divs.h_divisor,
108 cfg->freq.pclk, cfg->divs.p_divisor);
109}
110
111/* functions to wrapper the driver info calls to do the cpu specific work */
112
113static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
114{
115 if (cfg->info->set_iotiming)
116 (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
117}
118
119static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
120{
121 if (cfg->info->calc_iotiming)
122 return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
123
124 return 0;
125}
126
127static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
128{
129 (cfg->info->set_refresh)(cfg);
130}
131
132static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
133{
134 (cfg->info->set_divs)(cfg);
135}
136
137static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
138{
139 return (cfg->info->calc_divs)(cfg);
140}
141
142static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
143{
144 (cfg->info->set_fvco)(cfg);
145}
146
147static inline void s3c_cpufreq_resume_clocks(void)
148{
149 cpu_cur.info->resume_clocks();
150}
151
152static inline void s3c_cpufreq_updateclk(struct clk *clk,
153 unsigned int freq)
154{
155 clk_set_rate(clk, freq);
156}
157
158static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
159 unsigned int target_freq,
160 struct cpufreq_frequency_table *pll)
161{
162 struct s3c_cpufreq_freqs freqs;
163 struct s3c_cpufreq_config cpu_new;
164 unsigned long flags;
165
166 cpu_new = cpu_cur; /* copy new from current */
167
168 s3c_cpufreq_show("cur", &cpu_cur);
169
170 /* TODO - check for DMA currently outstanding */
171
172 cpu_new.pll = pll ? *pll : cpu_cur.pll;
173
174 if (pll)
175 freqs.pll_changing = 1;
176
177 /* update our frequencies */
178
179 cpu_new.freq.armclk = target_freq;
180 cpu_new.freq.fclk = cpu_new.pll.frequency;
181
182 if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
183 printk(KERN_ERR "no divisors for %d\n", target_freq);
184 goto err_notpossible;
185 }
186
187 s3c_freq_dbg("%s: got divs\n", __func__);
188
189 s3c_cpufreq_calc(&cpu_new);
190
191 s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
192
193 if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
194 if (s3c_cpufreq_calcio(&cpu_new) < 0) {
195 printk(KERN_ERR "%s: no IO timings\n", __func__);
196 goto err_notpossible;
197 }
198 }
199
200 s3c_cpufreq_show("new", &cpu_new);
201
202 /* setup our cpufreq parameters */
203
204 freqs.old = cpu_cur.freq;
205 freqs.new = cpu_new.freq;
206
207 freqs.freqs.cpu = 0;
208 freqs.freqs.old = cpu_cur.freq.armclk / 1000;
209 freqs.freqs.new = cpu_new.freq.armclk / 1000;
210
211 /* update f/h/p clock settings before we issue the change
212 * notification, so that drivers do not need to do anything
213 * special if they want to recalculate on CPUFREQ_PRECHANGE. */
214
215 s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
216 s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
217 s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
218 s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
219
220 /* start the frequency change */
221
222 if (policy)
223 cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE);
224
225 /* If hclk is staying the same, then we do not need to
226 * re-write the IO or the refresh timings whilst we are changing
227 * speed. */
228
229 local_irq_save(flags);
230
231 /* is our memory clock slowing down? */
232 if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
233 s3c_cpufreq_setrefresh(&cpu_new);
234 s3c_cpufreq_setio(&cpu_new);
235 }
236
237 if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
238 /* not changing PLL, just set the divisors */
239
240 s3c_cpufreq_setdivs(&cpu_new);
241 } else {
242 if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
243 /* slow the cpu down, then set divisors */
244
245 s3c_cpufreq_setfvco(&cpu_new);
246 s3c_cpufreq_setdivs(&cpu_new);
247 } else {
248 /* set the divisors, then speed up */
249
250 s3c_cpufreq_setdivs(&cpu_new);
251 s3c_cpufreq_setfvco(&cpu_new);
252 }
253 }
254
255 /* did our memory clock speed up */
256 if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
257 s3c_cpufreq_setrefresh(&cpu_new);
258 s3c_cpufreq_setio(&cpu_new);
259 }
260
261 /* update our current settings */
262 cpu_cur = cpu_new;
263
264 local_irq_restore(flags);
265
266 /* notify everyone we've done this */
267 if (policy)
268 cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE);
269
270 s3c_freq_dbg("%s: finished\n", __func__);
271 return 0;
272
273 err_notpossible:
274 printk(KERN_ERR "no compatible settings for %d\n", target_freq);
275 return -EINVAL;
276}
277
278/* s3c_cpufreq_target
279 *
280 * called by the cpufreq core to adjust the frequency that the CPU
281 * is currently running at.
282 */
283
284static int s3c_cpufreq_target(struct cpufreq_policy *policy,
285 unsigned int target_freq,
286 unsigned int relation)
287{
288 struct cpufreq_frequency_table *pll;
289 unsigned int index;
290
291 /* avoid repeated calls which cause a needless amout of duplicated
292 * logging output (and CPU time as the calculation process is
293 * done) */
294 if (target_freq == last_target)
295 return 0;
296
297 last_target = target_freq;
298
299 s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
300 __func__, policy, target_freq, relation);
301
302 if (ftab) {
303 if (cpufreq_frequency_table_target(policy, ftab,
304 target_freq, relation,
305 &index)) {
306 s3c_freq_dbg("%s: table failed\n", __func__);
307 return -EINVAL;
308 }
309
310 s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
311 target_freq, index, ftab[index].frequency);
312 target_freq = ftab[index].frequency;
313 }
314
315 target_freq *= 1000; /* convert target to Hz */
316
317 /* find the settings for our new frequency */
318
319 if (!pll_reg || cpu_cur.lock_pll) {
320 /* either we've not got any PLL values, or we've locked
321 * to the current one. */
322 pll = NULL;
323 } else {
324 struct cpufreq_policy tmp_policy;
325 int ret;
326
327 /* we keep the cpu pll table in Hz, to ensure we get an
328 * accurate value for the PLL output. */
329
330 tmp_policy.min = policy->min * 1000;
331 tmp_policy.max = policy->max * 1000;
332 tmp_policy.cpu = policy->cpu;
333
334 /* cpufreq_frequency_table_target uses a pointer to 'index'
335 * which is the number of the table entry, not the value of
336 * the table entry's index field. */
337
338 ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg,
339 target_freq, relation,
340 &index);
341
342 if (ret < 0) {
343 printk(KERN_ERR "%s: no PLL available\n", __func__);
344 goto err_notpossible;
345 }
346
347 pll = pll_reg + index;
348
349 s3c_freq_dbg("%s: target %u => %u\n",
350 __func__, target_freq, pll->frequency);
351
352 target_freq = pll->frequency;
353 }
354
355 return s3c_cpufreq_settarget(policy, target_freq, pll);
356
357 err_notpossible:
358 printk(KERN_ERR "no compatible settings for %d\n", target_freq);
359 return -EINVAL;
360}
361
362static unsigned int s3c_cpufreq_get(unsigned int cpu)
363{
364 return clk_get_rate(clk_arm) / 1000;
365}
366
367struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
368{
369 struct clk *clk;
370
371 clk = clk_get(dev, name);
372 if (IS_ERR(clk))
373 printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name);
374
375 return clk;
376}
377
378static int s3c_cpufreq_init(struct cpufreq_policy *policy)
379{
380 printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy);
381
382 if (policy->cpu != 0)
383 return -EINVAL;
384
385 policy->cur = s3c_cpufreq_get(0);
386 policy->min = policy->cpuinfo.min_freq = 0;
387 policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000;
388 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
389
390 /* feed the latency information from the cpu driver */
391 policy->cpuinfo.transition_latency = cpu_cur.info->latency;
392
393 if (ftab)
394 cpufreq_frequency_table_cpuinfo(policy, ftab);
395
396 return 0;
397}
398
399static __init int s3c_cpufreq_initclks(void)
400{
401 _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
402 _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
403 clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
404 clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
405 clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
406 clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
407
408 if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
409 IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
410 printk(KERN_ERR "%s: could not get clock(s)\n", __func__);
411 return -ENOENT;
412 }
413
414 printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__,
415 clk_get_rate(clk_fclk) / 1000,
416 clk_get_rate(clk_hclk) / 1000,
417 clk_get_rate(clk_pclk) / 1000,
418 clk_get_rate(clk_arm) / 1000);
419
420 return 0;
421}
422
423static int s3c_cpufreq_verify(struct cpufreq_policy *policy)
424{
425 if (policy->cpu != 0)
426 return -EINVAL;
427
428 return 0;
429}
430
431#ifdef CONFIG_PM
432static struct cpufreq_frequency_table suspend_pll;
433static unsigned int suspend_freq;
434
435static int s3c_cpufreq_suspend(struct cpufreq_policy *policy)
436{
437 suspend_pll.frequency = clk_get_rate(_clk_mpll);
438 suspend_pll.index = __raw_readl(S3C2410_MPLLCON);
439 suspend_freq = s3c_cpufreq_get(0) * 1000;
440
441 return 0;
442}
443
444static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
445{
446 int ret;
447
448 s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
449
450 last_target = ~0; /* invalidate last_target setting */
451
452 /* first, find out what speed we resumed at. */
453 s3c_cpufreq_resume_clocks();
454
455 /* whilst we will be called later on, we try and re-set the
456 * cpu frequencies as soon as possible so that we do not end
457 * up resuming devices and then immediately having to re-set
458 * a number of settings once these devices have restarted.
459 *
460 * as a note, it is expected devices are not used until they
461 * have been un-suspended and at that time they should have
462 * used the updated clock settings.
463 */
464
465 ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
466 if (ret) {
467 printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__);
468 return ret;
469 }
470
471 return 0;
472}
473#else
474#define s3c_cpufreq_resume NULL
475#define s3c_cpufreq_suspend NULL
476#endif
477
478static struct cpufreq_driver s3c24xx_driver = {
479 .flags = CPUFREQ_STICKY,
480 .verify = s3c_cpufreq_verify,
481 .target = s3c_cpufreq_target,
482 .get = s3c_cpufreq_get,
483 .init = s3c_cpufreq_init,
484 .suspend = s3c_cpufreq_suspend,
485 .resume = s3c_cpufreq_resume,
486 .name = "s3c24xx",
487};
488
489
490int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info)
491{
492 if (!info || !info->name) {
493 printk(KERN_ERR "%s: failed to pass valid information\n",
494 __func__);
495 return -EINVAL;
496 }
497
498 printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n",
499 info->name);
500
501 /* check our driver info has valid data */
502
503 BUG_ON(info->set_refresh == NULL);
504 BUG_ON(info->set_divs == NULL);
505 BUG_ON(info->calc_divs == NULL);
506
507 /* info->set_fvco is optional, depending on whether there
508 * is a need to set the clock code. */
509
510 cpu_cur.info = info;
511
512 /* Note, driver registering should probably update locktime */
513
514 return 0;
515}
516
517int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
518{
519 struct s3c_cpufreq_board *ours;
520
521 if (!board) {
522 printk(KERN_INFO "%s: no board data\n", __func__);
523 return -EINVAL;
524 }
525
526 /* Copy the board information so that each board can make this
527 * initdata. */
528
529 ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL);
530 if (ours == NULL) {
531 printk(KERN_ERR "%s: no memory\n", __func__);
532 return -ENOMEM;
533 }
534
535 *ours = *board;
536 cpu_cur.board = ours;
537
538 return 0;
539}
540
541int __init s3c_cpufreq_auto_io(void)
542{
543 int ret;
544
545 if (!cpu_cur.info->get_iotiming) {
546 printk(KERN_ERR "%s: get_iotiming undefined\n", __func__);
547 return -ENOENT;
548 }
549
550 printk(KERN_INFO "%s: working out IO settings\n", __func__);
551
552 ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
553 if (ret)
554 printk(KERN_ERR "%s: failed to get timings\n", __func__);
555
556 return ret;
557}
558
559/* if one or is zero, then return the other, otherwise return the min */
560#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
561
562/**
563 * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
564 * @dst: The destination structure
565 * @a: One argument.
566 * @b: The other argument.
567 *
568 * Create a minimum of each frequency entry in the 'struct s3c_freq',
569 * unless the entry is zero when it is ignored and the non-zero argument
570 * used.
571 */
572static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
573 struct s3c_freq *a, struct s3c_freq *b)
574{
575 dst->fclk = do_min(a->fclk, b->fclk);
576 dst->hclk = do_min(a->hclk, b->hclk);
577 dst->pclk = do_min(a->pclk, b->pclk);
578 dst->armclk = do_min(a->armclk, b->armclk);
579}
580
581static inline u32 calc_locktime(u32 freq, u32 time_us)
582{
583 u32 result;
584
585 result = freq * time_us;
586 result = DIV_ROUND_UP(result, 1000 * 1000);
587
588 return result;
589}
590
591static void s3c_cpufreq_update_loctkime(void)
592{
593 unsigned int bits = cpu_cur.info->locktime_bits;
594 u32 rate = (u32)clk_get_rate(_clk_xtal);
595 u32 val;
596
597 if (bits == 0) {
598 WARN_ON(1);
599 return;
600 }
601
602 val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
603 val |= calc_locktime(rate, cpu_cur.info->locktime_m);
604
605 printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val);
606 __raw_writel(val, S3C2410_LOCKTIME);
607}
608
609static int s3c_cpufreq_build_freq(void)
610{
611 int size, ret;
612
613 if (!cpu_cur.info->calc_freqtable)
614 return -EINVAL;
615
616 kfree(ftab);
617 ftab = NULL;
618
619 size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
620 size++;
621
622 ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL);
623 if (!ftab) {
624 printk(KERN_ERR "%s: no memory for tables\n", __func__);
625 return -ENOMEM;
626 }
627
628 ftab_size = size;
629
630 ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
631 s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
632
633 return 0;
634}
635
636static int __init s3c_cpufreq_initcall(void)
637{
638 int ret = 0;
639
640 if (cpu_cur.info && cpu_cur.board) {
641 ret = s3c_cpufreq_initclks();
642 if (ret)
643 goto out;
644
645 /* get current settings */
646 s3c_cpufreq_getcur(&cpu_cur);
647 s3c_cpufreq_show("cur", &cpu_cur);
648
649 if (cpu_cur.board->auto_io) {
650 ret = s3c_cpufreq_auto_io();
651 if (ret) {
652 printk(KERN_ERR "%s: failed to get io timing\n",
653 __func__);
654 goto out;
655 }
656 }
657
658 if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
659 printk(KERN_ERR "%s: no IO support registered\n",
660 __func__);
661 ret = -EINVAL;
662 goto out;
663 }
664
665 if (!cpu_cur.info->need_pll)
666 cpu_cur.lock_pll = 1;
667
668 s3c_cpufreq_update_loctkime();
669
670 s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
671 &cpu_cur.info->max);
672
673 if (cpu_cur.info->calc_freqtable)
674 s3c_cpufreq_build_freq();
675
676 ret = cpufreq_register_driver(&s3c24xx_driver);
677 }
678
679 out:
680 return ret;
681}
682
683late_initcall(s3c_cpufreq_initcall);
684
685/**
686 * s3c_plltab_register - register CPU PLL table.
687 * @plls: The list of PLL entries.
688 * @plls_no: The size of the PLL entries @plls.
689 *
690 * Register the given set of PLLs with the system.
691 */
692int __init s3c_plltab_register(struct cpufreq_frequency_table *plls,
693 unsigned int plls_no)
694{
695 struct cpufreq_frequency_table *vals;
696 unsigned int size;
697
698 size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1);
699
700 vals = kmalloc(size, GFP_KERNEL);
701 if (vals) {
702 memcpy(vals, plls, size);
703 pll_reg = vals;
704
705 /* write a terminating entry, we don't store it in the
706 * table that is stored in the kernel */
707 vals += plls_no;
708 vals->frequency = CPUFREQ_TABLE_END;
709
710 printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no);
711 } else
712 printk(KERN_ERR "cpufreq: no memory for PLL tables\n");
713
714 return vals ? 0 : -ENOMEM;
715}
diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
new file mode 100644
index 000000000000..aab64909e9a3
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/dma.c
@@ -0,0 +1,1468 @@
1/*
2 * Copyright 2003-2006 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
4 *
5 * S3C2410 DMA core
6 *
7 * http://armlinux.simtec.co.uk/
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14
15#ifdef CONFIG_S3C2410_DMA_DEBUG
16#define DEBUG
17#endif
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/sched.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/syscore_ops.h>
25#include <linux/slab.h>
26#include <linux/errno.h>
27#include <linux/io.h>
28
29#include <asm/irq.h>
30#include <mach/hardware.h>
31#include <mach/dma.h>
32#include <mach/map.h>
33
34#include <plat/dma-s3c24xx.h>
35#include <plat/regs-dma.h>
36
37/* io map for dma */
38static void __iomem *dma_base;
39static struct kmem_cache *dma_kmem;
40
41static int dma_channels;
42
43static struct s3c24xx_dma_selection dma_sel;
44
45
46/* debugging functions */
47
48#define BUF_MAGIC (0xcafebabe)
49
50#define dmawarn(fmt...) printk(KERN_DEBUG fmt)
51
52#define dma_regaddr(chan, reg) ((chan)->regs + (reg))
53
54#if 1
55#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
56#else
57static inline void
58dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
59{
60 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
61 writel(val, dma_regaddr(chan, reg));
62}
63#endif
64
65#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
66
67/* captured register state for debug */
68
69struct s3c2410_dma_regstate {
70 unsigned long dcsrc;
71 unsigned long disrc;
72 unsigned long dstat;
73 unsigned long dcon;
74 unsigned long dmsktrig;
75};
76
77#ifdef CONFIG_S3C2410_DMA_DEBUG
78
79/* dmadbg_showregs
80 *
81 * simple debug routine to print the current state of the dma registers
82*/
83
84static void
85dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
86{
87 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
88 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
89 regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
90 regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
91 regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
92}
93
94static void
95dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
96 struct s3c2410_dma_regstate *regs)
97{
98 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
99 chan->number, fname, line,
100 regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
101 regs->dcon);
102}
103
104static void
105dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
106{
107 struct s3c2410_dma_regstate state;
108
109 dmadbg_capture(chan, &state);
110
111 printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
112 chan->number, fname, line, chan->load_state,
113 chan->curr, chan->next, chan->end);
114
115 dmadbg_dumpregs(fname, line, chan, &state);
116}
117
118static void
119dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
120{
121 struct s3c2410_dma_regstate state;
122
123 dmadbg_capture(chan, &state);
124 dmadbg_dumpregs(fname, line, chan, &state);
125}
126
127#define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
128#define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
129#else
130#define dbg_showregs(chan) do { } while(0)
131#define dbg_showchan(chan) do { } while(0)
132#endif /* CONFIG_S3C2410_DMA_DEBUG */
133
134/* s3c2410_dma_stats_timeout
135 *
136 * Update DMA stats from timeout info
137*/
138
139static void
140s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
141{
142 if (stats == NULL)
143 return;
144
145 if (val > stats->timeout_longest)
146 stats->timeout_longest = val;
147 if (val < stats->timeout_shortest)
148 stats->timeout_shortest = val;
149
150 stats->timeout_avg += val;
151}
152
153/* s3c2410_dma_waitforload
154 *
155 * wait for the DMA engine to load a buffer, and update the state accordingly
156*/
157
158static int
159s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
160{
161 int timeout = chan->load_timeout;
162 int took;
163
164 if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
165 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
166 return 0;
167 }
168
169 if (chan->stats != NULL)
170 chan->stats->loads++;
171
172 while (--timeout > 0) {
173 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
174 took = chan->load_timeout - timeout;
175
176 s3c2410_dma_stats_timeout(chan->stats, took);
177
178 switch (chan->load_state) {
179 case S3C2410_DMALOAD_1LOADED:
180 chan->load_state = S3C2410_DMALOAD_1RUNNING;
181 break;
182
183 default:
184 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
185 }
186
187 return 1;
188 }
189 }
190
191 if (chan->stats != NULL) {
192 chan->stats->timeout_failed++;
193 }
194
195 return 0;
196}
197
198/* s3c2410_dma_loadbuffer
199 *
200 * load a buffer, and update the channel state
201*/
202
203static inline int
204s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
205 struct s3c2410_dma_buf *buf)
206{
207 unsigned long reload;
208
209 if (buf == NULL) {
210 dmawarn("buffer is NULL\n");
211 return -EINVAL;
212 }
213
214 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
215 buf, (unsigned long)buf->data, buf->size);
216
217 /* check the state of the channel before we do anything */
218
219 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
220 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
221 }
222
223 if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
224 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
225 }
226
227 /* it would seem sensible if we are the last buffer to not bother
228 * with the auto-reload bit, so that the DMA engine will not try
229 * and load another transfer after this one has finished...
230 */
231 if (chan->load_state == S3C2410_DMALOAD_NONE) {
232 pr_debug("load_state is none, checking for noreload (next=%p)\n",
233 buf->next);
234 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
235 } else {
236 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
237 reload = S3C2410_DCON_AUTORELOAD;
238 }
239
240 if ((buf->data & 0xf0000000) != 0x30000000) {
241 dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
242 }
243
244 writel(buf->data, chan->addr_reg);
245
246 dma_wrreg(chan, S3C2410_DMA_DCON,
247 chan->dcon | reload | (buf->size/chan->xfer_unit));
248
249 chan->next = buf->next;
250
251 /* update the state of the channel */
252
253 switch (chan->load_state) {
254 case S3C2410_DMALOAD_NONE:
255 chan->load_state = S3C2410_DMALOAD_1LOADED;
256 break;
257
258 case S3C2410_DMALOAD_1RUNNING:
259 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
260 break;
261
262 default:
263 dmawarn("dmaload: unknown state %d in loadbuffer\n",
264 chan->load_state);
265 break;
266 }
267
268 return 0;
269}
270
271/* s3c2410_dma_call_op
272 *
273 * small routine to call the op routine with the given op if it has been
274 * registered
275*/
276
277static void
278s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
279{
280 if (chan->op_fn != NULL) {
281 (chan->op_fn)(chan, op);
282 }
283}
284
285/* s3c2410_dma_buffdone
286 *
287 * small wrapper to check if callback routine needs to be called, and
288 * if so, call it
289*/
290
291static inline void
292s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
293 enum s3c2410_dma_buffresult result)
294{
295#if 0
296 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
297 chan->callback_fn, buf, buf->id, buf->size, result);
298#endif
299
300 if (chan->callback_fn != NULL) {
301 (chan->callback_fn)(chan, buf->id, buf->size, result);
302 }
303}
304
305/* s3c2410_dma_start
306 *
307 * start a dma channel going
308*/
309
310static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
311{
312 unsigned long tmp;
313 unsigned long flags;
314
315 pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
316
317 local_irq_save(flags);
318
319 if (chan->state == S3C2410_DMA_RUNNING) {
320 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
321 local_irq_restore(flags);
322 return 0;
323 }
324
325 chan->state = S3C2410_DMA_RUNNING;
326
327 /* check whether there is anything to load, and if not, see
328 * if we can find anything to load
329 */
330
331 if (chan->load_state == S3C2410_DMALOAD_NONE) {
332 if (chan->next == NULL) {
333 printk(KERN_ERR "dma%d: channel has nothing loaded\n",
334 chan->number);
335 chan->state = S3C2410_DMA_IDLE;
336 local_irq_restore(flags);
337 return -EINVAL;
338 }
339
340 s3c2410_dma_loadbuffer(chan, chan->next);
341 }
342
343 dbg_showchan(chan);
344
345 /* enable the channel */
346
347 if (!chan->irq_enabled) {
348 enable_irq(chan->irq);
349 chan->irq_enabled = 1;
350 }
351
352 /* start the channel going */
353
354 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
355 tmp &= ~S3C2410_DMASKTRIG_STOP;
356 tmp |= S3C2410_DMASKTRIG_ON;
357 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
358
359 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
360
361#if 0
362 /* the dma buffer loads should take care of clearing the AUTO
363 * reloading feature */
364 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
365 tmp &= ~S3C2410_DCON_NORELOAD;
366 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
367#endif
368
369 s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
370
371 dbg_showchan(chan);
372
373 /* if we've only loaded one buffer onto the channel, then chec
374 * to see if we have another, and if so, try and load it so when
375 * the first buffer is finished, the new one will be loaded onto
376 * the channel */
377
378 if (chan->next != NULL) {
379 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
380
381 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
382 pr_debug("%s: buff not yet loaded, no more todo\n",
383 __func__);
384 } else {
385 chan->load_state = S3C2410_DMALOAD_1RUNNING;
386 s3c2410_dma_loadbuffer(chan, chan->next);
387 }
388
389 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
390 s3c2410_dma_loadbuffer(chan, chan->next);
391 }
392 }
393
394
395 local_irq_restore(flags);
396
397 return 0;
398}
399
400/* s3c2410_dma_canload
401 *
402 * work out if we can queue another buffer into the DMA engine
403*/
404
405static int
406s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
407{
408 if (chan->load_state == S3C2410_DMALOAD_NONE ||
409 chan->load_state == S3C2410_DMALOAD_1RUNNING)
410 return 1;
411
412 return 0;
413}
414
415/* s3c2410_dma_enqueue
416 *
417 * queue an given buffer for dma transfer.
418 *
419 * id the device driver's id information for this buffer
420 * data the physical address of the buffer data
421 * size the size of the buffer in bytes
422 *
423 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
424 * is checked, and if set, the channel is started. If this flag isn't set,
425 * then an error will be returned.
426 *
427 * It is possible to queue more than one DMA buffer onto a channel at
428 * once, and the code will deal with the re-loading of the next buffer
429 * when necessary.
430*/
431
432int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
433 dma_addr_t data, int size)
434{
435 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
436 struct s3c2410_dma_buf *buf;
437 unsigned long flags;
438
439 if (chan == NULL)
440 return -EINVAL;
441
442 pr_debug("%s: id=%p, data=%08x, size=%d\n",
443 __func__, id, (unsigned int)data, size);
444
445 buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
446 if (buf == NULL) {
447 pr_debug("%s: out of memory (%ld alloc)\n",
448 __func__, (long)sizeof(*buf));
449 return -ENOMEM;
450 }
451
452 //pr_debug("%s: new buffer %p\n", __func__, buf);
453 //dbg_showchan(chan);
454
455 buf->next = NULL;
456 buf->data = buf->ptr = data;
457 buf->size = size;
458 buf->id = id;
459 buf->magic = BUF_MAGIC;
460
461 local_irq_save(flags);
462
463 if (chan->curr == NULL) {
464 /* we've got nothing loaded... */
465 pr_debug("%s: buffer %p queued onto empty channel\n",
466 __func__, buf);
467
468 chan->curr = buf;
469 chan->end = buf;
470 chan->next = NULL;
471 } else {
472 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
473 chan->number, __func__, buf);
474
475 if (chan->end == NULL) {
476 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
477 chan->number, __func__, chan);
478 } else {
479 chan->end->next = buf;
480 chan->end = buf;
481 }
482 }
483
484 /* if necessary, update the next buffer field */
485 if (chan->next == NULL)
486 chan->next = buf;
487
488 /* check to see if we can load a buffer */
489 if (chan->state == S3C2410_DMA_RUNNING) {
490 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
491 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
492 printk(KERN_ERR "dma%d: loadbuffer:"
493 "timeout loading buffer\n",
494 chan->number);
495 dbg_showchan(chan);
496 local_irq_restore(flags);
497 return -EINVAL;
498 }
499 }
500
501 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
502 s3c2410_dma_loadbuffer(chan, chan->next);
503 }
504 } else if (chan->state == S3C2410_DMA_IDLE) {
505 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
506 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
507 S3C2410_DMAOP_START);
508 }
509 }
510
511 local_irq_restore(flags);
512 return 0;
513}
514
515EXPORT_SYMBOL(s3c2410_dma_enqueue);
516
517static inline void
518s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
519{
520 int magicok = (buf->magic == BUF_MAGIC);
521
522 buf->magic = -1;
523
524 if (magicok) {
525 kmem_cache_free(dma_kmem, buf);
526 } else {
527 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
528 }
529}
530
531/* s3c2410_dma_lastxfer
532 *
533 * called when the system is out of buffers, to ensure that the channel
534 * is prepared for shutdown.
535*/
536
537static inline void
538s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
539{
540#if 0
541 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
542 chan->number, chan->load_state);
543#endif
544
545 switch (chan->load_state) {
546 case S3C2410_DMALOAD_NONE:
547 break;
548
549 case S3C2410_DMALOAD_1LOADED:
550 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
551 /* flag error? */
552 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
553 chan->number, __func__);
554 return;
555 }
556 break;
557
558 case S3C2410_DMALOAD_1LOADED_1RUNNING:
559 /* I believe in this case we do not have anything to do
560 * until the next buffer comes along, and we turn off the
561 * reload */
562 return;
563
564 default:
565 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
566 chan->number, chan->load_state);
567 return;
568
569 }
570
571 /* hopefully this'll shut the damned thing up after the transfer... */
572 dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
573}
574
575
576#define dmadbg2(x...)
577
578static irqreturn_t
579s3c2410_dma_irq(int irq, void *devpw)
580{
581 struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
582 struct s3c2410_dma_buf *buf;
583
584 buf = chan->curr;
585
586 dbg_showchan(chan);
587
588 /* modify the channel state */
589
590 switch (chan->load_state) {
591 case S3C2410_DMALOAD_1RUNNING:
592 /* TODO - if we are running only one buffer, we probably
593 * want to reload here, and then worry about the buffer
594 * callback */
595
596 chan->load_state = S3C2410_DMALOAD_NONE;
597 break;
598
599 case S3C2410_DMALOAD_1LOADED:
600 /* iirc, we should go back to NONE loaded here, we
601 * had a buffer, and it was never verified as being
602 * loaded.
603 */
604
605 chan->load_state = S3C2410_DMALOAD_NONE;
606 break;
607
608 case S3C2410_DMALOAD_1LOADED_1RUNNING:
609 /* we'll worry about checking to see if another buffer is
610 * ready after we've called back the owner. This should
611 * ensure we do not wait around too long for the DMA
612 * engine to start the next transfer
613 */
614
615 chan->load_state = S3C2410_DMALOAD_1LOADED;
616 break;
617
618 case S3C2410_DMALOAD_NONE:
619 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
620 chan->number);
621 break;
622
623 default:
624 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
625 chan->number, chan->load_state);
626 break;
627 }
628
629 if (buf != NULL) {
630 /* update the chain to make sure that if we load any more
631 * buffers when we call the callback function, things should
632 * work properly */
633
634 chan->curr = buf->next;
635 buf->next = NULL;
636
637 if (buf->magic != BUF_MAGIC) {
638 printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
639 chan->number, __func__, buf);
640 return IRQ_HANDLED;
641 }
642
643 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
644
645 /* free resouces */
646 s3c2410_dma_freebuf(buf);
647 } else {
648 }
649
650 /* only reload if the channel is still running... our buffer done
651 * routine may have altered the state by requesting the dma channel
652 * to stop or shutdown... */
653
654 /* todo: check that when the channel is shut-down from inside this
655 * function, we cope with unsetting reload, etc */
656
657 if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
658 unsigned long flags;
659
660 switch (chan->load_state) {
661 case S3C2410_DMALOAD_1RUNNING:
662 /* don't need to do anything for this state */
663 break;
664
665 case S3C2410_DMALOAD_NONE:
666 /* can load buffer immediately */
667 break;
668
669 case S3C2410_DMALOAD_1LOADED:
670 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
671 /* flag error? */
672 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
673 chan->number, __func__);
674 return IRQ_HANDLED;
675 }
676
677 break;
678
679 case S3C2410_DMALOAD_1LOADED_1RUNNING:
680 goto no_load;
681
682 default:
683 printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
684 chan->number, chan->load_state);
685 return IRQ_HANDLED;
686 }
687
688 local_irq_save(flags);
689 s3c2410_dma_loadbuffer(chan, chan->next);
690 local_irq_restore(flags);
691 } else {
692 s3c2410_dma_lastxfer(chan);
693
694 /* see if we can stop this channel.. */
695 if (chan->load_state == S3C2410_DMALOAD_NONE) {
696 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
697 chan->number, jiffies);
698 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
699 S3C2410_DMAOP_STOP);
700 }
701 }
702
703 no_load:
704 return IRQ_HANDLED;
705}
706
707static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
708
709/* s3c2410_request_dma
710 *
711 * get control of an dma channel
712*/
713
714int s3c2410_dma_request(enum dma_ch channel,
715 struct s3c2410_dma_client *client,
716 void *dev)
717{
718 struct s3c2410_dma_chan *chan;
719 unsigned long flags;
720 int err;
721
722 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
723 channel, client->name, dev);
724
725 local_irq_save(flags);
726
727 chan = s3c2410_dma_map_channel(channel);
728 if (chan == NULL) {
729 local_irq_restore(flags);
730 return -EBUSY;
731 }
732
733 dbg_showchan(chan);
734
735 chan->client = client;
736 chan->in_use = 1;
737
738 if (!chan->irq_claimed) {
739 pr_debug("dma%d: %s : requesting irq %d\n",
740 channel, __func__, chan->irq);
741
742 chan->irq_claimed = 1;
743 local_irq_restore(flags);
744
745 err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
746 client->name, (void *)chan);
747
748 local_irq_save(flags);
749
750 if (err) {
751 chan->in_use = 0;
752 chan->irq_claimed = 0;
753 local_irq_restore(flags);
754
755 printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
756 client->name, chan->irq, chan->number);
757 return err;
758 }
759
760 chan->irq_enabled = 1;
761 }
762
763 local_irq_restore(flags);
764
765 /* need to setup */
766
767 pr_debug("%s: channel initialised, %p\n", __func__, chan);
768
769 return chan->number | DMACH_LOW_LEVEL;
770}
771
772EXPORT_SYMBOL(s3c2410_dma_request);
773
774/* s3c2410_dma_free
775 *
776 * release the given channel back to the system, will stop and flush
777 * any outstanding transfers, and ensure the channel is ready for the
778 * next claimant.
779 *
780 * Note, although a warning is currently printed if the freeing client
781 * info is not the same as the registrant's client info, the free is still
782 * allowed to go through.
783*/
784
785int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client)
786{
787 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
788 unsigned long flags;
789
790 if (chan == NULL)
791 return -EINVAL;
792
793 local_irq_save(flags);
794
795 if (chan->client != client) {
796 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
797 channel, chan->client, client);
798 }
799
800 /* sort out stopping and freeing the channel */
801
802 if (chan->state != S3C2410_DMA_IDLE) {
803 pr_debug("%s: need to stop dma channel %p\n",
804 __func__, chan);
805
806 /* possibly flush the channel */
807 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
808 }
809
810 chan->client = NULL;
811 chan->in_use = 0;
812
813 if (chan->irq_claimed)
814 free_irq(chan->irq, (void *)chan);
815
816 chan->irq_claimed = 0;
817
818 if (!(channel & DMACH_LOW_LEVEL))
819 s3c_dma_chan_map[channel] = NULL;
820
821 local_irq_restore(flags);
822
823 return 0;
824}
825
826EXPORT_SYMBOL(s3c2410_dma_free);
827
828static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
829{
830 unsigned long flags;
831 unsigned long tmp;
832
833 pr_debug("%s:\n", __func__);
834
835 dbg_showchan(chan);
836
837 local_irq_save(flags);
838
839 s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
840
841 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
842 tmp |= S3C2410_DMASKTRIG_STOP;
843 //tmp &= ~S3C2410_DMASKTRIG_ON;
844 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
845
846#if 0
847 /* should also clear interrupts, according to WinCE BSP */
848 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
849 tmp |= S3C2410_DCON_NORELOAD;
850 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
851#endif
852
853 /* should stop do this, or should we wait for flush? */
854 chan->state = S3C2410_DMA_IDLE;
855 chan->load_state = S3C2410_DMALOAD_NONE;
856
857 local_irq_restore(flags);
858
859 return 0;
860}
861
862static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
863{
864 unsigned long tmp;
865 unsigned int timeout = 0x10000;
866
867 while (timeout-- > 0) {
868 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
869
870 if (!(tmp & S3C2410_DMASKTRIG_ON))
871 return;
872 }
873
874 pr_debug("dma%d: failed to stop?\n", chan->number);
875}
876
877
878/* s3c2410_dma_flush
879 *
880 * stop the channel, and remove all current and pending transfers
881*/
882
883static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
884{
885 struct s3c2410_dma_buf *buf, *next;
886 unsigned long flags;
887
888 pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number);
889
890 dbg_showchan(chan);
891
892 local_irq_save(flags);
893
894 if (chan->state != S3C2410_DMA_IDLE) {
895 pr_debug("%s: stopping channel...\n", __func__ );
896 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
897 }
898
899 buf = chan->curr;
900 if (buf == NULL)
901 buf = chan->next;
902
903 chan->curr = chan->next = chan->end = NULL;
904
905 if (buf != NULL) {
906 for ( ; buf != NULL; buf = next) {
907 next = buf->next;
908
909 pr_debug("%s: free buffer %p, next %p\n",
910 __func__, buf, buf->next);
911
912 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
913 s3c2410_dma_freebuf(buf);
914 }
915 }
916
917 dbg_showregs(chan);
918
919 s3c2410_dma_waitforstop(chan);
920
921#if 0
922 /* should also clear interrupts, according to WinCE BSP */
923 {
924 unsigned long tmp;
925
926 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
927 tmp |= S3C2410_DCON_NORELOAD;
928 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
929 }
930#endif
931
932 dbg_showregs(chan);
933
934 local_irq_restore(flags);
935
936 return 0;
937}
938
939static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
940{
941 unsigned long flags;
942
943 local_irq_save(flags);
944
945 dbg_showchan(chan);
946
947 /* if we've only loaded one buffer onto the channel, then chec
948 * to see if we have another, and if so, try and load it so when
949 * the first buffer is finished, the new one will be loaded onto
950 * the channel */
951
952 if (chan->next != NULL) {
953 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
954
955 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
956 pr_debug("%s: buff not yet loaded, no more todo\n",
957 __func__);
958 } else {
959 chan->load_state = S3C2410_DMALOAD_1RUNNING;
960 s3c2410_dma_loadbuffer(chan, chan->next);
961 }
962
963 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
964 s3c2410_dma_loadbuffer(chan, chan->next);
965 }
966 }
967
968
969 local_irq_restore(flags);
970
971 return 0;
972
973}
974
975int
976s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op)
977{
978 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
979
980 if (chan == NULL)
981 return -EINVAL;
982
983 switch (op) {
984 case S3C2410_DMAOP_START:
985 return s3c2410_dma_start(chan);
986
987 case S3C2410_DMAOP_STOP:
988 return s3c2410_dma_dostop(chan);
989
990 case S3C2410_DMAOP_PAUSE:
991 case S3C2410_DMAOP_RESUME:
992 return -ENOENT;
993
994 case S3C2410_DMAOP_FLUSH:
995 return s3c2410_dma_flush(chan);
996
997 case S3C2410_DMAOP_STARTED:
998 return s3c2410_dma_started(chan);
999
1000 case S3C2410_DMAOP_TIMEOUT:
1001 return 0;
1002
1003 }
1004
1005 return -ENOENT; /* unknown, don't bother */
1006}
1007
1008EXPORT_SYMBOL(s3c2410_dma_ctrl);
1009
1010/* DMA configuration for each channel
1011 *
1012 * DISRCC -> source of the DMA (AHB,APB)
1013 * DISRC -> source address of the DMA
1014 * DIDSTC -> destination of the DMA (AHB,APD)
1015 * DIDST -> destination address of the DMA
1016*/
1017
1018/* s3c2410_dma_config
1019 *
1020 * xfersize: size of unit in bytes (1,2,4)
1021*/
1022
1023int s3c2410_dma_config(enum dma_ch channel,
1024 int xferunit)
1025{
1026 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1027 unsigned int dcon;
1028
1029 pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__, channel, xferunit);
1030
1031 if (chan == NULL)
1032 return -EINVAL;
1033
1034 dcon = chan->dcon & dma_sel.dcon_mask;
1035 pr_debug("%s: dcon is %08x\n", __func__, dcon);
1036
1037 switch (chan->req_ch) {
1038 case DMACH_I2S_IN:
1039 case DMACH_I2S_OUT:
1040 case DMACH_PCM_IN:
1041 case DMACH_PCM_OUT:
1042 case DMACH_MIC_IN:
1043 default:
1044 dcon |= S3C2410_DCON_HANDSHAKE;
1045 dcon |= S3C2410_DCON_SYNC_PCLK;
1046 break;
1047
1048 case DMACH_SDI:
1049 /* note, ensure if need HANDSHAKE or not */
1050 dcon |= S3C2410_DCON_SYNC_PCLK;
1051 break;
1052
1053 case DMACH_XD0:
1054 case DMACH_XD1:
1055 dcon |= S3C2410_DCON_HANDSHAKE;
1056 dcon |= S3C2410_DCON_SYNC_HCLK;
1057 break;
1058 }
1059
1060 switch (xferunit) {
1061 case 1:
1062 dcon |= S3C2410_DCON_BYTE;
1063 break;
1064
1065 case 2:
1066 dcon |= S3C2410_DCON_HALFWORD;
1067 break;
1068
1069 case 4:
1070 dcon |= S3C2410_DCON_WORD;
1071 break;
1072
1073 default:
1074 pr_debug("%s: bad transfer size %d\n", __func__, xferunit);
1075 return -EINVAL;
1076 }
1077
1078 dcon |= S3C2410_DCON_HWTRIG;
1079 dcon |= S3C2410_DCON_INTREQ;
1080
1081 pr_debug("%s: dcon now %08x\n", __func__, dcon);
1082
1083 chan->dcon = dcon;
1084 chan->xfer_unit = xferunit;
1085
1086 return 0;
1087}
1088
1089EXPORT_SYMBOL(s3c2410_dma_config);
1090
1091
1092/* s3c2410_dma_devconfig
1093 *
1094 * configure the dma source/destination hardware type and address
1095 *
1096 * source: DMA_FROM_DEVICE: source is hardware
1097 * DMA_TO_DEVICE: source is memory
1098 *
1099 * devaddr: physical address of the source
1100*/
1101
1102int s3c2410_dma_devconfig(enum dma_ch channel,
1103 enum dma_data_direction source,
1104 unsigned long devaddr)
1105{
1106 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1107 unsigned int hwcfg;
1108
1109 if (chan == NULL)
1110 return -EINVAL;
1111
1112 pr_debug("%s: source=%d, devaddr=%08lx\n",
1113 __func__, (int)source, devaddr);
1114
1115 chan->source = source;
1116 chan->dev_addr = devaddr;
1117
1118 switch (chan->req_ch) {
1119 case DMACH_XD0:
1120 case DMACH_XD1:
1121 hwcfg = 0; /* AHB */
1122 break;
1123
1124 default:
1125 hwcfg = S3C2410_DISRCC_APB;
1126 }
1127
1128 /* always assume our peripheral desintation is a fixed
1129 * address in memory. */
1130 hwcfg |= S3C2410_DISRCC_INC;
1131
1132 switch (source) {
1133 case DMA_FROM_DEVICE:
1134 /* source is hardware */
1135 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1136 __func__, devaddr, hwcfg);
1137 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1138 dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
1139 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1140
1141 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1142 break;
1143
1144 case DMA_TO_DEVICE:
1145 /* source is memory */
1146 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1147 __func__, devaddr, hwcfg);
1148 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1149 dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
1150 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1151
1152 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1153 break;
1154
1155 default:
1156 printk(KERN_ERR "dma%d: invalid source type (%d)\n",
1157 channel, source);
1158
1159 return -EINVAL;
1160 }
1161
1162 if (dma_sel.direction != NULL)
1163 (dma_sel.direction)(chan, chan->map, source);
1164
1165 return 0;
1166}
1167
1168EXPORT_SYMBOL(s3c2410_dma_devconfig);
1169
1170/* s3c2410_dma_getposition
1171 *
1172 * returns the current transfer points for the dma source and destination
1173*/
1174
1175int s3c2410_dma_getposition(enum dma_ch channel, dma_addr_t *src, dma_addr_t *dst)
1176{
1177 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1178
1179 if (chan == NULL)
1180 return -EINVAL;
1181
1182 if (src != NULL)
1183 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1184
1185 if (dst != NULL)
1186 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1187
1188 return 0;
1189}
1190
1191EXPORT_SYMBOL(s3c2410_dma_getposition);
1192
1193/* system core operations */
1194
1195#ifdef CONFIG_PM
1196
1197static void s3c2410_dma_suspend_chan(struct s3c2410_dma_chan *cp)
1198{
1199 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1200
1201 if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1202 /* the dma channel is still working, which is probably
1203 * a bad thing to do over suspend/resume. We stop the
1204 * channel and assume that the client is either going to
1205 * retry after resume, or that it is broken.
1206 */
1207
1208 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1209 cp->number);
1210
1211 s3c2410_dma_dostop(cp);
1212 }
1213}
1214
1215static int s3c2410_dma_suspend(void)
1216{
1217 struct s3c2410_dma_chan *cp = s3c2410_chans;
1218 int channel;
1219
1220 for (channel = 0; channel < dma_channels; cp++, channel++)
1221 s3c2410_dma_suspend_chan(cp);
1222
1223 return 0;
1224}
1225
1226static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp)
1227{
1228 unsigned int no = cp->number | DMACH_LOW_LEVEL;
1229
1230 /* restore channel's hardware configuration */
1231
1232 if (!cp->in_use)
1233 return;
1234
1235 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1236
1237 s3c2410_dma_config(no, cp->xfer_unit);
1238 s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
1239
1240 /* re-select the dma source for this channel */
1241
1242 if (cp->map != NULL)
1243 dma_sel.select(cp, cp->map);
1244}
1245
1246static void s3c2410_dma_resume(void)
1247{
1248 struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1;
1249 int channel;
1250
1251 for (channel = dma_channels - 1; channel >= 0; cp--, channel--)
1252 s3c2410_dma_resume_chan(cp);
1253}
1254
1255#else
1256#define s3c2410_dma_suspend NULL
1257#define s3c2410_dma_resume NULL
1258#endif /* CONFIG_PM */
1259
1260struct syscore_ops dma_syscore_ops = {
1261 .suspend = s3c2410_dma_suspend,
1262 .resume = s3c2410_dma_resume,
1263};
1264
1265/* kmem cache implementation */
1266
1267static void s3c2410_dma_cache_ctor(void *p)
1268{
1269 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1270}
1271
1272/* initialisation code */
1273
1274static int __init s3c24xx_dma_syscore_init(void)
1275{
1276 register_syscore_ops(&dma_syscore_ops);
1277
1278 return 0;
1279}
1280
1281late_initcall(s3c24xx_dma_syscore_init);
1282
1283int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1284 unsigned int stride)
1285{
1286 struct s3c2410_dma_chan *cp;
1287 int channel;
1288 int ret;
1289
1290 printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n");
1291
1292 dma_channels = channels;
1293
1294 dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
1295 if (dma_base == NULL) {
1296 printk(KERN_ERR "dma failed to remap register block\n");
1297 return -ENOMEM;
1298 }
1299
1300 dma_kmem = kmem_cache_create("dma_desc",
1301 sizeof(struct s3c2410_dma_buf), 0,
1302 SLAB_HWCACHE_ALIGN,
1303 s3c2410_dma_cache_ctor);
1304
1305 if (dma_kmem == NULL) {
1306 printk(KERN_ERR "dma failed to make kmem cache\n");
1307 ret = -ENOMEM;
1308 goto err;
1309 }
1310
1311 for (channel = 0; channel < channels; channel++) {
1312 cp = &s3c2410_chans[channel];
1313
1314 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1315
1316 /* dma channel irqs are in order.. */
1317 cp->number = channel;
1318 cp->irq = channel + irq;
1319 cp->regs = dma_base + (channel * stride);
1320
1321 /* point current stats somewhere */
1322 cp->stats = &cp->stats_store;
1323 cp->stats_store.timeout_shortest = LONG_MAX;
1324
1325 /* basic channel configuration */
1326
1327 cp->load_timeout = 1<<18;
1328
1329 printk("DMA channel %d at %p, irq %d\n",
1330 cp->number, cp->regs, cp->irq);
1331 }
1332
1333 return 0;
1334
1335 err:
1336 kmem_cache_destroy(dma_kmem);
1337 iounmap(dma_base);
1338 dma_base = NULL;
1339 return ret;
1340}
1341
1342int __init s3c2410_dma_init(void)
1343{
1344 return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
1345}
1346
1347static inline int is_channel_valid(unsigned int channel)
1348{
1349 return (channel & DMA_CH_VALID);
1350}
1351
1352static struct s3c24xx_dma_order *dma_order;
1353
1354
1355/* s3c2410_dma_map_channel()
1356 *
1357 * turn the virtual channel number into a real, and un-used hardware
1358 * channel.
1359 *
1360 * first, try the dma ordering given to us by either the relevant
1361 * dma code, or the board. Then just find the first usable free
1362 * channel
1363*/
1364
1365static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1366{
1367 struct s3c24xx_dma_order_ch *ord = NULL;
1368 struct s3c24xx_dma_map *ch_map;
1369 struct s3c2410_dma_chan *dmach;
1370 int ch;
1371
1372 if (dma_sel.map == NULL || channel > dma_sel.map_size)
1373 return NULL;
1374
1375 ch_map = dma_sel.map + channel;
1376
1377 /* first, try the board mapping */
1378
1379 if (dma_order) {
1380 ord = &dma_order->channels[channel];
1381
1382 for (ch = 0; ch < dma_channels; ch++) {
1383 int tmp;
1384 if (!is_channel_valid(ord->list[ch]))
1385 continue;
1386
1387 tmp = ord->list[ch] & ~DMA_CH_VALID;
1388 if (s3c2410_chans[tmp].in_use == 0) {
1389 ch = tmp;
1390 goto found;
1391 }
1392 }
1393
1394 if (ord->flags & DMA_CH_NEVER)
1395 return NULL;
1396 }
1397
1398 /* second, search the channel map for first free */
1399
1400 for (ch = 0; ch < dma_channels; ch++) {
1401 if (!is_channel_valid(ch_map->channels[ch]))
1402 continue;
1403
1404 if (s3c2410_chans[ch].in_use == 0) {
1405 printk("mapped channel %d to %d\n", channel, ch);
1406 break;
1407 }
1408 }
1409
1410 if (ch >= dma_channels)
1411 return NULL;
1412
1413 /* update our channel mapping */
1414
1415 found:
1416 dmach = &s3c2410_chans[ch];
1417 dmach->map = ch_map;
1418 dmach->req_ch = channel;
1419 s3c_dma_chan_map[channel] = dmach;
1420
1421 /* select the channel */
1422
1423 (dma_sel.select)(dmach, ch_map);
1424
1425 return dmach;
1426}
1427
1428static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1429{
1430 return 0;
1431}
1432
1433int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1434{
1435 struct s3c24xx_dma_map *nmap;
1436 size_t map_sz = sizeof(*nmap) * sel->map_size;
1437 int ptr;
1438
1439 nmap = kmemdup(sel->map, map_sz, GFP_KERNEL);
1440 if (nmap == NULL)
1441 return -ENOMEM;
1442
1443 memcpy(&dma_sel, sel, sizeof(*sel));
1444
1445 dma_sel.map = nmap;
1446
1447 for (ptr = 0; ptr < sel->map_size; ptr++)
1448 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1449
1450 return 0;
1451}
1452
1453int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
1454{
1455 struct s3c24xx_dma_order *nord = dma_order;
1456
1457 if (nord == NULL)
1458 nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
1459
1460 if (nord == NULL) {
1461 printk(KERN_ERR "no memory to store dma channel order\n");
1462 return -ENOMEM;
1463 }
1464
1465 dma_order = nord;
1466 memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
1467 return 0;
1468}
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
new file mode 100644
index 000000000000..48ccfcf715fa
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
@@ -0,0 +1,477 @@
1/*
2 * Copyright (c) 2006-2009 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/cpufreq.h>
17#include <linux/seq_file.h>
18#include <linux/io.h>
19#include <linux/slab.h>
20
21#include <mach/map.h>
22#include <mach/regs-mem.h>
23#include <mach/regs-clock.h>
24
25#include <plat/cpu-freq-core.h>
26
27#define print_ns(x) ((x) / 10), ((x) % 10)
28
29/**
30 * s3c2410_print_timing - print bank timing data for debug purposes
31 * @pfx: The prefix to put on the output
32 * @timings: The timing inforamtion to print.
33*/
34static void s3c2410_print_timing(const char *pfx,
35 struct s3c_iotimings *timings)
36{
37 struct s3c2410_iobank_timing *bt;
38 int bank;
39
40 for (bank = 0; bank < MAX_BANKS; bank++) {
41 bt = timings->bank[bank].io_2410;
42 if (!bt)
43 continue;
44
45 printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, "
46 "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank,
47 print_ns(bt->tacs),
48 print_ns(bt->tcos),
49 print_ns(bt->tacc),
50 print_ns(bt->tcoh),
51 print_ns(bt->tcah));
52 }
53}
54
55/**
56 * bank_reg - convert bank number to pointer to the control register.
57 * @bank: The IO bank number.
58 */
59static inline void __iomem *bank_reg(unsigned int bank)
60{
61 return S3C2410_BANKCON0 + (bank << 2);
62}
63
64/**
65 * bank_is_io - test whether bank is used for IO
66 * @bankcon: The bank control register.
67 *
68 * This is a simplistic test to see if any BANKCON[x] is not an IO
69 * bank. It currently does not take into account whether BWSCON has
70 * an illegal width-setting in it, or if the pin connected to nCS[x]
71 * is actually being handled as a chip-select.
72 */
73static inline int bank_is_io(unsigned long bankcon)
74{
75 return !(bankcon & S3C2410_BANKCON_SDRAM);
76}
77
78/**
79 * to_div - convert cycle time to divisor
80 * @cyc: The cycle time, in 10ths of nanoseconds.
81 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
82 *
83 * Convert the given cycle time into the divisor to use to obtain it from
84 * HCLK.
85*/
86static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns)
87{
88 if (cyc == 0)
89 return 0;
90
91 return DIV_ROUND_UP(cyc, hclk_tns);
92}
93
94/**
95 * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
96 * @cyc: The cycle time, in 10ths of nanoseconds.
97 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
98 * @v: Pointer to register to alter.
99 * @shift: The shift to get to the control bits.
100 *
101 * Calculate the divisor, and turn it into the correct control bits to
102 * set in the result, @v.
103 */
104static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns,
105 unsigned long *v, int shift)
106{
107 unsigned int div = to_div(cyc, hclk_tns);
108 unsigned long val;
109
110 s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n",
111 __func__, cyc, hclk_tns, shift, div);
112
113 switch (div) {
114 case 0:
115 val = 0;
116 break;
117 case 1:
118 val = 1;
119 break;
120 case 2:
121 val = 2;
122 break;
123 case 3:
124 case 4:
125 val = 3;
126 break;
127 default:
128 return -1;
129 }
130
131 *v |= val << shift;
132 return 0;
133}
134
135int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
136{
137 /* Currently no support for Tacp calculations. */
138 return 0;
139}
140
141/**
142 * calc_tacc - calculate divisor control for tacc.
143 * @cyc: The cycle time, in 10ths of nanoseconds.
144 * @nwait_en: IS nWAIT enabled for this bank.
145 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
146 * @v: Pointer to register to alter.
147 *
148 * Calculate the divisor control for tACC, taking into account whether
149 * the bank has nWAIT enabled. The result is used to modify the value
150 * pointed to by @v.
151*/
152static int calc_tacc(unsigned int cyc, int nwait_en,
153 unsigned long hclk_tns, unsigned long *v)
154{
155 unsigned int div = to_div(cyc, hclk_tns);
156 unsigned long val;
157
158 s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n",
159 __func__, cyc, nwait_en, hclk_tns, div);
160
161 /* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */
162 if (nwait_en && div < 4)
163 div = 4;
164
165 switch (div) {
166 case 0:
167 val = 0;
168 break;
169
170 case 1:
171 case 2:
172 case 3:
173 case 4:
174 val = div - 1;
175 break;
176
177 case 5:
178 case 6:
179 val = 4;
180 break;
181
182 case 7:
183 case 8:
184 val = 5;
185 break;
186
187 case 9:
188 case 10:
189 val = 6;
190 break;
191
192 case 11:
193 case 12:
194 case 13:
195 case 14:
196 val = 7;
197 break;
198
199 default:
200 return -1;
201 }
202
203 *v |= val << 8;
204 return 0;
205}
206
207/**
208 * s3c2410_calc_bank - calculate bank timing infromation
209 * @cfg: The configuration we need to calculate for.
210 * @bt: The bank timing information.
211 *
212 * Given the cycle timine for a bank @bt, calculate the new BANKCON
213 * setting for the @cfg timing. This updates the timing information
214 * ready for the cpu frequency change.
215 */
216static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg,
217 struct s3c2410_iobank_timing *bt)
218{
219 unsigned long hclk = cfg->freq.hclk_tns;
220 unsigned long res;
221 int ret;
222
223 res = bt->bankcon;
224 res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16);
225
226 /* tacp: 2,3,4,5 */
227 /* tcah: 0,1,2,4 */
228 /* tcoh: 0,1,2,4 */
229 /* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */
230 /* tcos: 0,1,2,4 */
231 /* tacs: 0,1,2,4 */
232
233 ret = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT);
234 ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT);
235 ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT);
236 ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT);
237
238 if (ret)
239 return -EINVAL;
240
241 ret |= calc_tacp(bt->tacp, hclk, &res);
242 ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res);
243
244 if (ret)
245 return -EINVAL;
246
247 bt->bankcon = res;
248 return 0;
249}
250
251static unsigned int tacc_tab[] = {
252 [0] = 1,
253 [1] = 2,
254 [2] = 3,
255 [3] = 4,
256 [4] = 6,
257 [5] = 9,
258 [6] = 10,
259 [7] = 14,
260};
261
262/**
263 * get_tacc - turn tACC value into cycle time
264 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
265 * @val: The bank timing register value, shifed down.
266 */
267static unsigned int get_tacc(unsigned long hclk_tns,
268 unsigned long val)
269{
270 val &= 7;
271 return hclk_tns * tacc_tab[val];
272}
273
274/**
275 * get_0124 - turn 0/1/2/4 divider into cycle time
276 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
277 * @val: The bank timing register value, shifed down.
278 */
279static unsigned int get_0124(unsigned long hclk_tns,
280 unsigned long val)
281{
282 val &= 3;
283 return hclk_tns * ((val == 3) ? 4 : val);
284}
285
286/**
287 * s3c2410_iotiming_getbank - turn BANKCON into cycle time information
288 * @cfg: The frequency configuration
289 * @bt: The bank timing to fill in (uses cached BANKCON)
290 *
291 * Given the BANKCON setting in @bt and the current frequency settings
292 * in @cfg, update the cycle timing information.
293 */
294void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
295 struct s3c2410_iobank_timing *bt)
296{
297 unsigned long bankcon = bt->bankcon;
298 unsigned long hclk = cfg->freq.hclk_tns;
299
300 bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
301 bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
302 bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
303 bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
304 bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
305}
306
307/**
308 * s3c2410_iotiming_debugfs - debugfs show io bank timing information
309 * @seq: The seq_file to write output to using seq_printf().
310 * @cfg: The current configuration.
311 * @iob: The IO bank information to decode.
312 */
313void s3c2410_iotiming_debugfs(struct seq_file *seq,
314 struct s3c_cpufreq_config *cfg,
315 union s3c_iobank *iob)
316{
317 struct s3c2410_iobank_timing *bt = iob->io_2410;
318 unsigned long bankcon = bt->bankcon;
319 unsigned long hclk = cfg->freq.hclk_tns;
320 unsigned int tacs;
321 unsigned int tcos;
322 unsigned int tacc;
323 unsigned int tcoh;
324 unsigned int tcah;
325
326 seq_printf(seq, "BANKCON=0x%08lx\n", bankcon);
327
328 tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
329 tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
330 tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
331 tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
332 tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
333
334 seq_printf(seq,
335 "\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
336 print_ns(bt->tacs),
337 print_ns(bt->tcos),
338 print_ns(bt->tacc),
339 print_ns(bt->tcoh),
340 print_ns(bt->tcah));
341
342 seq_printf(seq,
343 "\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
344 print_ns(tacs),
345 print_ns(tcos),
346 print_ns(tacc),
347 print_ns(tcoh),
348 print_ns(tcah));
349}
350
351/**
352 * s3c2410_iotiming_calc - Calculate bank timing for frequency change.
353 * @cfg: The frequency configuration
354 * @iot: The IO timing information to fill out.
355 *
356 * Calculate the new values for the banks in @iot based on the new
357 * frequency information in @cfg. This is then used by s3c2410_iotiming_set()
358 * to update the timing when necessary.
359 */
360int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
361 struct s3c_iotimings *iot)
362{
363 struct s3c2410_iobank_timing *bt;
364 unsigned long bankcon;
365 int bank;
366 int ret;
367
368 for (bank = 0; bank < MAX_BANKS; bank++) {
369 bankcon = __raw_readl(bank_reg(bank));
370 bt = iot->bank[bank].io_2410;
371
372 if (!bt)
373 continue;
374
375 bt->bankcon = bankcon;
376
377 ret = s3c2410_calc_bank(cfg, bt);
378 if (ret) {
379 printk(KERN_ERR "%s: cannot calculate bank %d io\n",
380 __func__, bank);
381 goto err;
382 }
383
384 s3c_freq_iodbg("%s: bank %d: con=%08lx\n",
385 __func__, bank, bt->bankcon);
386 }
387
388 return 0;
389 err:
390 return ret;
391}
392
393/**
394 * s3c2410_iotiming_set - set the IO timings from the given setup.
395 * @cfg: The frequency configuration
396 * @iot: The IO timing information to use.
397 *
398 * Set all the currently used IO bank timing information generated
399 * by s3c2410_iotiming_calc() once the core has validated that all
400 * the new values are within permitted bounds.
401 */
402void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
403 struct s3c_iotimings *iot)
404{
405 struct s3c2410_iobank_timing *bt;
406 int bank;
407
408 /* set the io timings from the specifier */
409
410 for (bank = 0; bank < MAX_BANKS; bank++) {
411 bt = iot->bank[bank].io_2410;
412 if (!bt)
413 continue;
414
415 __raw_writel(bt->bankcon, bank_reg(bank));
416 }
417}
418
419/**
420 * s3c2410_iotiming_get - Get the timing information from current registers.
421 * @cfg: The frequency configuration
422 * @timings: The IO timing information to fill out.
423 *
424 * Calculate the @timings timing information from the current frequency
425 * information in @cfg, and the new frequency configur
426 * through all the IO banks, reading the state and then updating @iot
427 * as necessary.
428 *
429 * This is used at the moment on initialisation to get the current
430 * configuration so that boards do not have to carry their own setup
431 * if the timings are correct on initialisation.
432 */
433
434int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
435 struct s3c_iotimings *timings)
436{
437 struct s3c2410_iobank_timing *bt;
438 unsigned long bankcon;
439 unsigned long bwscon;
440 int bank;
441
442 bwscon = __raw_readl(S3C2410_BWSCON);
443
444 /* look through all banks to see what is currently set. */
445
446 for (bank = 0; bank < MAX_BANKS; bank++) {
447 bankcon = __raw_readl(bank_reg(bank));
448
449 if (!bank_is_io(bankcon))
450 continue;
451
452 s3c_freq_iodbg("%s: bank %d: con %08lx\n",
453 __func__, bank, bankcon);
454
455 bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL);
456 if (!bt) {
457 printk(KERN_ERR "%s: no memory for bank\n", __func__);
458 return -ENOMEM;
459 }
460
461 /* find out in nWait is enabled for bank. */
462
463 if (bank != 0) {
464 unsigned long tmp = S3C2410_BWSCON_GET(bwscon, bank);
465 if (tmp & S3C2410_BWSCON_WS)
466 bt->nwait_en = 1;
467 }
468
469 timings->bank[bank].io_2410 = bt;
470 bt->bankcon = bankcon;
471
472 s3c2410_iotiming_getbank(cfg, bt);
473 }
474
475 s3c2410_print_timing("get", timings);
476 return 0;
477}
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
new file mode 100644
index 000000000000..95273424d657
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -0,0 +1,285 @@
1/*
2 * Copyright (c) 2006-2008 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412/S3C2443 (PL093 based) IO timing support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/cpufreq.h>
18#include <linux/seq_file.h>
19#include <linux/device.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22#include <linux/err.h>
23#include <linux/slab.h>
24
25#include <linux/amba/pl093.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <mach/regs-s3c2412-mem.h>
31
32#include <plat/cpu.h>
33#include <plat/cpu-freq-core.h>
34#include <plat/clock.h>
35
36#define print_ns(x) ((x) / 10), ((x) % 10)
37
38/**
39 * s3c2412_print_timing - print timing infromation via printk.
40 * @pfx: The prefix to print each line with.
41 * @iot: The IO timing information
42 */
43static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot)
44{
45 struct s3c2412_iobank_timing *bt;
46 unsigned int bank;
47
48 for (bank = 0; bank < MAX_BANKS; bank++) {
49 bt = iot->bank[bank].io_2412;
50 if (!bt)
51 continue;
52
53 printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
54 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank,
55 print_ns(bt->idcy),
56 print_ns(bt->wstrd),
57 print_ns(bt->wstwr),
58 print_ns(bt->wstoen),
59 print_ns(bt->wstwen),
60 print_ns(bt->wstbrd));
61 }
62}
63
64/**
65 * to_div - turn a cycle length into a divisor setting.
66 * @cyc_tns: The cycle time in 10ths of nanoseconds.
67 * @clk_tns: The clock period in 10ths of nanoseconds.
68 */
69static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns)
70{
71 return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0;
72}
73
74/**
75 * calc_timing - calculate timing divisor value and check in range.
76 * @hwtm: The hardware timing in 10ths of nanoseconds.
77 * @clk_tns: The clock period in 10ths of nanoseconds.
78 * @err: Pointer to err variable to update in event of failure.
79 */
80static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns,
81 unsigned int *err)
82{
83 unsigned int ret = to_div(hwtm, clk_tns);
84
85 if (ret > 0xf)
86 *err = -EINVAL;
87
88 return ret;
89}
90
91/**
92 * s3c2412_calc_bank - calculate the bank divisor settings.
93 * @cfg: The current frequency configuration.
94 * @bt: The bank timing.
95 */
96static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg,
97 struct s3c2412_iobank_timing *bt)
98{
99 unsigned int hclk = cfg->freq.hclk_tns;
100 int err = 0;
101
102 bt->smbidcyr = calc_timing(bt->idcy, hclk, &err);
103 bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err);
104 bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err);
105 bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err);
106 bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err);
107 bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err);
108
109 return err;
110}
111
112/**
113 * s3c2412_iotiming_debugfs - debugfs show io bank timing information
114 * @seq: The seq_file to write output to using seq_printf().
115 * @cfg: The current configuration.
116 * @iob: The IO bank information to decode.
117*/
118void s3c2412_iotiming_debugfs(struct seq_file *seq,
119 struct s3c_cpufreq_config *cfg,
120 union s3c_iobank *iob)
121{
122 struct s3c2412_iobank_timing *bt = iob->io_2412;
123
124 seq_printf(seq,
125 "\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
126 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n",
127 print_ns(bt->idcy),
128 print_ns(bt->wstrd),
129 print_ns(bt->wstwr),
130 print_ns(bt->wstoen),
131 print_ns(bt->wstwen),
132 print_ns(bt->wstbrd));
133}
134
135/**
136 * s3c2412_iotiming_calc - calculate all the bank divisor settings.
137 * @cfg: The current frequency configuration.
138 * @iot: The bank timing information.
139 *
140 * Calculate the timing information for all the banks that are
141 * configured as IO, using s3c2412_calc_bank().
142 */
143int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
144 struct s3c_iotimings *iot)
145{
146 struct s3c2412_iobank_timing *bt;
147 int bank;
148 int ret;
149
150 for (bank = 0; bank < MAX_BANKS; bank++) {
151 bt = iot->bank[bank].io_2412;
152 if (!bt)
153 continue;
154
155 ret = s3c2412_calc_bank(cfg, bt);
156 if (ret) {
157 printk(KERN_ERR "%s: cannot calculate bank %d io\n",
158 __func__, bank);
159 goto err;
160 }
161 }
162
163 return 0;
164 err:
165 return ret;
166}
167
168/**
169 * s3c2412_iotiming_set - set the timing information
170 * @cfg: The current frequency configuration.
171 * @iot: The bank timing information.
172 *
173 * Set the IO bank information from the details calculated earlier from
174 * calling s3c2412_iotiming_calc().
175 */
176void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
177 struct s3c_iotimings *iot)
178{
179 struct s3c2412_iobank_timing *bt;
180 void __iomem *regs;
181 int bank;
182
183 /* set the io timings from the specifier */
184
185 for (bank = 0; bank < MAX_BANKS; bank++) {
186 bt = iot->bank[bank].io_2412;
187 if (!bt)
188 continue;
189
190 regs = S3C2412_SSMC_BANK(bank);
191
192 __raw_writel(bt->smbidcyr, regs + SMBIDCYR);
193 __raw_writel(bt->smbwstrd, regs + SMBWSTRDR);
194 __raw_writel(bt->smbwstwr, regs + SMBWSTWRR);
195 __raw_writel(bt->smbwstoen, regs + SMBWSTOENR);
196 __raw_writel(bt->smbwstwen, regs + SMBWSTWENR);
197 __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR);
198 }
199}
200
201static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg)
202{
203 return (reg & 0xf) * clock;
204}
205
206static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg,
207 struct s3c2412_iobank_timing *bt,
208 unsigned int bank)
209{
210 unsigned long clk = cfg->freq.hclk_tns; /* ssmc clock??? */
211 void __iomem *regs = S3C2412_SSMC_BANK(bank);
212
213 bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR));
214 bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR));
215 bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR));
216 bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR));
217 bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR));
218}
219
220/**
221 * bank_is_io - return true if bank is (possibly) IO.
222 * @bank: The bank number.
223 * @bankcfg: The value of S3C2412_EBI_BANKCFG.
224 */
225static inline bool bank_is_io(unsigned int bank, u32 bankcfg)
226{
227 if (bank < 2)
228 return true;
229
230 return !(bankcfg & (1 << bank));
231}
232
233int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
234 struct s3c_iotimings *timings)
235{
236 struct s3c2412_iobank_timing *bt;
237 u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG);
238 unsigned int bank;
239
240 /* look through all banks to see what is currently set. */
241
242 for (bank = 0; bank < MAX_BANKS; bank++) {
243 if (!bank_is_io(bank, bankcfg))
244 continue;
245
246 bt = kzalloc(sizeof(struct s3c2412_iobank_timing), GFP_KERNEL);
247 if (!bt) {
248 printk(KERN_ERR "%s: no memory for bank\n", __func__);
249 return -ENOMEM;
250 }
251
252 timings->bank[bank].io_2412 = bt;
253 s3c2412_iotiming_getbank(cfg, bt, bank);
254 }
255
256 s3c2412_print_timing("get", timings);
257 return 0;
258}
259
260/* this is in here as it is so small, it doesn't currently warrant a file
261 * to itself. We expect that any s3c24xx needing this is going to also
262 * need the iotiming support.
263 */
264void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
265{
266 struct s3c_cpufreq_board *board = cfg->board;
267 u32 refresh;
268
269 WARN_ON(board == NULL);
270
271 /* Reduce both the refresh time (in ns) and the frequency (in MHz)
272 * down to ensure that we do not overflow 32 bit numbers.
273 *
274 * This should work for HCLK up to 133MHz and refresh period up
275 * to 30usec.
276 */
277
278 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
279 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
280 refresh &= ((1 << 16) - 1);
281
282 s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh);
283
284 __raw_writel(refresh, S3C2412_REFRESH);
285}
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
new file mode 100644
index 000000000000..cb9f5e011e73
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/irq.c
@@ -0,0 +1,822 @@
1/*
2 * S3C24XX IRQ handling
3 *
4 * Copyright (c) 2003-2004 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17*/
18
19#include <linux/init.h>
20#include <linux/slab.h>
21#include <linux/module.h>
22#include <linux/io.h>
23#include <linux/err.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/device.h>
27#include <linux/irqdomain.h>
28
29#include <asm/mach/irq.h>
30
31#include <mach/regs-irq.h>
32#include <mach/regs-gpio.h>
33
34#include <plat/cpu.h>
35#include <plat/regs-irqtype.h>
36#include <plat/pm.h>
37#include <plat/irq.h>
38
39#define S3C_IRQTYPE_NONE 0
40#define S3C_IRQTYPE_EINT 1
41#define S3C_IRQTYPE_EDGE 2
42#define S3C_IRQTYPE_LEVEL 3
43
44struct s3c_irq_data {
45 unsigned int type;
46 unsigned long parent_irq;
47
48 /* data gets filled during init */
49 struct s3c_irq_intc *intc;
50 unsigned long sub_bits;
51 struct s3c_irq_intc *sub_intc;
52};
53
54/*
55 * Sructure holding the controller data
56 * @reg_pending register holding pending irqs
57 * @reg_intpnd special register intpnd in main intc
58 * @reg_mask mask register
59 * @domain irq_domain of the controller
60 * @parent parent controller for ext and sub irqs
61 * @irqs irq-data, always s3c_irq_data[32]
62 */
63struct s3c_irq_intc {
64 void __iomem *reg_pending;
65 void __iomem *reg_intpnd;
66 void __iomem *reg_mask;
67 struct irq_domain *domain;
68 struct s3c_irq_intc *parent;
69 struct s3c_irq_data *irqs;
70};
71
72static void s3c_irq_mask(struct irq_data *data)
73{
74 struct s3c_irq_intc *intc = data->domain->host_data;
75 struct s3c_irq_intc *parent_intc = intc->parent;
76 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
77 struct s3c_irq_data *parent_data;
78 unsigned long mask;
79 unsigned int irqno;
80
81 mask = __raw_readl(intc->reg_mask);
82 mask |= (1UL << data->hwirq);
83 __raw_writel(mask, intc->reg_mask);
84
85 if (parent_intc && irq_data->parent_irq) {
86 parent_data = &parent_intc->irqs[irq_data->parent_irq];
87
88 /* check to see if we need to mask the parent IRQ */
89 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
90 irqno = irq_find_mapping(parent_intc->domain,
91 irq_data->parent_irq);
92 s3c_irq_mask(irq_get_irq_data(irqno));
93 }
94 }
95}
96
97static void s3c_irq_unmask(struct irq_data *data)
98{
99 struct s3c_irq_intc *intc = data->domain->host_data;
100 struct s3c_irq_intc *parent_intc = intc->parent;
101 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
102 unsigned long mask;
103 unsigned int irqno;
104
105 mask = __raw_readl(intc->reg_mask);
106 mask &= ~(1UL << data->hwirq);
107 __raw_writel(mask, intc->reg_mask);
108
109 if (parent_intc && irq_data->parent_irq) {
110 irqno = irq_find_mapping(parent_intc->domain,
111 irq_data->parent_irq);
112 s3c_irq_unmask(irq_get_irq_data(irqno));
113 }
114}
115
116static inline void s3c_irq_ack(struct irq_data *data)
117{
118 struct s3c_irq_intc *intc = data->domain->host_data;
119 unsigned long bitval = 1UL << data->hwirq;
120
121 __raw_writel(bitval, intc->reg_pending);
122 if (intc->reg_intpnd)
123 __raw_writel(bitval, intc->reg_intpnd);
124}
125
126static int s3c_irqext_type_set(void __iomem *gpcon_reg,
127 void __iomem *extint_reg,
128 unsigned long gpcon_offset,
129 unsigned long extint_offset,
130 unsigned int type)
131{
132 unsigned long newvalue = 0, value;
133
134 /* Set the GPIO to external interrupt mode */
135 value = __raw_readl(gpcon_reg);
136 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
137 __raw_writel(value, gpcon_reg);
138
139 /* Set the external interrupt to pointed trigger type */
140 switch (type)
141 {
142 case IRQ_TYPE_NONE:
143 pr_warn("No edge setting!\n");
144 break;
145
146 case IRQ_TYPE_EDGE_RISING:
147 newvalue = S3C2410_EXTINT_RISEEDGE;
148 break;
149
150 case IRQ_TYPE_EDGE_FALLING:
151 newvalue = S3C2410_EXTINT_FALLEDGE;
152 break;
153
154 case IRQ_TYPE_EDGE_BOTH:
155 newvalue = S3C2410_EXTINT_BOTHEDGE;
156 break;
157
158 case IRQ_TYPE_LEVEL_LOW:
159 newvalue = S3C2410_EXTINT_LOWLEV;
160 break;
161
162 case IRQ_TYPE_LEVEL_HIGH:
163 newvalue = S3C2410_EXTINT_HILEV;
164 break;
165
166 default:
167 pr_err("No such irq type %d", type);
168 return -EINVAL;
169 }
170
171 value = __raw_readl(extint_reg);
172 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
173 __raw_writel(value, extint_reg);
174
175 return 0;
176}
177
178/* FIXME: make static when it's out of plat-samsung/irq.h */
179int s3c_irqext_type(struct irq_data *data, unsigned int type)
180{
181 void __iomem *extint_reg;
182 void __iomem *gpcon_reg;
183 unsigned long gpcon_offset, extint_offset;
184
185 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
186 gpcon_reg = S3C2410_GPFCON;
187 extint_reg = S3C24XX_EXTINT0;
188 gpcon_offset = (data->hwirq) * 2;
189 extint_offset = (data->hwirq) * 4;
190 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
191 gpcon_reg = S3C2410_GPGCON;
192 extint_reg = S3C24XX_EXTINT1;
193 gpcon_offset = (data->hwirq - 8) * 2;
194 extint_offset = (data->hwirq - 8) * 4;
195 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
196 gpcon_reg = S3C2410_GPGCON;
197 extint_reg = S3C24XX_EXTINT2;
198 gpcon_offset = (data->hwirq - 8) * 2;
199 extint_offset = (data->hwirq - 16) * 4;
200 } else {
201 return -EINVAL;
202 }
203
204 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
205 extint_offset, type);
206}
207
208static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
209{
210 void __iomem *extint_reg;
211 void __iomem *gpcon_reg;
212 unsigned long gpcon_offset, extint_offset;
213
214 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
215 gpcon_reg = S3C2410_GPFCON;
216 extint_reg = S3C24XX_EXTINT0;
217 gpcon_offset = (data->hwirq) * 2;
218 extint_offset = (data->hwirq) * 4;
219 } else {
220 return -EINVAL;
221 }
222
223 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
224 extint_offset, type);
225}
226
227struct irq_chip s3c_irq_chip = {
228 .name = "s3c",
229 .irq_ack = s3c_irq_ack,
230 .irq_mask = s3c_irq_mask,
231 .irq_unmask = s3c_irq_unmask,
232 .irq_set_wake = s3c_irq_wake
233};
234
235struct irq_chip s3c_irq_level_chip = {
236 .name = "s3c-level",
237 .irq_mask = s3c_irq_mask,
238 .irq_unmask = s3c_irq_unmask,
239 .irq_ack = s3c_irq_ack,
240};
241
242static struct irq_chip s3c_irqext_chip = {
243 .name = "s3c-ext",
244 .irq_mask = s3c_irq_mask,
245 .irq_unmask = s3c_irq_unmask,
246 .irq_ack = s3c_irq_ack,
247 .irq_set_type = s3c_irqext_type,
248 .irq_set_wake = s3c_irqext_wake
249};
250
251static struct irq_chip s3c_irq_eint0t4 = {
252 .name = "s3c-ext0",
253 .irq_ack = s3c_irq_ack,
254 .irq_mask = s3c_irq_mask,
255 .irq_unmask = s3c_irq_unmask,
256 .irq_set_wake = s3c_irq_wake,
257 .irq_set_type = s3c_irqext0_type,
258};
259
260static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
261{
262 struct irq_chip *chip = irq_desc_get_chip(desc);
263 struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
264 struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
265 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
266 unsigned long src;
267 unsigned long msk;
268 unsigned int n;
269
270 chained_irq_enter(chip, desc);
271
272 src = __raw_readl(sub_intc->reg_pending);
273 msk = __raw_readl(sub_intc->reg_mask);
274
275 src &= ~msk;
276 src &= irq_data->sub_bits;
277
278 while (src) {
279 n = __ffs(src);
280 src &= ~(1 << n);
281 generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
282 }
283
284 chained_irq_exit(chip, desc);
285}
286
287#ifdef CONFIG_FIQ
288/**
289 * s3c24xx_set_fiq - set the FIQ routing
290 * @irq: IRQ number to route to FIQ on processor.
291 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
292 *
293 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
294 * @on is true, the @irq is checked to see if it can be routed and the
295 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
296 * routing is cleared, regardless of which @irq is specified.
297 */
298int s3c24xx_set_fiq(unsigned int irq, bool on)
299{
300 u32 intmod;
301 unsigned offs;
302
303 if (on) {
304 offs = irq - FIQ_START;
305 if (offs > 31)
306 return -EINVAL;
307
308 intmod = 1 << offs;
309 } else {
310 intmod = 0;
311 }
312
313 __raw_writel(intmod, S3C2410_INTMOD);
314 return 0;
315}
316
317EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
318#endif
319
320static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
321 irq_hw_number_t hw)
322{
323 struct s3c_irq_intc *intc = h->host_data;
324 struct s3c_irq_data *irq_data = &intc->irqs[hw];
325 struct s3c_irq_intc *parent_intc;
326 struct s3c_irq_data *parent_irq_data;
327 unsigned int irqno;
328
329 if (!intc) {
330 pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
331 return -EINVAL;
332 }
333
334 if (!irq_data) {
335 pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
336 return -EINVAL;
337 }
338
339 /* attach controller pointer to irq_data */
340 irq_data->intc = intc;
341
342 /* set handler and flags */
343 switch (irq_data->type) {
344 case S3C_IRQTYPE_NONE:
345 return 0;
346 case S3C_IRQTYPE_EINT:
347 if (irq_data->parent_irq)
348 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
349 handle_edge_irq);
350 else
351 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
352 handle_edge_irq);
353 break;
354 case S3C_IRQTYPE_EDGE:
355 if (irq_data->parent_irq ||
356 intc->reg_pending == S3C2416_SRCPND2)
357 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
358 handle_edge_irq);
359 else
360 irq_set_chip_and_handler(virq, &s3c_irq_chip,
361 handle_edge_irq);
362 break;
363 case S3C_IRQTYPE_LEVEL:
364 if (irq_data->parent_irq)
365 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
366 handle_level_irq);
367 else
368 irq_set_chip_and_handler(virq, &s3c_irq_chip,
369 handle_level_irq);
370 break;
371 default:
372 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
373 return -EINVAL;
374 }
375 set_irq_flags(virq, IRQF_VALID);
376
377 if (irq_data->parent_irq) {
378 parent_intc = intc->parent;
379 if (!parent_intc) {
380 pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
381 hw);
382 goto err;
383 }
384
385 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
386 if (!irq_data) {
387 pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
388 hw);
389 goto err;
390 }
391
392 parent_irq_data->sub_intc = intc;
393 parent_irq_data->sub_bits |= (1UL << hw);
394
395 /* attach the demuxer to the parent irq */
396 irqno = irq_find_mapping(parent_intc->domain,
397 irq_data->parent_irq);
398 if (!irqno) {
399 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
400 irq_data->parent_irq);
401 goto err;
402 }
403 irq_set_chained_handler(irqno, s3c_irq_demux);
404 }
405
406 return 0;
407
408err:
409 set_irq_flags(virq, 0);
410
411 /* the only error can result from bad mapping data*/
412 return -EINVAL;
413}
414
415static struct irq_domain_ops s3c24xx_irq_ops = {
416 .map = s3c24xx_irq_map,
417 .xlate = irq_domain_xlate_twocell,
418};
419
420static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
421{
422 void __iomem *reg_source;
423 unsigned long pend;
424 unsigned long last;
425 int i;
426
427 /* if intpnd is set, read the next pending irq from there */
428 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
429
430 last = 0;
431 for (i = 0; i < 4; i++) {
432 pend = __raw_readl(reg_source);
433
434 if (pend == 0 || pend == last)
435 break;
436
437 __raw_writel(pend, intc->reg_pending);
438 if (intc->reg_intpnd)
439 __raw_writel(pend, intc->reg_intpnd);
440
441 pr_info("irq: clearing pending status %08x\n", (int)pend);
442 last = pend;
443 }
444}
445
446struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
447 struct s3c_irq_data *irq_data,
448 struct s3c_irq_intc *parent,
449 unsigned long address)
450{
451 struct s3c_irq_intc *intc;
452 void __iomem *base = (void *)0xf6000000; /* static mapping */
453 int irq_num;
454 int irq_start;
455 int irq_offset;
456 int ret;
457
458 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
459 if (!intc)
460 return ERR_PTR(-ENOMEM);
461
462 intc->irqs = irq_data;
463
464 if (parent)
465 intc->parent = parent;
466
467 /* select the correct data for the controller.
468 * Need to hard code the irq num start and offset
469 * to preserve the static mapping for now
470 */
471 switch (address) {
472 case 0x4a000000:
473 pr_debug("irq: found main intc\n");
474 intc->reg_pending = base;
475 intc->reg_mask = base + 0x08;
476 intc->reg_intpnd = base + 0x10;
477 irq_num = 32;
478 irq_start = S3C2410_IRQ(0);
479 irq_offset = 0;
480 break;
481 case 0x4a000018:
482 pr_debug("irq: found subintc\n");
483 intc->reg_pending = base + 0x18;
484 intc->reg_mask = base + 0x1c;
485 irq_num = 29;
486 irq_start = S3C2410_IRQSUB(0);
487 irq_offset = 0;
488 break;
489 case 0x4a000040:
490 pr_debug("irq: found intc2\n");
491 intc->reg_pending = base + 0x40;
492 intc->reg_mask = base + 0x48;
493 intc->reg_intpnd = base + 0x50;
494 irq_num = 8;
495 irq_start = S3C2416_IRQ(0);
496 irq_offset = 0;
497 break;
498 case 0x560000a4:
499 pr_debug("irq: found eintc\n");
500 base = (void *)0xfd000000;
501
502 intc->reg_mask = base + 0xa4;
503 intc->reg_pending = base + 0x08;
504 irq_num = 20;
505 irq_start = S3C2410_IRQ(32);
506 irq_offset = 4;
507 break;
508 default:
509 pr_err("irq: unsupported controller address\n");
510 ret = -EINVAL;
511 goto err;
512 }
513
514 /* now that all the data is complete, init the irq-domain */
515 s3c24xx_clear_intc(intc);
516 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
517 irq_offset, &s3c24xx_irq_ops,
518 intc);
519 if (!intc->domain) {
520 pr_err("irq: could not create irq-domain\n");
521 ret = -EINVAL;
522 goto err;
523 }
524
525 return intc;
526
527err:
528 kfree(intc);
529 return ERR_PTR(ret);
530}
531
532/* s3c24xx_init_irq
533 *
534 * Initialise S3C2410 IRQ system
535*/
536
537static struct s3c_irq_data init_base[32] = {
538 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
539 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
540 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
541 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
542 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
543 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
544 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
545 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
546 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
547 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
548 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
549 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
550 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
551 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
552 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
553 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
554 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
555 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
556 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
557 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
558 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
559 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
560 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
561 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
562 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
563 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
564 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
565 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
566 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
567 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
568 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
569 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
570};
571
572static struct s3c_irq_data init_eint[32] = {
573 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
574 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
575 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
576 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
577 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
578 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
579 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
580 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
581 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
582 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
583 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
584 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
585 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
586 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
587 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
588 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
589 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
590 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
591 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
592 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
593 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
594 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
595 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
596 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
597};
598
599static struct s3c_irq_data init_subint[32] = {
600 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
601 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
602 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
603 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
604 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
605 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
606 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
607 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
608 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
609 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
610 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
611};
612
613void __init s3c24xx_init_irq(void)
614{
615 struct s3c_irq_intc *main_intc;
616
617#ifdef CONFIG_FIQ
618 init_FIQ(FIQ_START);
619#endif
620
621 main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
622 if (IS_ERR(main_intc)) {
623 pr_err("irq: could not create main interrupt controller\n");
624 return;
625 }
626
627 s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
628 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
629}
630
631#ifdef CONFIG_CPU_S3C2416
632static struct s3c_irq_data init_s3c2416base[32] = {
633 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
634 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
635 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
636 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
637 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
638 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
639 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
640 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
641 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
642 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
643 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
644 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
645 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
646 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
647 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
648 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
649 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
650 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
651 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
652 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
653 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
654 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
655 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
656 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
657 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
658 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
659 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
660 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
661 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
662 { .type = S3C_IRQTYPE_NONE, },
663 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
664 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
665};
666
667static struct s3c_irq_data init_s3c2416subint[32] = {
668 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
669 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
670 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
671 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
676 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
677 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
678 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
679 { .type = S3C_IRQTYPE_NONE }, /* reserved */
680 { .type = S3C_IRQTYPE_NONE }, /* reserved */
681 { .type = S3C_IRQTYPE_NONE }, /* reserved */
682 { .type = S3C_IRQTYPE_NONE }, /* reserved */
683 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
684 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
685 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
686 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
687 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
688 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
689 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
690 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
691 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
692 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
693 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
694 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
695 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
696 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
697};
698
699static struct s3c_irq_data init_s3c2416_second[32] = {
700 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
701 { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
702 { .type = S3C_IRQTYPE_NONE }, /* reserved */
703 { .type = S3C_IRQTYPE_NONE }, /* reserved */
704 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
705 { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
706 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
707 { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
708};
709
710void __init s3c2416_init_irq(void)
711{
712 struct s3c_irq_intc *main_intc;
713
714 pr_info("S3C2416: IRQ Support\n");
715
716#ifdef CONFIG_FIQ
717 init_FIQ(FIQ_START);
718#endif
719
720 main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
721 if (IS_ERR(main_intc)) {
722 pr_err("irq: could not create main interrupt controller\n");
723 return;
724 }
725
726 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
727 s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
728
729 s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
730}
731
732#endif
733
734#ifdef CONFIG_CPU_S3C2443
735static struct s3c_irq_data init_s3c2443base[32] = {
736 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
737 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
738 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
739 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
740 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
741 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
742 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
743 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
744 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
745 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
746 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
747 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
748 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
749 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
750 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
751 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
752 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
753 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
754 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
755 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
756 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
757 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
758 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
759 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
760 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
761 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
762 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
763 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
764 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
765 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
766 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
767 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
768};
769
770
771static struct s3c_irq_data init_s3c2443subint[32] = {
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
776 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
777 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
778 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
779 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
780 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
781 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
782 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
783 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
784 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
785 { .type = S3C_IRQTYPE_NONE }, /* reserved */
786 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
787 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
788 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
789 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
790 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
791 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
792 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
793 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
794 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
795 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
796 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
797 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
798 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
799 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
800 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
801};
802
803void __init s3c2443_init_irq(void)
804{
805 struct s3c_irq_intc *main_intc;
806
807 pr_info("S3C2443: IRQ Support\n");
808
809#ifdef CONFIG_FIQ
810 init_FIQ(FIQ_START);
811#endif
812
813 main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
814 if (IS_ERR(main_intc)) {
815 pr_err("irq: could not create main interrupt controller\n");
816 return;
817 }
818
819 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
820 s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
821}
822#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 22:45:57 -0500