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authorArnd Bergmann <arnd@arndb.de>2013-02-14 09:05:40 -0500
committerArnd Bergmann <arnd@arndb.de>2013-02-14 09:05:40 -0500
commit7822eee1acbbea254212ad69ac99aae7986461da (patch)
treed7168d2e23130e3e6c36a731edc29eadd5128fc2 /arch/arm/mach-s3c24xx
parent0e55f0b0037c91bf269f7975ad353c31d8d12c32 (diff)
parent8c0c774dd7b4aa0e0b69f483a70c7f41995139ef (diff)
Merge branch 'warning-fixes' into next/fixes-non-critical
These are fixes for compiler warnings that for the most part were introduced during the 3.8 cycle but are otherwise harmless. * warning-fixes: scripts/sortextable: silence script output ARM: s3c: i2c: add platform_device forward declaration ARM: mvebu: allow selecting mvebu without Armada XP ARM: pick Versatile by default for !MMU ARM: integrator: fix build with INTEGRATOR_AP off ARM: integrator/versatile: fix NOMMU warnings ARM: sa1100: don't warn about mach/ide.h ARM: shmobile: fix defconfig warning on CONFIG_USB ARM: w90x900: fix legacy assembly syntax ARM: samsung: fix assembly syntax for new gas ARM: disable virt_to_bus/virt_to_bus almost everywhere Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-s3c24xx')
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/debug-macro.S12
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/entry-macro.S4
-rw-r--r--arch/arm/mach-s3c24xx/pm-h1940.S2
-rw-r--r--arch/arm/mach-s3c24xx/sleep-s3c2410.S12
-rw-r--r--arch/arm/mach-s3c24xx/sleep-s3c2412.S12
5 files changed, 21 insertions, 21 deletions
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
index 4135de87d1f7..13ed33c69113 100644
--- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
@@ -40,17 +40,17 @@
40 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) 40 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
41 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) 41 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
42 bic \rd, \rd, #0xff000 42 bic \rd, \rd, #0xff000
43 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] 43 ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
44 and \rd, \rd, #0x00ff0000 44 and \rd, \rd, #0x00ff0000
45 teq \rd, #0x00440000 @ is it 2440? 45 teq \rd, #0x00440000 @ is it 2440?
461004: 461004:
47 ldr \rd, [ \rx, # S3C2410_UFSTAT ] 47 ldr \rd, [\rx, # S3C2410_UFSTAT]
48 moveq \rd, \rd, lsr #SHIFT_2440TXF 48 moveq \rd, \rd, lsr #SHIFT_2440TXF
49 tst \rd, #S3C2410_UFSTAT_TXFULL 49 tst \rd, #S3C2410_UFSTAT_TXFULL
50 .endm 50 .endm
51 51
52 .macro fifo_full_s3c2410 rd, rx 52 .macro fifo_full_s3c2410 rd, rx
53 ldr \rd, [ \rx, # S3C2410_UFSTAT ] 53 ldr \rd, [\rx, # S3C2410_UFSTAT]
54 tst \rd, #S3C2410_UFSTAT_TXFULL 54 tst \rd, #S3C2410_UFSTAT_TXFULL
55 .endm 55 .endm
56 56
@@ -68,18 +68,18 @@
68 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) 68 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
69 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) 69 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
70 bic \rd, \rd, #0xff000 70 bic \rd, \rd, #0xff000
71 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] 71 ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
72 and \rd, \rd, #0x00ff0000 72 and \rd, \rd, #0x00ff0000
73 teq \rd, #0x00440000 @ is it 2440? 73 teq \rd, #0x00440000 @ is it 2440?
74 74
7510000: 7510000:
76 ldr \rd, [ \rx, # S3C2410_UFSTAT ] 76 ldr \rd, [\rx, # S3C2410_UFSTAT]
77 andne \rd, \rd, #S3C2410_UFSTAT_TXMASK 77 andne \rd, \rd, #S3C2410_UFSTAT_TXMASK
78 andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK 78 andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK
79 .endm 79 .endm
80 80
81 .macro fifo_level_s3c2410 rd, rx 81 .macro fifo_level_s3c2410 rd, rx
82 ldr \rd, [ \rx, # S3C2410_UFSTAT ] 82 ldr \rd, [\rx, # S3C2410_UFSTAT]
83 and \rd, \rd, #S3C2410_UFSTAT_TXMASK 83 and \rd, \rd, #S3C2410_UFSTAT_TXMASK
84 .endm 84 .endm
85 85
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
index 7615a14773fa..6a21beeba1da 100644
--- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
@@ -31,10 +31,10 @@
31 31
32 @@ try the interrupt offset register, since it is there 32 @@ try the interrupt offset register, since it is there
33 33
34 ldr \irqstat, [ \base, #INTPND ] 34 ldr \irqstat, [\base, #INTPND ]
35 teq \irqstat, #0 35 teq \irqstat, #0
36 beq 1002f 36 beq 1002f
37 ldr \irqnr, [ \base, #INTOFFSET ] 37 ldr \irqnr, [\base, #INTOFFSET ]
38 mov \tmp, #1 38 mov \tmp, #1
39 tst \irqstat, \tmp, lsl \irqnr 39 tst \irqstat, \tmp, lsl \irqnr
40 bne 1001f 40 bne 1001f
diff --git a/arch/arm/mach-s3c24xx/pm-h1940.S b/arch/arm/mach-s3c24xx/pm-h1940.S
index c93bf2db9f4d..6183a688012b 100644
--- a/arch/arm/mach-s3c24xx/pm-h1940.S
+++ b/arch/arm/mach-s3c24xx/pm-h1940.S
@@ -30,4 +30,4 @@
30 30
31h1940_pm_return: 31h1940_pm_return:
32 mov r0, #S3C2410_PA_GPIO 32 mov r0, #S3C2410_PA_GPIO
33 ldr pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ] 33 ldr pc, [r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO]
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
index dd5b6388a5a5..65200ae72c90 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
@@ -45,9 +45,9 @@ ENTRY(s3c2410_cpu_suspend)
45 ldr r4, =S3C2410_REFRESH 45 ldr r4, =S3C2410_REFRESH
46 ldr r5, =S3C24XX_MISCCR 46 ldr r5, =S3C24XX_MISCCR
47 ldr r6, =S3C2410_CLKCON 47 ldr r6, =S3C2410_CLKCON
48 ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB) 48 ldr r7, [r4] @ get REFRESH (and ensure in TLB)
49 ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB) 49 ldr r8, [r5] @ get MISCCR (and ensure in TLB)
50 ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB) 50 ldr r9, [r6] @ get CLKCON (and ensure in TLB)
51 51
52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command 52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals 53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
@@ -61,8 +61,8 @@ ENTRY(s3c2410_cpu_suspend)
61 @@ align next bit of code to cache line 61 @@ align next bit of code to cache line
62 .align 5 62 .align 5
63s3c2410_do_sleep: 63s3c2410_do_sleep:
64 streq r7, [ r4 ] @ SDRAM sleep command 64 streq r7, [r4] @ SDRAM sleep command
65 streq r8, [ r5 ] @ SDRAM power-down config 65 streq r8, [r5] @ SDRAM power-down config
66 streq r9, [ r6 ] @ CPU sleep 66 streq r9, [r6] @ CPU sleep
671: beq 1b 671: beq 1b
68 mov pc, r14 68 mov pc, r14
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2412.S b/arch/arm/mach-s3c24xx/sleep-s3c2412.S
index c82418ed714d..5adaceb7da13 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2412.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2412.S
@@ -57,12 +57,12 @@ s3c2412_sleep_enter1:
57 * retry, as simply returning causes the system to lock. 57 * retry, as simply returning causes the system to lock.
58 */ 58 */
59 59
60 ldrne r9, [ r1 ] 60 ldrne r9, [r1]
61 strne r9, [ r1 ] 61 strne r9, [r1]
62 ldrne r9, [ r2 ] 62 ldrne r9, [r2]
63 strne r9, [ r2 ] 63 strne r9, [r2]
64 ldrne r9, [ r3 ] 64 ldrne r9, [r3]
65 strne r9, [ r3 ] 65 strne r9, [r3]
66 bne s3c2412_sleep_enter1 66 bne s3c2412_sleep_enter1
67 67
68 mov pc, r14 68 mov pc, r14