ARM: S3C24XX: add support for second irq set of S3C2416

The S3C2416 has a separate second interrupt register-set to support
additional irqs. This patch adds the necessary constants and registers
the irq handlers for it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 7743fade50df..ed5a95ece9eb 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -106,6 +106,7 @@ int __init s3c2416_init(void)
         register_syscore_ops(&s3c2416_pm_syscore_ops);
 #endif
         register_syscore_ops(&s3c24xx_irq_syscore_ops);
+        register_syscore_ops(&s3c2416_irq_syscore_ops);
 
         return device_register(&s3c2416_dev);
 }