ARM: S3C24XX: add support for second irq set of S3C2416

The S3C2416 has a separate second interrupt register-set to support
additional irqs. This patch adds the necessary constants and registers
the irq handlers for it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 14 insertions, 1 deletions

diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index e53b2177319e..b7a9f4d469e8 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -134,6 +134,17 @@
 #define IRQ_S32416_WDT          S3C2410_IRQSUB(27)
 #define IRQ_S32416_AC97         S3C2410_IRQSUB(28)
 
+/* second interrupt-register of s3c2416/s3c2450 */
+
+#define S3C2416_IRQ(x)          S3C2410_IRQ((x) + 54 + 29)
+#define IRQ_S3C2416_2D          S3C2416_IRQ(0)
+#define IRQ_S3C2416_IIC1        S3C2416_IRQ(1)
+#define IRQ_S3C2416_RESERVED2   S3C2416_IRQ(2)
+#define IRQ_S3C2416_RESERVED3   S3C2416_IRQ(3)
+#define IRQ_S3C2416_PCM0        S3C2416_IRQ(4)
+#define IRQ_S3C2416_PCM1        S3C2416_IRQ(5)
+#define IRQ_S3C2416_I2S0        S3C2416_IRQ(6)
+#define IRQ_S3C2416_I2S1        S3C2416_IRQ(7)
 
 /* extra irqs for s3c2440 */
 
@@ -175,7 +186,9 @@
 #define IRQ_S3C2443_WDT         S3C2410_IRQSUB(27)
 #define IRQ_S3C2443_AC97        S3C2410_IRQSUB(28)
 
-#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
+#if defined(CONFIG_CPU_S3C2416)
+#define NR_IRQS (IRQ_S3C2416_I2S1 + 1)
+#elif defined(CONFIG_CPU_S3C2443)
 #define NR_IRQS (IRQ_S3C2443_AC97+1)
 #else
 #define NR_IRQS (IRQ_S3C2440_AC97+1)