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authorKukjin Kim <kgene.kim@samsung.com>2013-01-31 19:54:38 -0500
committerKukjin Kim <kgene.kim@samsung.com>2013-02-03 19:17:10 -0500
commit09ec1d7ea67f6e23b6ef2178fa2ec48fd65477dc (patch)
tree38318b5c98f48754521a288f40e3c77a1fe8a623 /arch/arm/mach-s3c24xx/cpufreq-utils.c
parentf44ddba3635e35317057e976888d4a12dcb0f842 (diff)
ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/
This patch is for just moving plat-s3c24xx/*.c into mach-s3c24xx/, so that we could remove plat-s3c24xx directory. But since the PLAT_S3C24XX is used in drivers, the statement is not deleted and it will be sorted out next time. Cc: Ben Dooks <ben-linux@fluff.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c24xx/cpufreq-utils.c')
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-utils.c63
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
new file mode 100644
index 000000000000..89e4e2b7a82e
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright (c) 2009 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/cpufreq.h>
16#include <linux/io.h>
17
18#include <mach/map.h>
19#include <mach/regs-mem.h>
20#include <mach/regs-clock.h>
21
22#include <plat/cpu-freq-core.h>
23
24/**
25 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
26 * @cfg: The frequency configuration
27 *
28 * Set the SDRAM refresh value appropriately for the configured
29 * frequency.
30 */
31void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
32{
33 struct s3c_cpufreq_board *board = cfg->board;
34 unsigned long refresh;
35 unsigned long refval;
36
37 /* Reduce both the refresh time (in ns) and the frequency (in MHz)
38 * down to ensure that we do not overflow 32 bit numbers.
39 *
40 * This should work for HCLK up to 133MHz and refresh period up
41 * to 30usec.
42 */
43
44 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
45 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
46 refresh = (1 << 11) + 1 - refresh;
47
48 s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
49
50 refval = __raw_readl(S3C2410_REFRESH);
51 refval &= ~((1 << 12) - 1);
52 refval |= refresh;
53 __raw_writel(refval, S3C2410_REFRESH);
54}
55
56/**
57 * s3c2410_set_fvco - set the PLL value
58 * @cfg: The frequency configuration
59 */
60void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
61{
62 __raw_writel(cfg->pll.index, S3C2410_MPLLCON);
63}