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authorBen Dooks <ben-linux@fluff.org>2008-10-21 09:07:00 -0400
committerBen Dooks <ben-linux@fluff.org>2008-12-15 16:53:58 -0500
commit4b31d8b2256db3ed825a63603f223f84d927ca39 (patch)
tree256cfe52c637140342791d230c0f3de4b725284b /arch/arm/mach-s3c2443
parent952b564b4d26964e3114d02368741e192e30ae28 (diff)
[ARM] S3C64XX: Add initial clock framework
Add the initial clocks definitions for the s3c6400 and s3c6410. Move the epll and ext clock from the s3c2443 support into the common code. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c2443')
-rw-r--r--arch/arm/mach-s3c2443/clock.c15
1 files changed, 1 insertions, 14 deletions
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 1df8429242b8..363f39608783 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -147,12 +147,6 @@ static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk,
147 147
148/* clock selections */ 148/* clock selections */
149 149
150/* CPU EXTCLK input */
151static struct clk clk_ext = {
152 .name = "ext",
153 .id = -1,
154};
155
156static struct clk clk_mpllref = { 150static struct clk clk_mpllref = {
157 .name = "mpllref", 151 .name = "mpllref",
158 .parent = &clk_xtal, 152 .parent = &clk_xtal,
@@ -167,14 +161,6 @@ static struct clk clk_mpll = {
167}; 161};
168#endif 162#endif
169 163
170static struct clk clk_epllref;
171
172static struct clk clk_epll = {
173 .name = "epll",
174 .parent = &clk_epllref,
175 .id = -1,
176};
177
178static struct clk clk_i2s_ext = { 164static struct clk clk_i2s_ext = {
179 .name = "i2s-ext", 165 .name = "i2s-ext",
180 .id = -1, 166 .id = -1,
@@ -1072,6 +1058,7 @@ void __init s3c2443_init_clocks(int xtal)
1072 } 1058 }
1073 1059
1074 clk_epll.rate = s3c2443_get_epll(epllcon, xtal); 1060 clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
1061 clk_epll.parent = &clk_epllref;
1075 clk_usb_bus.parent = &clk_usb_bus_host; 1062 clk_usb_bus.parent = &clk_usb_bus_host;
1076 1063
1077 /* ensure usb bus clock is within correct rate of 48MHz */ 1064 /* ensure usb bus clock is within correct rate of 48MHz */