diff options
author | Ben Dooks <ben-linux@fluff.org> | 2010-01-26 02:31:32 -0500 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-02-01 12:55:31 -0500 |
commit | 916ee9249a7f19d8eb18cc9ee16ca495a517ab34 (patch) | |
tree | 43e77e20a48d32586ec44a46fab1c32782aa55d5 /arch/arm/mach-s3c2442 | |
parent | 1f51bbfd5905b8c860cc95ae10c20e0844d0ade8 (diff) |
ARM: S3C244X: Move S3C2442 code into S3C2440
Move the remaining S3C2442 code into mach-s3c2440 as there is only one
file currently in there and these two SoCs are very similar.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c2442')
-rw-r--r-- | arch/arm/mach-s3c2442/Kconfig | 11 | ||||
-rw-r--r-- | arch/arm/mach-s3c2442/s3c2442.c | 165 |
2 files changed, 0 insertions, 176 deletions
diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig index 4832cd6ccfbc..29ef0669e959 100644 --- a/arch/arm/mach-s3c2442/Kconfig +++ b/arch/arm/mach-s3c2442/Kconfig | |||
@@ -2,14 +2,3 @@ | |||
2 | # | 2 | # |
3 | # Licensed under GPLv2 | 3 | # Licensed under GPLv2 |
4 | 4 | ||
5 | config CPU_S3C2442 | ||
6 | bool | ||
7 | depends on ARCH_S3C2410 | ||
8 | select CPU_ARM920T | ||
9 | select S3C2410_CLOCK | ||
10 | select S3C2410_GPIO | ||
11 | select S3C2410_PM if PM | ||
12 | select CPU_S3C244X | ||
13 | select CPU_LLSERIAL_S3C2440 | ||
14 | help | ||
15 | Support for S3C2442 Samsung Mobile CPU based systems. | ||
diff --git a/arch/arm/mach-s3c2442/s3c2442.c b/arch/arm/mach-s3c2442/s3c2442.c deleted file mode 100644 index 188ad1e57dc0..000000000000 --- a/arch/arm/mach-s3c2442/s3c2442.c +++ /dev/null | |||
@@ -1,165 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s3c2442/s3c2442.c | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C2442 core and lock support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | */ | ||
23 | |||
24 | #include <linux/init.h> | ||
25 | #include <linux/module.h> | ||
26 | #include <linux/kernel.h> | ||
27 | #include <linux/list.h> | ||
28 | #include <linux/errno.h> | ||
29 | #include <linux/err.h> | ||
30 | #include <linux/device.h> | ||
31 | #include <linux/sysdev.h> | ||
32 | #include <linux/interrupt.h> | ||
33 | #include <linux/ioport.h> | ||
34 | #include <linux/mutex.h> | ||
35 | #include <linux/clk.h> | ||
36 | #include <linux/io.h> | ||
37 | |||
38 | #include <mach/hardware.h> | ||
39 | #include <asm/atomic.h> | ||
40 | #include <asm/irq.h> | ||
41 | |||
42 | #include <mach/regs-clock.h> | ||
43 | |||
44 | #include <plat/clock.h> | ||
45 | #include <plat/cpu.h> | ||
46 | |||
47 | /* S3C2442 extended clock support */ | ||
48 | |||
49 | static unsigned long s3c2442_camif_upll_round(struct clk *clk, | ||
50 | unsigned long rate) | ||
51 | { | ||
52 | unsigned long parent_rate = clk_get_rate(clk->parent); | ||
53 | int div; | ||
54 | |||
55 | if (rate > parent_rate) | ||
56 | return parent_rate; | ||
57 | |||
58 | div = parent_rate / rate; | ||
59 | |||
60 | if (div == 3) | ||
61 | return parent_rate / 3; | ||
62 | |||
63 | /* note, we remove the +/- 1 calculations for the divisor */ | ||
64 | |||
65 | div /= 2; | ||
66 | |||
67 | if (div < 1) | ||
68 | div = 1; | ||
69 | else if (div > 16) | ||
70 | div = 16; | ||
71 | |||
72 | return parent_rate / (div * 2); | ||
73 | } | ||
74 | |||
75 | static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate) | ||
76 | { | ||
77 | unsigned long parent_rate = clk_get_rate(clk->parent); | ||
78 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); | ||
79 | |||
80 | rate = s3c2442_camif_upll_round(clk, rate); | ||
81 | |||
82 | camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3; | ||
83 | |||
84 | if (rate == parent_rate) { | ||
85 | camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL; | ||
86 | } else if ((parent_rate / rate) == 3) { | ||
87 | camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; | ||
88 | camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3; | ||
89 | } else { | ||
90 | camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK; | ||
91 | camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; | ||
92 | camdivn |= (((parent_rate / rate) / 2) - 1); | ||
93 | } | ||
94 | |||
95 | __raw_writel(camdivn, S3C2440_CAMDIVN); | ||
96 | |||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | /* Extra S3C2442 clocks */ | ||
101 | |||
102 | static struct clk s3c2442_clk_cam = { | ||
103 | .name = "camif", | ||
104 | .id = -1, | ||
105 | .enable = s3c2410_clkcon_enable, | ||
106 | .ctrlbit = S3C2440_CLKCON_CAMERA, | ||
107 | }; | ||
108 | |||
109 | static struct clk s3c2442_clk_cam_upll = { | ||
110 | .name = "camif-upll", | ||
111 | .id = -1, | ||
112 | .ops = &(struct clk_ops) { | ||
113 | .set_rate = s3c2442_camif_upll_setrate, | ||
114 | .round_rate = s3c2442_camif_upll_round, | ||
115 | }, | ||
116 | }; | ||
117 | |||
118 | static int s3c2442_clk_add(struct sys_device *sysdev) | ||
119 | { | ||
120 | struct clk *clock_upll; | ||
121 | struct clk *clock_h; | ||
122 | struct clk *clock_p; | ||
123 | |||
124 | clock_p = clk_get(NULL, "pclk"); | ||
125 | clock_h = clk_get(NULL, "hclk"); | ||
126 | clock_upll = clk_get(NULL, "upll"); | ||
127 | |||
128 | if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { | ||
129 | printk(KERN_ERR "S3C2442: Failed to get parent clocks\n"); | ||
130 | return -EINVAL; | ||
131 | } | ||
132 | |||
133 | s3c2442_clk_cam.parent = clock_h; | ||
134 | s3c2442_clk_cam_upll.parent = clock_upll; | ||
135 | |||
136 | s3c24xx_register_clock(&s3c2442_clk_cam); | ||
137 | s3c24xx_register_clock(&s3c2442_clk_cam_upll); | ||
138 | |||
139 | clk_disable(&s3c2442_clk_cam); | ||
140 | |||
141 | return 0; | ||
142 | } | ||
143 | |||
144 | static struct sysdev_driver s3c2442_clk_driver = { | ||
145 | .add = s3c2442_clk_add, | ||
146 | }; | ||
147 | |||
148 | static __init int s3c2442_clk_init(void) | ||
149 | { | ||
150 | return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver); | ||
151 | } | ||
152 | |||
153 | arch_initcall(s3c2442_clk_init); | ||
154 | |||
155 | |||
156 | static struct sys_device s3c2442_sysdev = { | ||
157 | .cls = &s3c2442_sysclass, | ||
158 | }; | ||
159 | |||
160 | int __init s3c2442_init(void) | ||
161 | { | ||
162 | printk("S3C2442: Initialising architecture\n"); | ||
163 | |||
164 | return sysdev_register(&s3c2442_sysdev); | ||
165 | } | ||