diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-01-28 07:01:34 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-01-28 08:20:52 -0500 |
commit | 3a38e4be76e86c7b94c36dc8f3ce489987da24e4 (patch) | |
tree | 1b8ce87d0002c28fe9a8615151a28a3b666f5c17 /arch/arm/mach-s3c2442/clock.c | |
parent | c27cb681ac1598352569f75cb19850a12b7ef102 (diff) |
[ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code
Merge together the bits of the S3C2440 and S3C2442 clock code
that can be.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2442/clock.c')
-rw-r--r-- | arch/arm/mach-s3c2442/clock.c | 22 |
1 files changed, 1 insertions, 21 deletions
diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c index 5b9e830ac4d3..2d030d439fe9 100644 --- a/arch/arm/mach-s3c2442/clock.c +++ b/arch/arm/mach-s3c2442/clock.c | |||
@@ -115,14 +115,9 @@ static struct clk s3c2442_clk_cam_upll = { | |||
115 | 115 | ||
116 | static int s3c2442_clk_add(struct sys_device *sysdev) | 116 | static int s3c2442_clk_add(struct sys_device *sysdev) |
117 | { | 117 | { |
118 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); | 118 | struct clk *clock_upll; |
119 | unsigned long clkdivn; | ||
120 | struct clk *clock_h; | 119 | struct clk *clock_h; |
121 | struct clk *clock_p; | 120 | struct clk *clock_p; |
122 | struct clk *clock_upll; | ||
123 | |||
124 | printk("S3C2442: Clock Support, DVS %s\n", | ||
125 | (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); | ||
126 | 121 | ||
127 | clock_p = clk_get(NULL, "pclk"); | 122 | clock_p = clk_get(NULL, "pclk"); |
128 | clock_h = clk_get(NULL, "hclk"); | 123 | clock_h = clk_get(NULL, "hclk"); |
@@ -133,21 +128,6 @@ static int s3c2442_clk_add(struct sys_device *sysdev) | |||
133 | return -EINVAL; | 128 | return -EINVAL; |
134 | } | 129 | } |
135 | 130 | ||
136 | /* check rate of UPLL, and if it is near 96MHz, then change | ||
137 | * to using half the UPLL rate for the system */ | ||
138 | |||
139 | if (clk_get_rate(clock_upll) > (94 * MHZ)) { | ||
140 | clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; | ||
141 | |||
142 | mutex_lock(&clocks_mutex); | ||
143 | |||
144 | clkdivn = __raw_readl(S3C2410_CLKDIVN); | ||
145 | clkdivn |= S3C2440_CLKDIVN_UCLK; | ||
146 | __raw_writel(clkdivn, S3C2410_CLKDIVN); | ||
147 | |||
148 | mutex_unlock(&clocks_mutex); | ||
149 | } | ||
150 | |||
151 | s3c2442_clk_cam.parent = clock_h; | 131 | s3c2442_clk_cam.parent = clock_h; |
152 | s3c2442_clk_cam_upll.parent = clock_upll; | 132 | s3c2442_clk_cam_upll.parent = clock_upll; |
153 | 133 | ||