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authorThomas Gleixner <tglx@linutronix.de>2011-03-24 08:35:09 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-03-29 08:47:58 -0400
commitf38c02f3b338651e145aac2889ba976baf6b28b3 (patch)
tree30cfbf42ccff4a9dc26d95e9058ec76f5fde78bb /arch/arm/mach-s3c2440
parent9323f26186403433293e87e717a7785f74f75d80 (diff)
arm: Fold irq_set_chip/irq_set_handler
Use irq_set_chip_and_handler() instead. Converted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mach-s3c2440')
-rw-r--r--arch/arm/mach-s3c2440/irq.c8
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-irq.c12
2 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 0c564b149a46..eb1cc0f0705e 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -100,13 +100,13 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
100 100
101 /* add new chained handler for wdt, ac7 */ 101 /* add new chained handler for wdt, ac7 */
102 102
103 irq_set_chip(IRQ_WDT, &s3c_irq_level_chip); 103 irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
104 irq_set_handler(IRQ_WDT, handle_level_irq); 104 handle_level_irq);
105 irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); 105 irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
106 106
107 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { 107 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
108 irq_set_chip(irqno, &s3c_irq_wdtac97); 108 irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
109 irq_set_handler(irqno, handle_level_irq); 109 handle_level_irq);
110 set_irq_flags(irqno, IRQF_VALID); 110 set_irq_flags(irqno, IRQF_VALID);
111 } 111 }
112 112
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index 5a48881c4508..de07c2feaa32 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -95,19 +95,19 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
95{ 95{
96 unsigned int irqno; 96 unsigned int irqno;
97 97
98 irq_set_chip(IRQ_NFCON, &s3c_irq_level_chip); 98 irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
99 irq_set_handler(IRQ_NFCON, handle_level_irq); 99 handle_level_irq);
100 set_irq_flags(IRQ_NFCON, IRQF_VALID); 100 set_irq_flags(IRQ_NFCON, IRQF_VALID);
101 101
102 /* add chained handler for camera */ 102 /* add chained handler for camera */
103 103
104 irq_set_chip(IRQ_CAM, &s3c_irq_level_chip); 104 irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
105 irq_set_handler(IRQ_CAM, handle_level_irq); 105 handle_level_irq);
106 irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam); 106 irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
107 107
108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { 108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
109 irq_set_chip(irqno, &s3c_irq_cam); 109 irq_set_chip_and_handler(irqno, &s3c_irq_cam,
110 irq_set_handler(irqno, handle_level_irq); 110 handle_level_irq);
111 set_irq_flags(irqno, IRQF_VALID); 111 set_irq_flags(irqno, IRQF_VALID);
112 } 112 }
113 113