diff options
author | Thomas Abraham <thomas.abraham@linaro.org> | 2011-10-24 05:47:51 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-12-22 20:06:57 -0500 |
commit | afba7f91e64025748a2cfec181e5a910fd0dee0e (patch) | |
tree | 37872a38eea179a6adb9eacbd5334b4352043413 /arch/arm/mach-s3c2440 | |
parent | 5f5a7a5578c5885201cf9c85856f023fe8b81765 (diff) |
ARM: SAMSUNG: remove struct 's3c24xx_uart_clksrc' and all uses of it
With clkdev based clock lookup added to samsung serial driver, the use
of 'struct s3c24xx_uart_clksrc' to supply clock names in platform
data is removed from all the Samsung platform code.
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Ramax Lo <ramaxlo@gmail.com>
Cc: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c2440')
-rw-r--r-- | arch/arm/mach-s3c2440/mach-anubis.c | 22 | ||||
-rw-r--r-- | arch/arm/mach-s3c2440/mach-at2440evb.c | 22 | ||||
-rw-r--r-- | arch/arm/mach-s3c2440/mach-osiris.c | 24 | ||||
-rw-r--r-- | arch/arm/mach-s3c2440/mach-rx1950.c | 18 | ||||
-rw-r--r-- | arch/arm/mach-s3c2440/mach-rx3715.c | 19 |
5 files changed, 13 insertions, 92 deletions
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 74f92fc3fd04..d8f36c0a16ad 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c | |||
@@ -96,22 +96,6 @@ static struct map_desc anubis_iodesc[] __initdata = { | |||
96 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | 96 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB |
97 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | 97 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE |
98 | 98 | ||
99 | static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = { | ||
100 | [0] = { | ||
101 | .name = "uclk", | ||
102 | .divisor = 1, | ||
103 | .min_baud = 0, | ||
104 | .max_baud = 0, | ||
105 | }, | ||
106 | [1] = { | ||
107 | .name = "pclk", | ||
108 | .divisor = 1, | ||
109 | .min_baud = 0, | ||
110 | .max_baud = 0, | ||
111 | } | ||
112 | }; | ||
113 | |||
114 | |||
115 | static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { | 99 | static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { |
116 | [0] = { | 100 | [0] = { |
117 | .hwport = 0, | 101 | .hwport = 0, |
@@ -119,8 +103,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { | |||
119 | .ucon = UCON, | 103 | .ucon = UCON, |
120 | .ulcon = ULCON, | 104 | .ulcon = ULCON, |
121 | .ufcon = UFCON, | 105 | .ufcon = UFCON, |
122 | .clocks = anubis_serial_clocks, | 106 | .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, |
123 | .clocks_size = ARRAY_SIZE(anubis_serial_clocks), | ||
124 | }, | 107 | }, |
125 | [1] = { | 108 | [1] = { |
126 | .hwport = 2, | 109 | .hwport = 2, |
@@ -128,8 +111,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { | |||
128 | .ucon = UCON, | 111 | .ucon = UCON, |
129 | .ulcon = ULCON, | 112 | .ulcon = ULCON, |
130 | .ufcon = UFCON, | 113 | .ufcon = UFCON, |
131 | .clocks = anubis_serial_clocks, | 114 | .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, |
132 | .clocks_size = ARRAY_SIZE(anubis_serial_clocks), | ||
133 | }, | 115 | }, |
134 | }; | 116 | }; |
135 | 117 | ||
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index 38887ee0c784..aa86ca8fa1e9 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c | |||
@@ -57,22 +57,6 @@ static struct map_desc at2440evb_iodesc[] __initdata = { | |||
57 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) | 57 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) |
58 | #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) | 58 | #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) |
59 | 59 | ||
60 | static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = { | ||
61 | [0] = { | ||
62 | .name = "uclk", | ||
63 | .divisor = 1, | ||
64 | .min_baud = 0, | ||
65 | .max_baud = 0, | ||
66 | }, | ||
67 | [1] = { | ||
68 | .name = "pclk", | ||
69 | .divisor = 1, | ||
70 | .min_baud = 0, | ||
71 | .max_baud = 0, | ||
72 | } | ||
73 | }; | ||
74 | |||
75 | |||
76 | static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { | 60 | static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { |
77 | [0] = { | 61 | [0] = { |
78 | .hwport = 0, | 62 | .hwport = 0, |
@@ -80,8 +64,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { | |||
80 | .ucon = UCON, | 64 | .ucon = UCON, |
81 | .ulcon = ULCON, | 65 | .ulcon = ULCON, |
82 | .ufcon = UFCON, | 66 | .ufcon = UFCON, |
83 | .clocks = at2440evb_serial_clocks, | 67 | .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, |
84 | .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks), | ||
85 | }, | 68 | }, |
86 | [1] = { | 69 | [1] = { |
87 | .hwport = 1, | 70 | .hwport = 1, |
@@ -89,8 +72,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { | |||
89 | .ucon = UCON, | 72 | .ucon = UCON, |
90 | .ulcon = ULCON, | 73 | .ulcon = ULCON, |
91 | .ufcon = UFCON, | 74 | .ufcon = UFCON, |
92 | .clocks = at2440evb_serial_clocks, | 75 | .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, |
93 | .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks), | ||
94 | }, | 76 | }, |
95 | }; | 77 | }; |
96 | 78 | ||
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index dc142ebf8cba..d7e47b2b6ec9 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c | |||
@@ -100,21 +100,6 @@ static struct map_desc osiris_iodesc[] __initdata = { | |||
100 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | 100 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB |
101 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | 101 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE |
102 | 102 | ||
103 | static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = { | ||
104 | [0] = { | ||
105 | .name = "uclk", | ||
106 | .divisor = 1, | ||
107 | .min_baud = 0, | ||
108 | .max_baud = 0, | ||
109 | }, | ||
110 | [1] = { | ||
111 | .name = "pclk", | ||
112 | .divisor = 1, | ||
113 | .min_baud = 0, | ||
114 | .max_baud = 0, | ||
115 | } | ||
116 | }; | ||
117 | |||
118 | static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { | 103 | static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { |
119 | [0] = { | 104 | [0] = { |
120 | .hwport = 0, | 105 | .hwport = 0, |
@@ -122,8 +107,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { | |||
122 | .ucon = UCON, | 107 | .ucon = UCON, |
123 | .ulcon = ULCON, | 108 | .ulcon = ULCON, |
124 | .ufcon = UFCON, | 109 | .ufcon = UFCON, |
125 | .clocks = osiris_serial_clocks, | 110 | .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, |
126 | .clocks_size = ARRAY_SIZE(osiris_serial_clocks), | ||
127 | }, | 111 | }, |
128 | [1] = { | 112 | [1] = { |
129 | .hwport = 1, | 113 | .hwport = 1, |
@@ -131,8 +115,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { | |||
131 | .ucon = UCON, | 115 | .ucon = UCON, |
132 | .ulcon = ULCON, | 116 | .ulcon = ULCON, |
133 | .ufcon = UFCON, | 117 | .ufcon = UFCON, |
134 | .clocks = osiris_serial_clocks, | 118 | .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, |
135 | .clocks_size = ARRAY_SIZE(osiris_serial_clocks), | ||
136 | }, | 119 | }, |
137 | [2] = { | 120 | [2] = { |
138 | .hwport = 2, | 121 | .hwport = 2, |
@@ -140,8 +123,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { | |||
140 | .ucon = UCON, | 123 | .ucon = UCON, |
141 | .ulcon = ULCON, | 124 | .ulcon = ULCON, |
142 | .ufcon = UFCON, | 125 | .ufcon = UFCON, |
143 | .clocks = osiris_serial_clocks, | 126 | .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, |
144 | .clocks_size = ARRAY_SIZE(osiris_serial_clocks), | ||
145 | } | 127 | } |
146 | }; | 128 | }; |
147 | 129 | ||
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index 094c4bff7fe4..4267cd56bfe7 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c | |||
@@ -68,15 +68,6 @@ | |||
68 | static struct map_desc rx1950_iodesc[] __initdata = { | 68 | static struct map_desc rx1950_iodesc[] __initdata = { |
69 | }; | 69 | }; |
70 | 70 | ||
71 | static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = { | ||
72 | [0] = { | ||
73 | .name = "fclk_n", | ||
74 | .divisor = 1, | ||
75 | .min_baud = 0, | ||
76 | .max_baud = 0, | ||
77 | }, | ||
78 | }; | ||
79 | |||
80 | static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { | 71 | static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { |
81 | [0] = { | 72 | [0] = { |
82 | .hwport = 0, | 73 | .hwport = 0, |
@@ -84,8 +75,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { | |||
84 | .ucon = 0x3c5, | 75 | .ucon = 0x3c5, |
85 | .ulcon = 0x03, | 76 | .ulcon = 0x03, |
86 | .ufcon = 0x51, | 77 | .ufcon = 0x51, |
87 | .clocks = rx1950_serial_clocks, | 78 | .clk_sel = S3C2410_UCON_CLKSEL3, |
88 | .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), | ||
89 | }, | 79 | }, |
90 | [1] = { | 80 | [1] = { |
91 | .hwport = 1, | 81 | .hwport = 1, |
@@ -93,8 +83,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { | |||
93 | .ucon = 0x3c5, | 83 | .ucon = 0x3c5, |
94 | .ulcon = 0x03, | 84 | .ulcon = 0x03, |
95 | .ufcon = 0x51, | 85 | .ufcon = 0x51, |
96 | .clocks = rx1950_serial_clocks, | 86 | .clk_sel = S3C2410_UCON_CLKSEL3, |
97 | .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), | ||
98 | }, | 87 | }, |
99 | /* IR port */ | 88 | /* IR port */ |
100 | [2] = { | 89 | [2] = { |
@@ -103,8 +92,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { | |||
103 | .ucon = 0x3c5, | 92 | .ucon = 0x3c5, |
104 | .ulcon = 0x43, | 93 | .ulcon = 0x43, |
105 | .ufcon = 0xf1, | 94 | .ufcon = 0xf1, |
106 | .clocks = rx1950_serial_clocks, | 95 | .clk_sel = S3C2410_UCON_CLKSEL3, |
107 | .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), | ||
108 | }, | 96 | }, |
109 | }; | 97 | }; |
110 | 98 | ||
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index f934f5b88a4a..3d5e2e67971e 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c | |||
@@ -67,16 +67,6 @@ static struct map_desc rx3715_iodesc[] __initdata = { | |||
67 | }, | 67 | }, |
68 | }; | 68 | }; |
69 | 69 | ||
70 | |||
71 | static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = { | ||
72 | [0] = { | ||
73 | .name = "fclk_n", | ||
74 | .divisor = 1, | ||
75 | .min_baud = 0, | ||
76 | .max_baud = 0, | ||
77 | } | ||
78 | }; | ||
79 | |||
80 | static struct s3c2410_uartcfg rx3715_uartcfgs[] = { | 70 | static struct s3c2410_uartcfg rx3715_uartcfgs[] = { |
81 | [0] = { | 71 | [0] = { |
82 | .hwport = 0, | 72 | .hwport = 0, |
@@ -84,8 +74,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { | |||
84 | .ucon = 0x3c5, | 74 | .ucon = 0x3c5, |
85 | .ulcon = 0x03, | 75 | .ulcon = 0x03, |
86 | .ufcon = 0x51, | 76 | .ufcon = 0x51, |
87 | .clocks = rx3715_serial_clocks, | 77 | .clk_sel = S3C2410_UCON_CLKSEL3, |
88 | .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), | ||
89 | }, | 78 | }, |
90 | [1] = { | 79 | [1] = { |
91 | .hwport = 1, | 80 | .hwport = 1, |
@@ -93,8 +82,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { | |||
93 | .ucon = 0x3c5, | 82 | .ucon = 0x3c5, |
94 | .ulcon = 0x03, | 83 | .ulcon = 0x03, |
95 | .ufcon = 0x00, | 84 | .ufcon = 0x00, |
96 | .clocks = rx3715_serial_clocks, | 85 | .clk_sel = S3C2410_UCON_CLKSEL3, |
97 | .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), | ||
98 | }, | 86 | }, |
99 | /* IR port */ | 87 | /* IR port */ |
100 | [2] = { | 88 | [2] = { |
@@ -103,8 +91,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { | |||
103 | .ucon = 0x3c5, | 91 | .ucon = 0x3c5, |
104 | .ulcon = 0x43, | 92 | .ulcon = 0x43, |
105 | .ufcon = 0x51, | 93 | .ufcon = 0x51, |
106 | .clocks = rx3715_serial_clocks, | 94 | .clk_sel = S3C2410_UCON_CLKSEL3, |
107 | .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), | ||
108 | } | 95 | } |
109 | }; | 96 | }; |
110 | 97 | ||