diff options
author | Ben Dooks <ben-linux@fluff.org> | 2010-03-04 18:14:44 -0500 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-03-04 18:14:44 -0500 |
commit | 8997de30adf5d11e9c807f1d89a894ffed60616b (patch) | |
tree | c3996b5d47129af57ba2247d43299fe97ef58834 /arch/arm/mach-s3c2440 | |
parent | d608c738bb8fb37e5fbfcdef9c566764f2fea086 (diff) |
ARM: S3C2440: Fix plat-s3c24xx move of s3c2440/s3c2442 support
Commit 58bac7b8ded70c39bcd5f7037091051c277618aa failed to move the two
PLL files s3c2440-pll-12000000.c and s3c2440-pll-16934400.c, so place
these in arch/arm/mach-s3c2440 to fix this commit up.
As a note, these are not built by the default configuration and thus the
failure to move wasn't spotted until much later.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c2440')
-rw-r--r-- | arch/arm/mach-s3c2440/s3c2440-pll-12000000.c | 97 | ||||
-rw-r--r-- | arch/arm/mach-s3c2440/s3c2440-pll-16934400.c | 127 |
2 files changed, 224 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c new file mode 100644 index 000000000000..f105d5e8c477 --- /dev/null +++ b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c | |||
@@ -0,0 +1,97 @@ | |||
1 | /* arch/arm/mach-s3c2440/s3c2440-pll-12000000.c | ||
2 | * | ||
3 | * Copyright (c) 2006-2007 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * Vincent Sanders <vince@arm.linux.org.uk> | ||
7 | * | ||
8 | * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal) | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/types.h> | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/sysdev.h> | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/err.h> | ||
20 | |||
21 | #include <plat/cpu.h> | ||
22 | #include <plat/cpu-freq-core.h> | ||
23 | |||
24 | static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = { | ||
25 | { .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */ | ||
26 | { .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */ | ||
27 | { .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */ | ||
28 | { .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */ | ||
29 | { .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */ | ||
30 | { .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */ | ||
31 | { .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */ | ||
32 | { .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */ | ||
33 | { .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */ | ||
34 | { .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */ | ||
35 | { .frequency = 190000000, .index = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */ | ||
36 | { .frequency = 200000000, .index = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */ | ||
37 | { .frequency = 210000000, .index = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */ | ||
38 | { .frequency = 220000000, .index = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */ | ||
39 | { .frequency = 230000000, .index = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */ | ||
40 | { .frequency = 240000000, .index = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */ | ||
41 | { .frequency = 300000000, .index = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */ | ||
42 | { .frequency = 310000000, .index = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */ | ||
43 | { .frequency = 320000000, .index = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */ | ||
44 | { .frequency = 330000000, .index = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */ | ||
45 | { .frequency = 340000000, .index = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */ | ||
46 | { .frequency = 350000000, .index = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */ | ||
47 | { .frequency = 360000000, .index = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */ | ||
48 | { .frequency = 370000000, .index = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */ | ||
49 | { .frequency = 380000000, .index = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */ | ||
50 | { .frequency = 390000000, .index = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */ | ||
51 | { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ | ||
52 | }; | ||
53 | |||
54 | static int s3c2440_plls12_add(struct sys_device *dev) | ||
55 | { | ||
56 | struct clk *xtal_clk; | ||
57 | unsigned long xtal; | ||
58 | |||
59 | xtal_clk = clk_get(NULL, "xtal"); | ||
60 | if (IS_ERR(xtal_clk)) | ||
61 | return PTR_ERR(xtal_clk); | ||
62 | |||
63 | xtal = clk_get_rate(xtal_clk); | ||
64 | clk_put(xtal_clk); | ||
65 | |||
66 | if (xtal == 12000000) { | ||
67 | printk(KERN_INFO "Using PLL table for 12MHz crystal\n"); | ||
68 | return s3c_plltab_register(s3c2440_plls_12, | ||
69 | ARRAY_SIZE(s3c2440_plls_12)); | ||
70 | } | ||
71 | |||
72 | return 0; | ||
73 | } | ||
74 | |||
75 | static struct sysdev_driver s3c2440_plls12_drv = { | ||
76 | .add = s3c2440_plls12_add, | ||
77 | }; | ||
78 | |||
79 | static int __init s3c2440_pll_12mhz(void) | ||
80 | { | ||
81 | return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_plls12_drv); | ||
82 | |||
83 | } | ||
84 | |||
85 | arch_initcall(s3c2440_pll_12mhz); | ||
86 | |||
87 | static struct sysdev_driver s3c2442_plls12_drv = { | ||
88 | .add = s3c2440_plls12_add, | ||
89 | }; | ||
90 | |||
91 | static int __init s3c2442_pll_12mhz(void) | ||
92 | { | ||
93 | return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv); | ||
94 | |||
95 | } | ||
96 | |||
97 | arch_initcall(s3c2442_pll_12mhz); | ||
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c new file mode 100644 index 000000000000..c8a8f90ef382 --- /dev/null +++ b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c | |||
@@ -0,0 +1,127 @@ | |||
1 | /* arch/arm/mach-s3c2440/s3c2440-pll-16934400.c | ||
2 | * | ||
3 | * Copyright (c) 2006-2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * Vincent Sanders <vince@arm.linux.org.uk> | ||
7 | * | ||
8 | * S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal) | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/types.h> | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/sysdev.h> | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/err.h> | ||
20 | |||
21 | #include <plat/cpu.h> | ||
22 | #include <plat/cpu-freq-core.h> | ||
23 | |||
24 | static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = { | ||
25 | { .frequency = 78019200, .index = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */ | ||
26 | { .frequency = 84067200, .index = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */ | ||
27 | { .frequency = 90115200, .index = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */ | ||
28 | { .frequency = 96163200, .index = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */ | ||
29 | { .frequency = 102135600, .index = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */ | ||
30 | { .frequency = 108259200, .index = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */ | ||
31 | { .frequency = 114307200, .index = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */ | ||
32 | { .frequency = 120234240, .index = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */ | ||
33 | { .frequency = 126161280, .index = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */ | ||
34 | { .frequency = 132088320, .index = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */ | ||
35 | { .frequency = 138015360, .index = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */ | ||
36 | { .frequency = 144789120, .index = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */ | ||
37 | { .frequency = 150100363, .index = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */ | ||
38 | { .frequency = 156038400, .index = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */ | ||
39 | { .frequency = 162086400, .index = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */ | ||
40 | { .frequency = 168134400, .index = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */ | ||
41 | { .frequency = 174048000, .index = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */ | ||
42 | { .frequency = 180230400, .index = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */ | ||
43 | { .frequency = 186278400, .index = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */ | ||
44 | { .frequency = 192326400, .index = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */ | ||
45 | { .frequency = 198132480, .index = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */ | ||
46 | { .frequency = 204271200, .index = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */ | ||
47 | { .frequency = 210268800, .index = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */ | ||
48 | { .frequency = 216518400, .index = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */ | ||
49 | { .frequency = 222264000, .index = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */ | ||
50 | { .frequency = 228614400, .index = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */ | ||
51 | { .frequency = 234259200, .index = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */ | ||
52 | { .frequency = 240468480, .index = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */ | ||
53 | { .frequency = 246960000, .index = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */ | ||
54 | { .frequency = 252322560, .index = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */ | ||
55 | { .frequency = 258249600, .index = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */ | ||
56 | { .frequency = 264176640, .index = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */ | ||
57 | { .frequency = 270950400, .index = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */ | ||
58 | { .frequency = 276030720, .index = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */ | ||
59 | { .frequency = 282240000, .index = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */ | ||
60 | { .frequency = 289578240, .index = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */ | ||
61 | { .frequency = 294235200, .index = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */ | ||
62 | { .frequency = 300200727, .index = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */ | ||
63 | { .frequency = 306358690, .index = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */ | ||
64 | { .frequency = 312076800, .index = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */ | ||
65 | { .frequency = 318366720, .index = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */ | ||
66 | { .frequency = 324172800, .index = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */ | ||
67 | { .frequency = 330220800, .index = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */ | ||
68 | { .frequency = 336268800, .index = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */ | ||
69 | { .frequency = 342074880, .index = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */ | ||
70 | { .frequency = 348096000, .index = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */ | ||
71 | { .frequency = 355622400, .index = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */ | ||
72 | { .frequency = 360460800, .index = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */ | ||
73 | { .frequency = 366206400, .index = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */ | ||
74 | { .frequency = 372556800, .index = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */ | ||
75 | { .frequency = 378201600, .index = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */ | ||
76 | { .frequency = 384652800, .index = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */ | ||
77 | { .frequency = 391608000, .index = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */ | ||
78 | { .frequency = 396264960, .index = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */ | ||
79 | { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ | ||
80 | }; | ||
81 | |||
82 | static int s3c2440_plls169344_add(struct sys_device *dev) | ||
83 | { | ||
84 | struct clk *xtal_clk; | ||
85 | unsigned long xtal; | ||
86 | |||
87 | xtal_clk = clk_get(NULL, "xtal"); | ||
88 | if (IS_ERR(xtal_clk)) | ||
89 | return PTR_ERR(xtal_clk); | ||
90 | |||
91 | xtal = clk_get_rate(xtal_clk); | ||
92 | clk_put(xtal_clk); | ||
93 | |||
94 | if (xtal == 169344000) { | ||
95 | printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n"); | ||
96 | return s3c_plltab_register(s3c2440_plls_169344, | ||
97 | ARRAY_SIZE(s3c2440_plls_169344)); | ||
98 | } | ||
99 | |||
100 | return 0; | ||
101 | } | ||
102 | |||
103 | static struct sysdev_driver s3c2440_plls169344_drv = { | ||
104 | .add = s3c2440_plls169344_add, | ||
105 | }; | ||
106 | |||
107 | static int __init s3c2440_pll_16934400(void) | ||
108 | { | ||
109 | return sysdev_driver_register(&s3c2440_sysclass, | ||
110 | &s3c2440_plls169344_drv); | ||
111 | |||
112 | } | ||
113 | |||
114 | arch_initcall(s3c2440_pll_16934400); | ||
115 | |||
116 | static struct sysdev_driver s3c2442_plls169344_drv = { | ||
117 | .add = s3c2440_plls169344_add, | ||
118 | }; | ||
119 | |||
120 | static int __init s3c2442_pll_16934400(void) | ||
121 | { | ||
122 | return sysdev_driver_register(&s3c2442_sysclass, | ||
123 | &s3c2442_plls169344_drv); | ||
124 | |||
125 | } | ||
126 | |||
127 | arch_initcall(s3c2442_pll_16934400); | ||