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authorBen Dooks <ben-linux@fluff.org>2007-02-11 12:31:01 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-11 12:36:09 -0500
commita21765a70ec06be175d3997320a83fa66fcc8955 (patch)
tree24bdbf437a9bd5b7c1af05898f5aa25dccf67fe9 /arch/arm/mach-s3c2440
parentd19494b187b20e363f9b434b9ceab4159ac88324 (diff)
[ARM] 4157/2: S3C24XX: move arch/arch/mach-s3c2410 into cpu components
The following patch and script moves the arch/arm/mach-s3c2410 directory into arch/arm/plat-s3c24xx for the generic core code and inti arch/arm/mach-s3c{cpu} for the cpu/machine support files Include directory include/asm-arm/plat-s3c24xx is added for the core include files. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2440')
-rw-r--r--arch/arm/mach-s3c2440/Kconfig71
-rw-r--r--arch/arm/mach-s3c2440/Makefile23
-rw-r--r--arch/arm/mach-s3c2440/clock.c170
-rw-r--r--arch/arm/mach-s3c2440/dma.c165
-rw-r--r--arch/arm/mach-s3c2440/dsc.c54
-rw-r--r--arch/arm/mach-s3c2440/irq.c130
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c325
-rw-r--r--arch/arm/mach-s3c2440/mach-nexcoder.c158
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c303
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c244
-rw-r--r--arch/arm/mach-s3c2440/mach-smdk2440.c208
-rw-r--r--arch/arm/mach-s3c2440/s3c2440.c52
12 files changed, 1903 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
new file mode 100644
index 000000000000..e3bfda098c0f
--- /dev/null
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -0,0 +1,71 @@
1# arch/arm/mach-s3c2440/Kconfig
2#
3# Copyright 2007 Simtec Electronics
4#
5# Licensed under GPLv2
6
7config CPU_S3C2440
8 bool
9 depends on ARCH_S3C2410
10 select S3C2410_CLOCK
11 select S3C2410_PM if PM
12 select S3C2410_GPIO
13 select S3C2440_DMA if S3C2410_DMA
14 select CPU_S3C244X
15 help
16 Support for S3C2440 Samsung Mobile CPU based systems.
17
18config S3C2440_DMA
19 bool
20 depends on ARCH_S3C2410 && CPU_S3C24405B
21 help
22 Support for S3C2440 specific DMA code5A
23
24
25menu "S3C2440 Machines"
26
27config MACH_ANUBIS
28 bool "Simtec Electronics ANUBIS"
29 select CPU_S3C2440
30 select PM_SIMTEC if PM
31 help
32 Say Y here if you are using the Simtec Electronics ANUBIS
33 development system
34
35config MACH_OSIRIS
36 bool "Simtec IM2440D20 (OSIRIS) module"
37 select CPU_S3C2440
38 select PM_SIMTEC if PM
39 help
40 Say Y here if you are using the Simtec IM2440D20 module, also
41 known as the Osiris.
42
43config MACH_RX3715
44 bool "HP iPAQ rx3715"
45 select CPU_S3C2440
46 select PM_H1940 if PM
47 help
48 Say Y here if you are using the HP iPAQ rx3715.
49
50config ARCH_S3C2440
51 bool "SMDK2440"
52 select CPU_S3C2440
53 select MACH_SMDK
54 help
55 Say Y here if you are using the SMDK2440.
56
57config MACH_NEXCODER_2440
58 bool "NexVision NEXCODER 2440 Light Board"
59 select CPU_S3C2440
60 help
61 Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
62
63config SMDK2440_CPU2440
64 bool "SMDK2440 with S3C2440 CPU module"
65 depends on ARCH_S3C2440
66 default y if ARCH_S3C2440
67 select CPU_S3C2440
68
69
70endmenu
71
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
new file mode 100644
index 000000000000..c81ed6248dcb
--- /dev/null
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -0,0 +1,23 @@
1# arch/arm/mach-s3c2440/Makefile
2#
3# Copyright 2007 Simtec Electronics
4#
5# Licensed under GPLv2
6
7obj-y :=
8obj-m :=
9obj-n :=
10obj- :=
11
12obj-$(CONFIG_CPU_S3C2440) += s3c2440.o dsc.o
13obj-$(CONFIG_CPU_S3C2440) += irq.o
14obj-$(CONFIG_CPU_S3C2440) += clock.o
15obj-$(CONFIG_S3C2440_DMA) += dma.o
16
17# Machine support
18
19obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o
20obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o
21obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o
22obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
23obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
new file mode 100644
index 000000000000..79e2ea4adaf3
--- /dev/null
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -0,0 +1,170 @@
1/* linux/arch/arm/mach-s3c2440/clock.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440 Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/mutex.h>
35#include <linux/clk.h>
36
37#include <asm/hardware.h>
38#include <asm/atomic.h>
39#include <asm/irq.h>
40#include <asm/io.h>
41
42#include <asm/arch/regs-clock.h>
43
44#include <asm/plat-s3c24xx/clock.h>
45#include <asm/plat-s3c24xx/cpu.h>
46
47/* S3C2440 extended clock support */
48
49static unsigned long s3c2440_camif_upll_round(struct clk *clk,
50 unsigned long rate)
51{
52 unsigned long parent_rate = clk_get_rate(clk->parent);
53 int div;
54
55 if (rate > parent_rate)
56 return parent_rate;
57
58 /* note, we remove the +/- 1 calculations for the divisor */
59
60 div = (parent_rate / rate) / 2;
61
62 if (div < 1)
63 div = 1;
64 else if (div > 16)
65 div = 16;
66
67 return parent_rate / (div * 2);
68}
69
70static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
71{
72 unsigned long parent_rate = clk_get_rate(clk->parent);
73 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
74
75 rate = s3c2440_camif_upll_round(clk, rate);
76
77 camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
78
79 if (rate != parent_rate) {
80 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
81 camdivn |= (((parent_rate / rate) / 2) - 1);
82 }
83
84 __raw_writel(camdivn, S3C2440_CAMDIVN);
85
86 return 0;
87}
88
89/* Extra S3C2440 clocks */
90
91static struct clk s3c2440_clk_cam = {
92 .name = "camif",
93 .id = -1,
94 .enable = s3c2410_clkcon_enable,
95 .ctrlbit = S3C2440_CLKCON_CAMERA,
96};
97
98static struct clk s3c2440_clk_cam_upll = {
99 .name = "camif-upll",
100 .id = -1,
101 .set_rate = s3c2440_camif_upll_setrate,
102 .round_rate = s3c2440_camif_upll_round,
103};
104
105static struct clk s3c2440_clk_ac97 = {
106 .name = "ac97",
107 .id = -1,
108 .enable = s3c2410_clkcon_enable,
109 .ctrlbit = S3C2440_CLKCON_CAMERA,
110};
111
112static int s3c2440_clk_add(struct sys_device *sysdev)
113{
114 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
115 unsigned long clkdivn;
116 struct clk *clock_h;
117 struct clk *clock_p;
118 struct clk *clock_upll;
119
120 printk("S3C2440: Clock Support, DVS %s\n",
121 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
122
123 clock_p = clk_get(NULL, "pclk");
124 clock_h = clk_get(NULL, "hclk");
125 clock_upll = clk_get(NULL, "upll");
126
127 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
128 printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
129 return -EINVAL;
130 }
131
132 /* check rate of UPLL, and if it is near 96MHz, then change
133 * to using half the UPLL rate for the system */
134
135 if (clk_get_rate(clock_upll) > (94 * MHZ)) {
136 clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
137
138 mutex_lock(&clocks_mutex);
139
140 clkdivn = __raw_readl(S3C2410_CLKDIVN);
141 clkdivn |= S3C2440_CLKDIVN_UCLK;
142 __raw_writel(clkdivn, S3C2410_CLKDIVN);
143
144 mutex_unlock(&clocks_mutex);
145 }
146
147 s3c2440_clk_cam.parent = clock_h;
148 s3c2440_clk_ac97.parent = clock_p;
149 s3c2440_clk_cam_upll.parent = clock_upll;
150
151 s3c24xx_register_clock(&s3c2440_clk_ac97);
152 s3c24xx_register_clock(&s3c2440_clk_cam);
153 s3c24xx_register_clock(&s3c2440_clk_cam_upll);
154
155 clk_disable(&s3c2440_clk_ac97);
156 clk_disable(&s3c2440_clk_cam);
157
158 return 0;
159}
160
161static struct sysdev_driver s3c2440_clk_driver = {
162 .add = s3c2440_clk_add,
163};
164
165static __init int s3c24xx_clk_driver(void)
166{
167 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
168}
169
170arch_initcall(s3c24xx_clk_driver);
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
new file mode 100644
index 000000000000..8e51137620f2
--- /dev/null
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -0,0 +1,165 @@
1/* linux/arch/arm/mach-s3c2440/dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2440 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18#include <linux/serial_core.h>
19
20#include <asm/dma.h>
21#include <asm/arch/dma.h>
22#include <asm/plat-s3c24xx/dma.h>
23
24#include <asm/plat-s3c24xx/cpu.h>
25
26#include <asm/arch/regs-serial.h>
27#include <asm/arch/regs-gpio.h>
28#include <asm/arch/regs-ac97.h>
29#include <asm/arch/regs-mem.h>
30#include <asm/arch/regs-lcd.h>
31#include <asm/arch/regs-sdi.h>
32#include <asm/arch/regs-iis.h>
33#include <asm/arch/regs-spi.h>
34
35static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
36 [DMACH_XD0] = {
37 .name = "xdreq0",
38 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
39 },
40 [DMACH_XD1] = {
41 .name = "xdreq1",
42 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
43 },
44 [DMACH_SDI] = {
45 .name = "sdi",
46 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
47 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
48 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
49 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
50 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
51 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
52 },
53 [DMACH_SPI0] = {
54 .name = "spi0",
55 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
56 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
57 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
58 },
59 [DMACH_SPI1] = {
60 .name = "spi1",
61 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
62 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
63 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
64 },
65 [DMACH_UART0] = {
66 .name = "uart0",
67 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
68 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
69 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
70 },
71 [DMACH_UART1] = {
72 .name = "uart1",
73 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
74 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
75 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
76 },
77 [DMACH_UART2] = {
78 .name = "uart2",
79 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
80 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
81 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
82 },
83 [DMACH_TIMER] = {
84 .name = "timer",
85 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
86 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
87 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
88 },
89 [DMACH_I2S_IN] = {
90 .name = "i2s-sdi",
91 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
92 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
93 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
94 },
95 [DMACH_I2S_OUT] = {
96 .name = "i2s-sdo",
97 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
98 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
99 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
100 },
101 [DMACH_PCM_IN] = {
102 .name = "pcm-in",
103 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
104 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
105 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
106 },
107 [DMACH_PCM_OUT] = {
108 .name = "pcm-out",
109 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
110 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
111 .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
112 },
113 [DMACH_MIC_IN] = {
114 .name = "mic-in",
115 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
116 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
117 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
118 },
119 [DMACH_USB_EP1] = {
120 .name = "usb-ep1",
121 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
122 },
123 [DMACH_USB_EP2] = {
124 .name = "usb-ep2",
125 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
126 },
127 [DMACH_USB_EP3] = {
128 .name = "usb-ep3",
129 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
130 },
131 [DMACH_USB_EP4] = {
132 .name = "usb-ep4",
133 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
134 },
135};
136
137static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
138 struct s3c24xx_dma_map *map)
139{
140 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
141}
142
143static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
144 .select = s3c2440_dma_select,
145 .dcon_mask = 7 << 24,
146 .map = s3c2440_dma_mappings,
147 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
148};
149
150static int s3c2440_dma_add(struct sys_device *sysdev)
151{
152 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
153}
154
155static struct sysdev_driver s3c2440_dma_driver = {
156 .add = s3c2440_dma_add,
157};
158
159static int __init s3c2440_dma_init(void)
160{
161 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver);
162}
163
164arch_initcall(s3c2440_dma_init);
165
diff --git a/arch/arm/mach-s3c2440/dsc.c b/arch/arm/mach-s3c2440/dsc.c
new file mode 100644
index 000000000000..2995ff5681bb
--- /dev/null
+++ b/arch/arm/mach-s3c2440/dsc.c
@@ -0,0 +1,54 @@
1/* linux/arch/arm/mach-s3c2440/dsc.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 Drive Strength Control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/init.h>
17#include <linux/module.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/mach/irq.h>
22
23#include <asm/hardware.h>
24#include <asm/io.h>
25#include <asm/irq.h>
26
27#include <asm/arch/regs-gpio.h>
28#include <asm/arch/regs-dsc.h>
29
30#include <asm/plat-s3c24xx/cpu.h>
31#include <asm/plat-s3c24xx/s3c2440.h>
32
33int s3c2440_set_dsc(unsigned int pin, unsigned int value)
34{
35 void __iomem *base;
36 unsigned long val;
37 unsigned long flags;
38 unsigned long mask;
39
40 base = (pin & S3C2440_SELECT_DSC1) ? S3C2440_DSC1 : S3C2440_DSC0;
41 mask = 3 << S3C2440_DSC_GETSHIFT(pin);
42
43 local_irq_save(flags);
44
45 val = __raw_readl(base);
46 val &= ~mask;
47 val |= value & mask;
48 __raw_writel(val, base);
49
50 local_irq_restore(flags);
51 return 0;
52}
53
54EXPORT_SYMBOL(s3c2440_set_dsc);
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
new file mode 100644
index 000000000000..1069d13d8c57
--- /dev/null
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -0,0 +1,130 @@
1/* linux/arch/arm/mach-s3c2440/irq.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/ptrace.h>
27#include <linux/sysdev.h>
28
29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/io.h>
32
33#include <asm/mach/irq.h>
34
35#include <asm/arch/regs-irq.h>
36#include <asm/arch/regs-gpio.h>
37
38#include <asm/plat-s3c24xx/cpu.h>
39#include <asm/plat-s3c24xx/pm.h>
40#include <asm/plat-s3c24xx/irq.h>
41
42/* WDT/AC97 */
43
44static void s3c_irq_demux_wdtac97(unsigned int irq,
45 struct irq_desc *desc)
46{
47 unsigned int subsrc, submsk;
48 struct irq_desc *mydesc;
49
50 /* read the current pending interrupts, and the mask
51 * for what it is available */
52
53 subsrc = __raw_readl(S3C2410_SUBSRCPND);
54 submsk = __raw_readl(S3C2410_INTSUBMSK);
55
56 subsrc &= ~submsk;
57 subsrc >>= 13;
58 subsrc &= 3;
59
60 if (subsrc != 0) {
61 if (subsrc & 1) {
62 mydesc = irq_desc + IRQ_S3C2440_WDT;
63 desc_handle_irq(IRQ_S3C2440_WDT, mydesc);
64 }
65 if (subsrc & 2) {
66 mydesc = irq_desc + IRQ_S3C2440_AC97;
67 desc_handle_irq(IRQ_S3C2440_AC97, mydesc);
68 }
69 }
70}
71
72
73#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
74
75static void
76s3c_irq_wdtac97_mask(unsigned int irqno)
77{
78 s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13);
79}
80
81static void
82s3c_irq_wdtac97_unmask(unsigned int irqno)
83{
84 s3c_irqsub_unmask(irqno, INTMSK_WDT);
85}
86
87static void
88s3c_irq_wdtac97_ack(unsigned int irqno)
89{
90 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
91}
92
93static struct irq_chip s3c_irq_wdtac97 = {
94 .mask = s3c_irq_wdtac97_mask,
95 .unmask = s3c_irq_wdtac97_unmask,
96 .ack = s3c_irq_wdtac97_ack,
97};
98
99static int s3c2440_irq_add(struct sys_device *sysdev)
100{
101 unsigned int irqno;
102
103 printk("S3C2440: IRQ Support\n");
104
105 /* add new chained handler for wdt, ac7 */
106
107 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
108 set_irq_handler(IRQ_WDT, handle_level_irq);
109 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
110
111 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
112 set_irq_chip(irqno, &s3c_irq_wdtac97);
113 set_irq_handler(irqno, handle_level_irq);
114 set_irq_flags(irqno, IRQF_VALID);
115 }
116
117 return 0;
118}
119
120static struct sysdev_driver s3c2440_irq_driver = {
121 .add = s3c2440_irq_add,
122};
123
124static int s3c2440_irq_init(void)
125{
126 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
127}
128
129arch_initcall(s3c2440_irq_init);
130
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
new file mode 100644
index 000000000000..3f0288eb1ed5
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -0,0 +1,325 @@
1/* linux/arch/arm/mach-s3c2440/mach-anubis.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20
21#include <asm/mach/arch.h>
22#include <asm/mach/map.h>
23#include <asm/mach/irq.h>
24
25#include <asm/arch/anubis-map.h>
26#include <asm/arch/anubis-irq.h>
27#include <asm/arch/anubis-cpld.h>
28
29#include <asm/hardware.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/mach-types.h>
33
34#include <asm/arch/regs-serial.h>
35#include <asm/arch/regs-gpio.h>
36#include <asm/arch/regs-mem.h>
37#include <asm/arch/regs-lcd.h>
38#include <asm/arch/nand.h>
39
40#include <linux/mtd/mtd.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/nand_ecc.h>
43#include <linux/mtd/partitions.h>
44
45#include <asm/plat-s3c24xx/clock.h>
46#include <asm/plat-s3c24xx/devs.h>
47#include <asm/plat-s3c24xx/cpu.h>
48
49#define COPYRIGHT ", (c) 2005 Simtec Electronics"
50
51static struct map_desc anubis_iodesc[] __initdata = {
52 /* ISA IO areas */
53
54 {
55 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
56 .pfn = __phys_to_pfn(0x0),
57 .length = SZ_4M,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = (u32)S3C24XX_VA_ISA_WORD,
61 .pfn = __phys_to_pfn(0x0),
62 .length = SZ_4M,
63 .type = MT_DEVICE,
64 },
65
66 /* we could possibly compress the next set down into a set of smaller tables
67 * pagetables, but that would mean using an L2 section, and it still means
68 * we cannot actually feed the same register to an LDR due to 16K spacing
69 */
70
71 /* CPLD control registers */
72
73 {
74 .virtual = (u32)ANUBIS_VA_CTRL1,
75 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
76 .length = SZ_4K,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = (u32)ANUBIS_VA_CTRL2,
80 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL2),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 },
84};
85
86#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
87#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
88#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
89
90static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
91 [0] = {
92 .name = "uclk",
93 .divisor = 1,
94 .min_baud = 0,
95 .max_baud = 0,
96 },
97 [1] = {
98 .name = "pclk",
99 .divisor = 1,
100 .min_baud = 0,
101 .max_baud = 0,
102 }
103};
104
105
106static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
107 [0] = {
108 .hwport = 0,
109 .flags = 0,
110 .ucon = UCON,
111 .ulcon = ULCON,
112 .ufcon = UFCON,
113 .clocks = anubis_serial_clocks,
114 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
115 },
116 [1] = {
117 .hwport = 2,
118 .flags = 0,
119 .ucon = UCON,
120 .ulcon = ULCON,
121 .ufcon = UFCON,
122 .clocks = anubis_serial_clocks,
123 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
124 },
125};
126
127/* NAND Flash on Anubis board */
128
129static int external_map[] = { 2 };
130static int chip0_map[] = { 0 };
131static int chip1_map[] = { 1 };
132
133static struct mtd_partition anubis_default_nand_part[] = {
134 [0] = {
135 .name = "Boot Agent",
136 .size = SZ_16K,
137 .offset = 0,
138 },
139 [1] = {
140 .name = "/boot",
141 .size = SZ_4M - SZ_16K,
142 .offset = SZ_16K,
143 },
144 [2] = {
145 .name = "user1",
146 .offset = SZ_4M,
147 .size = SZ_32M - SZ_4M,
148 },
149 [3] = {
150 .name = "user2",
151 .offset = SZ_32M,
152 .size = MTDPART_SIZ_FULL,
153 }
154};
155
156/* the Anubis has 3 selectable slots for nand-flash, the two
157 * on-board chip areas, as well as the external slot.
158 *
159 * Note, there is no current hot-plug support for the External
160 * socket.
161*/
162
163static struct s3c2410_nand_set anubis_nand_sets[] = {
164 [1] = {
165 .name = "External",
166 .nr_chips = 1,
167 .nr_map = external_map,
168 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
169 .partitions = anubis_default_nand_part,
170 },
171 [0] = {
172 .name = "chip0",
173 .nr_chips = 1,
174 .nr_map = chip0_map,
175 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
176 .partitions = anubis_default_nand_part,
177 },
178 [2] = {
179 .name = "chip1",
180 .nr_chips = 1,
181 .nr_map = chip1_map,
182 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
183 .partitions = anubis_default_nand_part,
184 },
185};
186
187static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
188{
189 unsigned int tmp;
190
191 slot = set->nr_map[slot] & 3;
192
193 pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
194 slot, set, set->nr_map);
195
196 tmp = __raw_readb(ANUBIS_VA_CTRL1);
197 tmp &= ~ANUBIS_CTRL1_NANDSEL;
198 tmp |= slot;
199
200 pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
201
202 __raw_writeb(tmp, ANUBIS_VA_CTRL1);
203}
204
205static struct s3c2410_platform_nand anubis_nand_info = {
206 .tacls = 25,
207 .twrph0 = 55,
208 .twrph1 = 40,
209 .nr_sets = ARRAY_SIZE(anubis_nand_sets),
210 .sets = anubis_nand_sets,
211 .select_chip = anubis_nand_select,
212};
213
214/* IDE channels */
215
216static struct resource anubis_ide0_resource[] = {
217 {
218 .start = S3C2410_CS3,
219 .end = S3C2410_CS3 + (8*32) - 1,
220 .flags = IORESOURCE_MEM,
221 }, {
222 .start = S3C2410_CS3 + (1<<26),
223 .end = S3C2410_CS3 + (1<<26) + (8*32) - 1,
224 .flags = IORESOURCE_MEM,
225 }, {
226 .start = IRQ_IDE0,
227 .end = IRQ_IDE0,
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device anubis_device_ide0 = {
233 .name = "simtec-ide",
234 .id = 0,
235 .num_resources = ARRAY_SIZE(anubis_ide0_resource),
236 .resource = anubis_ide0_resource,
237};
238
239static struct resource anubis_ide1_resource[] = {
240 {
241 .start = S3C2410_CS4,
242 .end = S3C2410_CS4 + (8*32) - 1,
243 .flags = IORESOURCE_MEM,
244 }, {
245 .start = S3C2410_CS4 + (1<<26),
246 .end = S3C2410_CS4 + (1<<26) + (8*32) - 1,
247 .flags = IORESOURCE_MEM,
248 }, {
249 .start = IRQ_IDE0,
250 .end = IRQ_IDE0,
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255
256static struct platform_device anubis_device_ide1 = {
257 .name = "simtec-ide",
258 .id = 1,
259 .num_resources = ARRAY_SIZE(anubis_ide1_resource),
260 .resource = anubis_ide1_resource,
261};
262
263/* Standard Anubis devices */
264
265static struct platform_device *anubis_devices[] __initdata = {
266 &s3c_device_usb,
267 &s3c_device_wdt,
268 &s3c_device_adc,
269 &s3c_device_i2c,
270 &s3c_device_rtc,
271 &s3c_device_nand,
272 &anubis_device_ide0,
273 &anubis_device_ide1,
274};
275
276static struct clk *anubis_clocks[] = {
277 &s3c24xx_dclk0,
278 &s3c24xx_dclk1,
279 &s3c24xx_clkout0,
280 &s3c24xx_clkout1,
281 &s3c24xx_uclk,
282};
283
284static struct s3c24xx_board anubis_board __initdata = {
285 .devices = anubis_devices,
286 .devices_count = ARRAY_SIZE(anubis_devices),
287 .clocks = anubis_clocks,
288 .clocks_count = ARRAY_SIZE(anubis_clocks),
289};
290
291static void __init anubis_map_io(void)
292{
293 /* initialise the clocks */
294
295 s3c24xx_dclk0.parent = NULL;
296 s3c24xx_dclk0.rate = 12*1000*1000;
297
298 s3c24xx_dclk1.parent = NULL;
299 s3c24xx_dclk1.rate = 24*1000*1000;
300
301 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
302 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
303
304 s3c24xx_uclk.parent = &s3c24xx_clkout1;
305
306 s3c_device_nand.dev.platform_data = &anubis_nand_info;
307
308 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
309 s3c24xx_init_clocks(0);
310 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
311 s3c24xx_set_board(&anubis_board);
312
313 /* ensure that the GPIO is setup */
314 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
315}
316
317MACHINE_START(ANUBIS, "Simtec-Anubis")
318 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
319 .phys_io = S3C2410_PA_UART,
320 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
321 .boot_params = S3C2410_SDRAM_PA + 0x100,
322 .map_io = anubis_map_io,
323 .init_irq = s3c24xx_init_irq,
324 .timer = &s3c24xx_timer,
325MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
new file mode 100644
index 000000000000..6d551d88330b
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -0,0 +1,158 @@
1/* linux/arch/arm/mach-s3c2440/mach-nexcoder.c
2 *
3 * Copyright (c) 2004 Nex Vision
4 * Guillaume GOURAT <guillaume.gourat@nexvision.tv>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Modifications:
11 * 15-10-2004 GG Created initial version
12 * 12-03-2005 BJD Updated for release
13 */
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/string.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24
25#include <linux/mtd/map.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
31#include <asm/setup.h>
32#include <asm/hardware.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/mach-types.h>
36
37//#include <asm/debug-ll.h>
38#include <asm/arch/regs-gpio.h>
39#include <asm/arch/regs-serial.h>
40
41#include <asm/plat-s3c24xx/s3c2410.h>
42#include <asm/plat-s3c24xx/s3c2440.h>
43#include <asm/plat-s3c24xx/clock.h>
44#include <asm/plat-s3c24xx/devs.h>
45#include <asm/plat-s3c24xx/cpu.h>
46
47static struct map_desc nexcoder_iodesc[] __initdata = {
48 /* nothing here yet */
49};
50
51#define UCON S3C2410_UCON_DEFAULT
52#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
53#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE
54
55static struct s3c2410_uartcfg nexcoder_uartcfgs[] __initdata = {
56 [0] = {
57 .hwport = 0,
58 .flags = 0,
59 .ucon = UCON,
60 .ulcon = ULCON,
61 .ufcon = UFCON,
62 },
63 [1] = {
64 .hwport = 1,
65 .flags = 0,
66 .ucon = UCON,
67 .ulcon = ULCON,
68 .ufcon = UFCON,
69 },
70 [2] = {
71 .hwport = 2,
72 .flags = 0,
73 .ucon = UCON,
74 .ulcon = ULCON,
75 .ufcon = UFCON,
76 }
77};
78
79/* NOR Flash on NexVision NexCoder 2440 board */
80
81static struct resource nexcoder_nor_resource[] = {
82 [0] = {
83 .start = S3C2410_CS0,
84 .end = S3C2410_CS0 + (8*1024*1024) - 1,
85 .flags = IORESOURCE_MEM,
86 }
87};
88
89static struct map_info nexcoder_nor_map = {
90 .bankwidth = 2,
91};
92
93static struct platform_device nexcoder_device_nor = {
94 .name = "mtd-flash",
95 .id = -1,
96 .num_resources = ARRAY_SIZE(nexcoder_nor_resource),
97 .resource = nexcoder_nor_resource,
98 .dev =
99 {
100 .platform_data = &nexcoder_nor_map,
101 }
102};
103
104/* Standard Nexcoder devices */
105
106static struct platform_device *nexcoder_devices[] __initdata = {
107 &s3c_device_usb,
108 &s3c_device_lcd,
109 &s3c_device_wdt,
110 &s3c_device_i2c,
111 &s3c_device_iis,
112 &s3c_device_rtc,
113 &s3c_device_camif,
114 &s3c_device_spi0,
115 &s3c_device_spi1,
116 &nexcoder_device_nor,
117};
118
119static struct s3c24xx_board nexcoder_board __initdata = {
120 .devices = nexcoder_devices,
121 .devices_count = ARRAY_SIZE(nexcoder_devices),
122};
123
124
125static void __init nexcoder_sensorboard_init(void)
126{
127 // Initialize SCCB bus
128 s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL
129 s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP);
130 s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA
131 s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP);
132
133 // Power up the sensor board
134 s3c2410_gpio_setpin(S3C2410_GPF1, 1);
135 s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN
136 s3c2410_gpio_setpin(S3C2410_GPF2, 0);
137 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN
138}
139
140static void __init nexcoder_map_io(void)
141{
142 s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
143 s3c24xx_init_clocks(0);
144 s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
145 s3c24xx_set_board(&nexcoder_board);
146 nexcoder_sensorboard_init();
147}
148
149
150MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
151 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
152 .phys_io = S3C2410_PA_UART,
153 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
154 .boot_params = S3C2410_SDRAM_PA + 0x100,
155 .map_io = nexcoder_map_io,
156 .init_irq = s3c24xx_init_irq,
157 .timer = &s3c24xx_timer,
158MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
new file mode 100644
index 000000000000..2ed8e51f20c8
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -0,0 +1,303 @@
1/* linux/arch/arm/mach-s3c2440/mach-osiris.c
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/device.h>
19#include <linux/serial_core.h>
20
21#include <asm/mach/arch.h>
22#include <asm/mach/map.h>
23#include <asm/mach/irq.h>
24
25#include <asm/arch/osiris-map.h>
26#include <asm/arch/osiris-cpld.h>
27
28#include <asm/hardware.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/mach-types.h>
32
33#include <asm/arch/regs-serial.h>
34#include <asm/arch/regs-gpio.h>
35#include <asm/arch/regs-mem.h>
36#include <asm/arch/regs-lcd.h>
37#include <asm/arch/nand.h>
38
39#include <linux/mtd/mtd.h>
40#include <linux/mtd/nand.h>
41#include <linux/mtd/nand_ecc.h>
42#include <linux/mtd/partitions.h>
43
44#include <asm/plat-s3c24xx/clock.h>
45#include <asm/plat-s3c24xx/devs.h>
46#include <asm/plat-s3c24xx/cpu.h>
47
48/* onboard perihpheral map */
49
50static struct map_desc osiris_iodesc[] __initdata = {
51 /* ISA IO areas (may be over-written later) */
52
53 {
54 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
55 .pfn = __phys_to_pfn(S3C2410_CS5),
56 .length = SZ_16M,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (u32)S3C24XX_VA_ISA_WORD,
60 .pfn = __phys_to_pfn(S3C2410_CS5),
61 .length = SZ_16M,
62 .type = MT_DEVICE,
63 },
64
65 /* CPLD control registers */
66
67 {
68 .virtual = (u32)OSIRIS_VA_CTRL1,
69 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
70 .length = SZ_16K,
71 .type = MT_DEVICE,
72 }, {
73 .virtual = (u32)OSIRIS_VA_CTRL2,
74 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
75 .length = SZ_16K,
76 .type = MT_DEVICE,
77 },
78};
79
80#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
81#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
82#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
83
84static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
85 [0] = {
86 .name = "uclk",
87 .divisor = 1,
88 .min_baud = 0,
89 .max_baud = 0,
90 },
91 [1] = {
92 .name = "pclk",
93 .divisor = 1,
94 .min_baud = 0,
95 .max_baud = 0,
96 }
97};
98
99static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
100 [0] = {
101 .hwport = 0,
102 .flags = 0,
103 .ucon = UCON,
104 .ulcon = ULCON,
105 .ufcon = UFCON,
106 .clocks = osiris_serial_clocks,
107 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
108 },
109 [1] = {
110 .hwport = 1,
111 .flags = 0,
112 .ucon = UCON,
113 .ulcon = ULCON,
114 .ufcon = UFCON,
115 .clocks = osiris_serial_clocks,
116 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
117 },
118 [2] = {
119 .hwport = 2,
120 .flags = 0,
121 .ucon = UCON,
122 .ulcon = ULCON,
123 .ufcon = UFCON,
124 .clocks = osiris_serial_clocks,
125 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
126 }
127};
128
129/* NAND Flash on Osiris board */
130
131static int external_map[] = { 2 };
132static int chip0_map[] = { 0 };
133static int chip1_map[] = { 1 };
134
135static struct mtd_partition osiris_default_nand_part[] = {
136 [0] = {
137 .name = "Boot Agent",
138 .size = SZ_16K,
139 .offset = 0,
140 },
141 [1] = {
142 .name = "/boot",
143 .size = SZ_4M - SZ_16K,
144 .offset = SZ_16K,
145 },
146 [2] = {
147 .name = "user1",
148 .offset = SZ_4M,
149 .size = SZ_32M - SZ_4M,
150 },
151 [3] = {
152 .name = "user2",
153 .offset = SZ_32M,
154 .size = MTDPART_SIZ_FULL,
155 }
156};
157
158/* the Osiris has 3 selectable slots for nand-flash, the two
159 * on-board chip areas, as well as the external slot.
160 *
161 * Note, there is no current hot-plug support for the External
162 * socket.
163*/
164
165static struct s3c2410_nand_set osiris_nand_sets[] = {
166 [1] = {
167 .name = "External",
168 .nr_chips = 1,
169 .nr_map = external_map,
170 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
171 .partitions = osiris_default_nand_part,
172 },
173 [0] = {
174 .name = "chip0",
175 .nr_chips = 1,
176 .nr_map = chip0_map,
177 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
178 .partitions = osiris_default_nand_part,
179 },
180 [2] = {
181 .name = "chip1",
182 .nr_chips = 1,
183 .nr_map = chip1_map,
184 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
185 .partitions = osiris_default_nand_part,
186 },
187};
188
189static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
190{
191 unsigned int tmp;
192
193 slot = set->nr_map[slot] & 3;
194
195 pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
196 slot, set, set->nr_map);
197
198 tmp = __raw_readb(OSIRIS_VA_CTRL1);
199 tmp &= ~OSIRIS_CTRL1_NANDSEL;
200 tmp |= slot;
201
202 pr_debug("osiris_nand: ctrl1 now %02x\n", tmp);
203
204 __raw_writeb(tmp, OSIRIS_VA_CTRL1);
205}
206
207static struct s3c2410_platform_nand osiris_nand_info = {
208 .tacls = 25,
209 .twrph0 = 60,
210 .twrph1 = 60,
211 .nr_sets = ARRAY_SIZE(osiris_nand_sets),
212 .sets = osiris_nand_sets,
213 .select_chip = osiris_nand_select,
214};
215
216/* PCMCIA control and configuration */
217
218static struct resource osiris_pcmcia_resource[] = {
219 [0] = {
220 .start = 0x0f000000,
221 .end = 0x0f100000,
222 .flags = IORESOURCE_MEM,
223 },
224 [1] = {
225 .start = 0x0c000000,
226 .end = 0x0c100000,
227 .flags = IORESOURCE_MEM,
228 }
229};
230
231static struct platform_device osiris_pcmcia = {
232 .name = "osiris-pcmcia",
233 .id = -1,
234 .num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
235 .resource = osiris_pcmcia_resource,
236};
237
238/* Standard Osiris devices */
239
240static struct platform_device *osiris_devices[] __initdata = {
241 &s3c_device_i2c,
242 &s3c_device_nand,
243 &osiris_pcmcia,
244};
245
246static struct clk *osiris_clocks[] = {
247 &s3c24xx_dclk0,
248 &s3c24xx_dclk1,
249 &s3c24xx_clkout0,
250 &s3c24xx_clkout1,
251 &s3c24xx_uclk,
252};
253
254static struct s3c24xx_board osiris_board __initdata = {
255 .devices = osiris_devices,
256 .devices_count = ARRAY_SIZE(osiris_devices),
257 .clocks = osiris_clocks,
258 .clocks_count = ARRAY_SIZE(osiris_clocks),
259};
260
261static void __init osiris_map_io(void)
262{
263 unsigned long flags;
264
265 /* initialise the clocks */
266
267 s3c24xx_dclk0.parent = NULL;
268 s3c24xx_dclk0.rate = 12*1000*1000;
269
270 s3c24xx_dclk1.parent = NULL;
271 s3c24xx_dclk1.rate = 24*1000*1000;
272
273 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
274 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
275
276 s3c24xx_uclk.parent = &s3c24xx_clkout1;
277
278 s3c_device_nand.dev.platform_data = &osiris_nand_info;
279
280 s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
281 s3c24xx_init_clocks(0);
282 s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
283 s3c24xx_set_board(&osiris_board);
284
285 /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
286
287 local_irq_save(flags);
288 __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
289 local_irq_restore(flags);
290
291 /* write-protect line to the NAND */
292 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
293}
294
295MACHINE_START(OSIRIS, "Simtec-OSIRIS")
296 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
297 .phys_io = S3C2410_PA_UART,
298 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
299 .boot_params = S3C2410_SDRAM_PA + 0x100,
300 .map_io = osiris_map_io,
301 .init_irq = s3c24xx_init_irq,
302 .timer = &s3c24xx_timer,
303MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
new file mode 100644
index 000000000000..1d4e19bd9206
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -0,0 +1,244 @@
1/* linux/arch/arm/mach-s3c2440/mach-rx3715.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.handhelds.org/projects/rx3715.html
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/tty.h>
21#include <linux/console.h>
22#include <linux/platform_device.h>
23#include <linux/serial_core.h>
24#include <linux/serial.h>
25
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/nand_ecc.h>
29#include <linux/mtd/partitions.h>
30
31#include <asm/mach/arch.h>
32#include <asm/mach/map.h>
33#include <asm/mach/irq.h>
34
35#include <asm/hardware.h>
36#include <asm/hardware/iomd.h>
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/mach-types.h>
40
41#include <asm/arch/regs-serial.h>
42#include <asm/arch/regs-gpio.h>
43#include <asm/arch/regs-lcd.h>
44
45#include <asm/arch/h1940.h>
46#include <asm/arch/nand.h>
47#include <asm/arch/fb.h>
48
49#include <asm/plat-s3c24xx/clock.h>
50#include <asm/plat-s3c24xx/devs.h>
51#include <asm/plat-s3c24xx/cpu.h>
52#include <asm/plat-s3c24xx/pm.h>
53
54static struct map_desc rx3715_iodesc[] __initdata = {
55 /* dump ISA space somewhere unused */
56
57 {
58 .virtual = (u32)S3C24XX_VA_ISA_WORD,
59 .pfn = __phys_to_pfn(S3C2410_CS3),
60 .length = SZ_1M,
61 .type = MT_DEVICE,
62 }, {
63 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
64 .pfn = __phys_to_pfn(S3C2410_CS3),
65 .length = SZ_1M,
66 .type = MT_DEVICE,
67 },
68};
69
70
71static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
72 [0] = {
73 .name = "fclk",
74 .divisor = 0,
75 .min_baud = 0,
76 .max_baud = 0,
77 }
78};
79
80static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
81 [0] = {
82 .hwport = 0,
83 .flags = 0,
84 .ucon = 0x3c5,
85 .ulcon = 0x03,
86 .ufcon = 0x51,
87 .clocks = rx3715_serial_clocks,
88 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
89 },
90 [1] = {
91 .hwport = 1,
92 .flags = 0,
93 .ucon = 0x3c5,
94 .ulcon = 0x03,
95 .ufcon = 0x00,
96 .clocks = rx3715_serial_clocks,
97 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
98 },
99 /* IR port */
100 [2] = {
101 .hwport = 2,
102 .uart_flags = UPF_CONS_FLOW,
103 .ucon = 0x3c5,
104 .ulcon = 0x43,
105 .ufcon = 0x51,
106 .clocks = rx3715_serial_clocks,
107 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
108 }
109};
110
111/* framebuffer lcd controller information */
112
113static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = {
114 .regs = {
115 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \
116 S3C2410_LCDCON1_TFT | \
117 S3C2410_LCDCON1_CLKVAL(0x0C),
118
119 .lcdcon2 = S3C2410_LCDCON2_VBPD(5) | \
120 S3C2410_LCDCON2_LINEVAL(319) | \
121 S3C2410_LCDCON2_VFPD(6) | \
122 S3C2410_LCDCON2_VSPW(2),
123
124 .lcdcon3 = S3C2410_LCDCON3_HBPD(35) | \
125 S3C2410_LCDCON3_HOZVAL(239) | \
126 S3C2410_LCDCON3_HFPD(35),
127
128 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | \
129 S3C2410_LCDCON4_HSPW(7),
130
131 .lcdcon5 = S3C2410_LCDCON5_INVVLINE |
132 S3C2410_LCDCON5_FRM565 |
133 S3C2410_LCDCON5_HWSWP,
134 },
135
136 .lpcsel = 0xf82,
137
138 .gpccon = 0xaa955699,
139 .gpccon_mask = 0xffc003cc,
140 .gpcup = 0x0000ffff,
141 .gpcup_mask = 0xffffffff,
142
143 .gpdcon = 0xaa95aaa1,
144 .gpdcon_mask = 0xffc0fff0,
145 .gpdup = 0x0000faff,
146 .gpdup_mask = 0xffffffff,
147
148 .fixed_syncs = 1,
149 .width = 240,
150 .height = 320,
151
152 .xres = {
153 .min = 240,
154 .max = 240,
155 .defval = 240,
156 },
157
158 .yres = {
159 .max = 320,
160 .min = 320,
161 .defval = 320,
162 },
163
164 .bpp = {
165 .min = 16,
166 .max = 16,
167 .defval = 16,
168 },
169};
170
171static struct mtd_partition rx3715_nand_part[] = {
172 [0] = {
173 .name = "Whole Flash",
174 .offset = 0,
175 .size = MTDPART_SIZ_FULL,
176 .mask_flags = MTD_WRITEABLE,
177 }
178};
179
180static struct s3c2410_nand_set rx3715_nand_sets[] = {
181 [0] = {
182 .name = "Internal",
183 .nr_chips = 1,
184 .nr_partitions = ARRAY_SIZE(rx3715_nand_part),
185 .partitions = rx3715_nand_part,
186 },
187};
188
189static struct s3c2410_platform_nand rx3715_nand_info = {
190 .tacls = 25,
191 .twrph0 = 50,
192 .twrph1 = 15,
193 .nr_sets = ARRAY_SIZE(rx3715_nand_sets),
194 .sets = rx3715_nand_sets,
195};
196
197static struct platform_device *rx3715_devices[] __initdata = {
198 &s3c_device_usb,
199 &s3c_device_lcd,
200 &s3c_device_wdt,
201 &s3c_device_i2c,
202 &s3c_device_iis,
203 &s3c_device_nand,
204};
205
206static struct s3c24xx_board rx3715_board __initdata = {
207 .devices = rx3715_devices,
208 .devices_count = ARRAY_SIZE(rx3715_devices)
209};
210
211static void __init rx3715_map_io(void)
212{
213 s3c_device_nand.dev.platform_data = &rx3715_nand_info;
214
215 s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
216 s3c24xx_init_clocks(16934000);
217 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
218 s3c24xx_set_board(&rx3715_board);
219}
220
221static void __init rx3715_init_irq(void)
222{
223 s3c24xx_init_irq();
224}
225
226static void __init rx3715_init_machine(void)
227{
228 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
229 s3c2410_pm_init();
230
231 s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
232}
233
234
235MACHINE_START(RX3715, "IPAQ-RX3715")
236 /* Maintainer: Ben Dooks <ben@fluff.org> */
237 .phys_io = S3C2410_PA_UART,
238 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
239 .boot_params = S3C2410_SDRAM_PA + 0x100,
240 .map_io = rx3715_map_io,
241 .init_irq = rx3715_init_irq,
242 .init_machine = rx3715_init_machine,
243 .timer = &s3c24xx_timer,
244MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
new file mode 100644
index 000000000000..270e42b9b5c1
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -0,0 +1,208 @@
1/* linux/arch/arm/mach-s3c2440/mach-smdk2440.c
2 *
3 * Copyright (c) 2004,2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.fluff.org/ben/smdk2440/
7 *
8 * Thanks to Dimity Andric and TomTom for the loan of an SMDK2440.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <asm/hardware.h>
30#include <asm/hardware/iomd.h>
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <asm/mach-types.h>
34
35//#include <asm/debug-ll.h>
36#include <asm/arch/regs-serial.h>
37#include <asm/arch/regs-gpio.h>
38#include <asm/arch/regs-lcd.h>
39
40#include <asm/arch/idle.h>
41#include <asm/arch/fb.h>
42
43#include <asm/plat-s3c24xx/s3c2410.h>
44#include <asm/plat-s3c24xx/s3c2440.h>
45#include <asm/plat-s3c24xx/clock.h>
46#include <asm/plat-s3c24xx/devs.h>
47#include <asm/plat-s3c24xx/cpu.h>
48
49#include <asm/plat-s3c24xx/common-smdk.h>
50
51static struct map_desc smdk2440_iodesc[] __initdata = {
52 /* ISA IO Space map (memory space selected by A24) */
53
54 {
55 .virtual = (u32)S3C24XX_VA_ISA_WORD,
56 .pfn = __phys_to_pfn(S3C2410_CS2),
57 .length = 0x10000,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
61 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
62 .length = SZ_4M,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
66 .pfn = __phys_to_pfn(S3C2410_CS2),
67 .length = 0x10000,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
71 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
72 .length = SZ_4M,
73 .type = MT_DEVICE,
74 }
75};
76
77#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
78#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
79#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
80
81static struct s3c2410_uartcfg smdk2440_uartcfgs[] __initdata = {
82 [0] = {
83 .hwport = 0,
84 .flags = 0,
85 .ucon = 0x3c5,
86 .ulcon = 0x03,
87 .ufcon = 0x51,
88 },
89 [1] = {
90 .hwport = 1,
91 .flags = 0,
92 .ucon = 0x3c5,
93 .ulcon = 0x03,
94 .ufcon = 0x51,
95 },
96 /* IR port */
97 [2] = {
98 .hwport = 2,
99 .flags = 0,
100 .ucon = 0x3c5,
101 .ulcon = 0x43,
102 .ufcon = 0x51,
103 }
104};
105
106/* LCD driver info */
107
108static struct s3c2410fb_mach_info smdk2440_lcd_cfg __initdata = {
109 .regs = {
110
111 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
112 S3C2410_LCDCON1_TFT |
113 S3C2410_LCDCON1_CLKVAL(0x04),
114
115 .lcdcon2 = S3C2410_LCDCON2_VBPD(7) |
116 S3C2410_LCDCON2_LINEVAL(319) |
117 S3C2410_LCDCON2_VFPD(6) |
118 S3C2410_LCDCON2_VSPW(3),
119
120 .lcdcon3 = S3C2410_LCDCON3_HBPD(19) |
121 S3C2410_LCDCON3_HOZVAL(239) |
122 S3C2410_LCDCON3_HFPD(7),
123
124 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
125 S3C2410_LCDCON4_HSPW(3),
126
127 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
128 S3C2410_LCDCON5_INVVLINE |
129 S3C2410_LCDCON5_INVVFRAME |
130 S3C2410_LCDCON5_PWREN |
131 S3C2410_LCDCON5_HWSWP,
132 },
133
134#if 0
135 /* currently setup by downloader */
136 .gpccon = 0xaa940659,
137 .gpccon_mask = 0xffffffff,
138 .gpcup = 0x0000ffff,
139 .gpcup_mask = 0xffffffff,
140 .gpdcon = 0xaa84aaa0,
141 .gpdcon_mask = 0xffffffff,
142 .gpdup = 0x0000faff,
143 .gpdup_mask = 0xffffffff,
144#endif
145
146 .lpcsel = ((0xCE6) & ~7) | 1<<4,
147
148 .width = 240,
149 .height = 320,
150
151 .xres = {
152 .min = 240,
153 .max = 240,
154 .defval = 240,
155 },
156
157 .yres = {
158 .min = 320,
159 .max = 320,
160 .defval = 320,
161 },
162
163 .bpp = {
164 .min = 16,
165 .max = 16,
166 .defval = 16,
167 },
168};
169
170static struct platform_device *smdk2440_devices[] __initdata = {
171 &s3c_device_usb,
172 &s3c_device_lcd,
173 &s3c_device_wdt,
174 &s3c_device_i2c,
175 &s3c_device_iis,
176};
177
178static struct s3c24xx_board smdk2440_board __initdata = {
179 .devices = smdk2440_devices,
180 .devices_count = ARRAY_SIZE(smdk2440_devices)
181};
182
183static void __init smdk2440_map_io(void)
184{
185 s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
186 s3c24xx_init_clocks(16934400);
187 s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
188 s3c24xx_set_board(&smdk2440_board);
189}
190
191static void __init smdk2440_machine_init(void)
192{
193 s3c24xx_fb_set_platdata(&smdk2440_lcd_cfg);
194
195 smdk_machine_init();
196}
197
198MACHINE_START(S3C2440, "SMDK2440")
199 /* Maintainer: Ben Dooks <ben@fluff.org> */
200 .phys_io = S3C2410_PA_UART,
201 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
202 .boot_params = S3C2410_SDRAM_PA + 0x100,
203
204 .init_irq = s3c24xx_init_irq,
205 .map_io = smdk2440_map_io,
206 .init_machine = smdk2440_machine_init,
207 .timer = &s3c24xx_timer,
208MACHINE_END
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
new file mode 100644
index 000000000000..90e1da61fbc3
--- /dev/null
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -0,0 +1,52 @@
1/* linux/arch/arm/mach-s3c2440/s3c2440.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 Mobile CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/serial_core.h>
21#include <linux/sysdev.h>
22#include <linux/clk.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <asm/hardware.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31
32#include <asm/plat-s3c24xx/s3c2440.h>
33#include <asm/plat-s3c24xx/devs.h>
34#include <asm/plat-s3c24xx/cpu.h>
35
36static struct sys_device s3c2440_sysdev = {
37 .cls = &s3c2440_sysclass,
38};
39
40int __init s3c2440_init(void)
41{
42 printk("S3C2440: Initialising architecture\n");
43
44 /* change irq for watchdog */
45
46 s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
47 s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT;
48
49 /* register our system device for everything else */
50
51 return sysdev_register(&s3c2440_sysdev);
52}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 08:07:03 -0500