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authorBen Dooks <ben-linux@fluff.org>2010-01-26 02:47:41 -0500
committerBen Dooks <ben-linux@fluff.org>2010-02-01 12:56:04 -0500
commit58bac7b8ded70c39bcd5f7037091051c277618aa (patch)
tree68fab2208ee756748a116ec39de1655923532d95 /arch/arm/mach-s3c2440/s3c244x.c
parent70556b143ae4cf404a73c2461a6bf7fef3fefbf7 (diff)
ARM: S3C24XX: Move S3C2440/S3C2442 plat-s3c24xx support to mach-s3c2440
Remove the old common S3C2440 and S3C2442 SoC support from plat-s3c24xx into mach-s3c2440 now this directory is serving both SoCs. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c2440/s3c244x.c')
-rw-r--r--arch/arm/mach-s3c2440/s3c244x.c196
1 files changed, 196 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c
new file mode 100644
index 000000000000..46e13db03e79
--- /dev/null
+++ b/arch/arm/mach-s3c2440/s3c244x.c
@@ -0,0 +1,196 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/sysdev.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <plat/cpu-freq.h>
33
34#include <mach/regs-clock.h>
35#include <plat/regs-serial.h>
36#include <mach/regs-gpio.h>
37#include <mach/regs-gpioj.h>
38#include <mach/regs-dsc.h>
39
40#include <plat/s3c2410.h>
41#include <plat/s3c2440.h>
42#include <plat/s3c244x.h>
43#include <plat/clock.h>
44#include <plat/devs.h>
45#include <plat/cpu.h>
46#include <plat/pm.h>
47#include <plat/pll.h>
48
49static struct map_desc s3c244x_iodesc[] __initdata = {
50 IODESC_ENT(CLKPWR),
51 IODESC_ENT(TIMER),
52 IODESC_ENT(WATCHDOG),
53};
54
55/* uart initialisation */
56
57void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
58{
59 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
60}
61
62void __init s3c244x_map_io(void)
63{
64 /* register our io-tables */
65
66 iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
67
68 /* rename any peripherals used differing from the s3c2410 */
69
70 s3c_device_sdi.name = "s3c2440-sdi";
71 s3c_device_i2c0.name = "s3c2440-i2c";
72 s3c_device_nand.name = "s3c2440-nand";
73 s3c_device_ts.name = "s3c2440-ts";
74 s3c_device_usbgadget.name = "s3c2440-usbgadget";
75}
76
77void __init_or_cpufreq s3c244x_setup_clocks(void)
78{
79 struct clk *xtal_clk;
80 unsigned long clkdiv;
81 unsigned long camdiv;
82 unsigned long xtal;
83 unsigned long hclk, fclk, pclk;
84 int hdiv = 1;
85
86 xtal_clk = clk_get(NULL, "xtal");
87 xtal = clk_get_rate(xtal_clk);
88 clk_put(xtal_clk);
89
90 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
91
92 clkdiv = __raw_readl(S3C2410_CLKDIVN);
93 camdiv = __raw_readl(S3C2440_CAMDIVN);
94
95 /* work out clock scalings */
96
97 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
98 case S3C2440_CLKDIVN_HDIVN_1:
99 hdiv = 1;
100 break;
101
102 case S3C2440_CLKDIVN_HDIVN_2:
103 hdiv = 2;
104 break;
105
106 case S3C2440_CLKDIVN_HDIVN_4_8:
107 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
108 break;
109
110 case S3C2440_CLKDIVN_HDIVN_3_6:
111 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
112 break;
113 }
114
115 hclk = fclk / hdiv;
116 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
117
118 /* print brief summary of clocks, etc */
119
120 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
121 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
122
123 s3c24xx_setup_clocks(fclk, hclk, pclk);
124}
125
126void __init s3c244x_init_clocks(int xtal)
127{
128 /* initialise the clocks here, to allow other things like the
129 * console to use them, and to add new ones after the initialisation
130 */
131
132 s3c24xx_register_baseclocks(xtal);
133 s3c244x_setup_clocks();
134 s3c2410_baseclk_add();
135}
136
137#ifdef CONFIG_PM
138
139static struct sleep_save s3c244x_sleep[] = {
140 SAVE_ITEM(S3C2440_DSC0),
141 SAVE_ITEM(S3C2440_DSC1),
142 SAVE_ITEM(S3C2440_GPJDAT),
143 SAVE_ITEM(S3C2440_GPJCON),
144 SAVE_ITEM(S3C2440_GPJUP)
145};
146
147static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
148{
149 s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
150 return 0;
151}
152
153static int s3c244x_resume(struct sys_device *dev)
154{
155 s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
156 return 0;
157}
158
159#else
160#define s3c244x_suspend NULL
161#define s3c244x_resume NULL
162#endif
163
164/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
165
166struct sysdev_class s3c2440_sysclass = {
167 .name = "s3c2440-core",
168 .suspend = s3c244x_suspend,
169 .resume = s3c244x_resume
170};
171
172struct sysdev_class s3c2442_sysclass = {
173 .name = "s3c2442-core",
174 .suspend = s3c244x_suspend,
175 .resume = s3c244x_resume
176};
177
178/* need to register class before we actually register the device, and
179 * we also need to ensure that it has been initialised before any of the
180 * drivers even try to use it (even if not on an s3c2440 based system)
181 * as a driver which may support both 2410 and 2440 may try and use it.
182*/
183
184static int __init s3c2440_core_init(void)
185{
186 return sysdev_class_register(&s3c2440_sysclass);
187}
188
189core_initcall(s3c2440_core_init);
190
191static int __init s3c2442_core_init(void)
192{
193 return sysdev_class_register(&s3c2442_sysclass);
194}
195
196core_initcall(s3c2442_core_init);