diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-07-25 15:38:42 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-07-25 15:38:42 -0400 |
commit | ae4c42e4e4d76d003f8ca551fe1aef93ff9a4b21 (patch) | |
tree | 2bff2e4f4456077e7d7c589c8c28824f12dfa21c /arch/arm/mach-s3c2412 | |
parent | dd58ecba48edf14be1a5f70120fcd3002277a74a (diff) | |
parent | ab2a0e0d135490729e384c1826d118f92e88cae8 (diff) |
Merge branch 'next/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (133 commits)
ARM: EXYNOS4: Change devname for FIMD clkdev
ARM: S3C64XX: Cleanup mach/regs-fb.h from mach-s3c64xx
ARM: S5PV210: Cleanup mach/regs-fb.h from mach-s5pv210
ARM: S5PC100: Cleanup mach/regs-fb.h from mach-s5pc100
ARM: S3C24XX: Use generic s3c_set_platdata for devices
ARM: S3C64XX: Use generic s3c_set_platdata for OneNAND
ARM: SAMSUNG: Use generic s3c_set_platdata for NAND
ARM: SAMSUNG: Use generic s3c_set_platdata for USB OHCI
ARM: SAMSUNG: Use generic s3c_set_platdata for HWMON
ARM: SAMSUNG: Use generic s3c_set_platdata for FB
ARM: SAMSUNG: Use generic s3c_set_platdata for TS
ARM: S3C64XX: Add PWM backlight support on SMDK6410
ARM: S5P64X0: Add PWM backlight support on SMDK6450
ARM: S5P64X0: Add PWM backlight support on SMDK6440
ARM: S5PC100: Add PWM backlight support on SMDKC100
ARM: S5PV210: Add PWM backlight support on SMDKV210
ARM: EXYNOS4: Add PWM backlight support on SMDKC210
ARM: EXYNOS4: Add PWM backlight support on SMDKV310
ARM: SAMSUNG: Create a common infrastructure for PWM backlight support
clocksource: convert 32-bit down counting clocksource on S5PV210/S5P64X0
...
Fix up trivial conflict in arch/arm/mach-imx/mach-scb9328.c
Diffstat (limited to 'arch/arm/mach-s3c2412')
-rw-r--r-- | arch/arm/mach-s3c2412/clock.c | 36 |
1 files changed, 3 insertions, 33 deletions
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index 0c0505b025cb..140711db6c89 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c | |||
@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable) | |||
95 | 95 | ||
96 | static struct clk clk_erefclk = { | 96 | static struct clk clk_erefclk = { |
97 | .name = "erefclk", | 97 | .name = "erefclk", |
98 | .id = -1, | ||
99 | }; | 98 | }; |
100 | 99 | ||
101 | static struct clk clk_urefclk = { | 100 | static struct clk clk_urefclk = { |
102 | .name = "urefclk", | 101 | .name = "urefclk", |
103 | .id = -1, | ||
104 | }; | 102 | }; |
105 | 103 | ||
106 | static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) | 104 | static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) |
@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) | |||
122 | 120 | ||
123 | static struct clk clk_usysclk = { | 121 | static struct clk clk_usysclk = { |
124 | .name = "usysclk", | 122 | .name = "usysclk", |
125 | .id = -1, | ||
126 | .parent = &clk_xtal, | 123 | .parent = &clk_xtal, |
127 | .ops = &(struct clk_ops) { | 124 | .ops = &(struct clk_ops) { |
128 | .set_parent = s3c2412_setparent_usysclk, | 125 | .set_parent = s3c2412_setparent_usysclk, |
@@ -132,13 +129,11 @@ static struct clk clk_usysclk = { | |||
132 | static struct clk clk_mrefclk = { | 129 | static struct clk clk_mrefclk = { |
133 | .name = "mrefclk", | 130 | .name = "mrefclk", |
134 | .parent = &clk_xtal, | 131 | .parent = &clk_xtal, |
135 | .id = -1, | ||
136 | }; | 132 | }; |
137 | 133 | ||
138 | static struct clk clk_mdivclk = { | 134 | static struct clk clk_mdivclk = { |
139 | .name = "mdivclk", | 135 | .name = "mdivclk", |
140 | .parent = &clk_xtal, | 136 | .parent = &clk_xtal, |
141 | .id = -1, | ||
142 | }; | 137 | }; |
143 | 138 | ||
144 | static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) | 139 | static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) |
@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) | |||
200 | 195 | ||
201 | static struct clk clk_usbsrc = { | 196 | static struct clk clk_usbsrc = { |
202 | .name = "usbsrc", | 197 | .name = "usbsrc", |
203 | .id = -1, | ||
204 | .ops = &(struct clk_ops) { | 198 | .ops = &(struct clk_ops) { |
205 | .get_rate = s3c2412_getrate_usbsrc, | 199 | .get_rate = s3c2412_getrate_usbsrc, |
206 | .set_rate = s3c2412_setrate_usbsrc, | 200 | .set_rate = s3c2412_setrate_usbsrc, |
@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) | |||
228 | 222 | ||
229 | static struct clk clk_msysclk = { | 223 | static struct clk clk_msysclk = { |
230 | .name = "msysclk", | 224 | .name = "msysclk", |
231 | .id = -1, | ||
232 | .ops = &(struct clk_ops) { | 225 | .ops = &(struct clk_ops) { |
233 | .set_parent = s3c2412_setparent_msysclk, | 226 | .set_parent = s3c2412_setparent_msysclk, |
234 | }, | 227 | }, |
@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) | |||
268 | 261 | ||
269 | static struct clk clk_armclk = { | 262 | static struct clk clk_armclk = { |
270 | .name = "armclk", | 263 | .name = "armclk", |
271 | .id = -1, | ||
272 | .parent = &clk_msysclk, | 264 | .parent = &clk_msysclk, |
273 | .ops = &(struct clk_ops) { | 265 | .ops = &(struct clk_ops) { |
274 | .set_parent = s3c2412_setparent_armclk, | 266 | .set_parent = s3c2412_setparent_armclk, |
@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) | |||
344 | 336 | ||
345 | static struct clk clk_uart = { | 337 | static struct clk clk_uart = { |
346 | .name = "uartclk", | 338 | .name = "uartclk", |
347 | .id = -1, | ||
348 | .ops = &(struct clk_ops) { | 339 | .ops = &(struct clk_ops) { |
349 | .get_rate = s3c2412_getrate_uart, | 340 | .get_rate = s3c2412_getrate_uart, |
350 | .set_rate = s3c2412_setrate_uart, | 341 | .set_rate = s3c2412_setrate_uart, |
@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) | |||
397 | 388 | ||
398 | static struct clk clk_i2s = { | 389 | static struct clk clk_i2s = { |
399 | .name = "i2sclk", | 390 | .name = "i2sclk", |
400 | .id = -1, | ||
401 | .ops = &(struct clk_ops) { | 391 | .ops = &(struct clk_ops) { |
402 | .get_rate = s3c2412_getrate_i2s, | 392 | .get_rate = s3c2412_getrate_i2s, |
403 | .set_rate = s3c2412_setrate_i2s, | 393 | .set_rate = s3c2412_setrate_i2s, |
@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) | |||
449 | 439 | ||
450 | static struct clk clk_cam = { | 440 | static struct clk clk_cam = { |
451 | .name = "camif-upll", /* same as 2440 name */ | 441 | .name = "camif-upll", /* same as 2440 name */ |
452 | .id = -1, | ||
453 | .ops = &(struct clk_ops) { | 442 | .ops = &(struct clk_ops) { |
454 | .get_rate = s3c2412_getrate_cam, | 443 | .get_rate = s3c2412_getrate_cam, |
455 | .set_rate = s3c2412_setrate_cam, | 444 | .set_rate = s3c2412_setrate_cam, |
@@ -463,37 +452,31 @@ static struct clk clk_cam = { | |||
463 | static struct clk init_clocks_disable[] = { | 452 | static struct clk init_clocks_disable[] = { |
464 | { | 453 | { |
465 | .name = "nand", | 454 | .name = "nand", |
466 | .id = -1, | ||
467 | .parent = &clk_h, | 455 | .parent = &clk_h, |
468 | .enable = s3c2412_clkcon_enable, | 456 | .enable = s3c2412_clkcon_enable, |
469 | .ctrlbit = S3C2412_CLKCON_NAND, | 457 | .ctrlbit = S3C2412_CLKCON_NAND, |
470 | }, { | 458 | }, { |
471 | .name = "sdi", | 459 | .name = "sdi", |
472 | .id = -1, | ||
473 | .parent = &clk_p, | 460 | .parent = &clk_p, |
474 | .enable = s3c2412_clkcon_enable, | 461 | .enable = s3c2412_clkcon_enable, |
475 | .ctrlbit = S3C2412_CLKCON_SDI, | 462 | .ctrlbit = S3C2412_CLKCON_SDI, |
476 | }, { | 463 | }, { |
477 | .name = "adc", | 464 | .name = "adc", |
478 | .id = -1, | ||
479 | .parent = &clk_p, | 465 | .parent = &clk_p, |
480 | .enable = s3c2412_clkcon_enable, | 466 | .enable = s3c2412_clkcon_enable, |
481 | .ctrlbit = S3C2412_CLKCON_ADC, | 467 | .ctrlbit = S3C2412_CLKCON_ADC, |
482 | }, { | 468 | }, { |
483 | .name = "i2c", | 469 | .name = "i2c", |
484 | .id = -1, | ||
485 | .parent = &clk_p, | 470 | .parent = &clk_p, |
486 | .enable = s3c2412_clkcon_enable, | 471 | .enable = s3c2412_clkcon_enable, |
487 | .ctrlbit = S3C2412_CLKCON_IIC, | 472 | .ctrlbit = S3C2412_CLKCON_IIC, |
488 | }, { | 473 | }, { |
489 | .name = "iis", | 474 | .name = "iis", |
490 | .id = -1, | ||
491 | .parent = &clk_p, | 475 | .parent = &clk_p, |
492 | .enable = s3c2412_clkcon_enable, | 476 | .enable = s3c2412_clkcon_enable, |
493 | .ctrlbit = S3C2412_CLKCON_IIS, | 477 | .ctrlbit = S3C2412_CLKCON_IIS, |
494 | }, { | 478 | }, { |
495 | .name = "spi", | 479 | .name = "spi", |
496 | .id = -1, | ||
497 | .parent = &clk_p, | 480 | .parent = &clk_p, |
498 | .enable = s3c2412_clkcon_enable, | 481 | .enable = s3c2412_clkcon_enable, |
499 | .ctrlbit = S3C2412_CLKCON_SPI, | 482 | .ctrlbit = S3C2412_CLKCON_SPI, |
@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = { | |||
503 | static struct clk init_clocks[] = { | 486 | static struct clk init_clocks[] = { |
504 | { | 487 | { |
505 | .name = "dma", | 488 | .name = "dma", |
506 | .id = 0, | ||
507 | .parent = &clk_h, | 489 | .parent = &clk_h, |
508 | .enable = s3c2412_clkcon_enable, | 490 | .enable = s3c2412_clkcon_enable, |
509 | .ctrlbit = S3C2412_CLKCON_DMA0, | 491 | .ctrlbit = S3C2412_CLKCON_DMA0, |
510 | }, { | 492 | }, { |
511 | .name = "dma", | 493 | .name = "dma", |
512 | .id = 1, | ||
513 | .parent = &clk_h, | 494 | .parent = &clk_h, |
514 | .enable = s3c2412_clkcon_enable, | 495 | .enable = s3c2412_clkcon_enable, |
515 | .ctrlbit = S3C2412_CLKCON_DMA1, | 496 | .ctrlbit = S3C2412_CLKCON_DMA1, |
516 | }, { | 497 | }, { |
517 | .name = "dma", | 498 | .name = "dma", |
518 | .id = 2, | ||
519 | .parent = &clk_h, | 499 | .parent = &clk_h, |
520 | .enable = s3c2412_clkcon_enable, | 500 | .enable = s3c2412_clkcon_enable, |
521 | .ctrlbit = S3C2412_CLKCON_DMA2, | 501 | .ctrlbit = S3C2412_CLKCON_DMA2, |
522 | }, { | 502 | }, { |
523 | .name = "dma", | 503 | .name = "dma", |
524 | .id = 3, | ||
525 | .parent = &clk_h, | 504 | .parent = &clk_h, |
526 | .enable = s3c2412_clkcon_enable, | 505 | .enable = s3c2412_clkcon_enable, |
527 | .ctrlbit = S3C2412_CLKCON_DMA3, | 506 | .ctrlbit = S3C2412_CLKCON_DMA3, |
528 | }, { | 507 | }, { |
529 | .name = "lcd", | 508 | .name = "lcd", |
530 | .id = -1, | ||
531 | .parent = &clk_h, | 509 | .parent = &clk_h, |
532 | .enable = s3c2412_clkcon_enable, | 510 | .enable = s3c2412_clkcon_enable, |
533 | .ctrlbit = S3C2412_CLKCON_LCDC, | 511 | .ctrlbit = S3C2412_CLKCON_LCDC, |
534 | }, { | 512 | }, { |
535 | .name = "gpio", | 513 | .name = "gpio", |
536 | .id = -1, | ||
537 | .parent = &clk_p, | 514 | .parent = &clk_p, |
538 | .enable = s3c2412_clkcon_enable, | 515 | .enable = s3c2412_clkcon_enable, |
539 | .ctrlbit = S3C2412_CLKCON_GPIO, | 516 | .ctrlbit = S3C2412_CLKCON_GPIO, |
540 | }, { | 517 | }, { |
541 | .name = "usb-host", | 518 | .name = "usb-host", |
542 | .id = -1, | ||
543 | .parent = &clk_h, | 519 | .parent = &clk_h, |
544 | .enable = s3c2412_clkcon_enable, | 520 | .enable = s3c2412_clkcon_enable, |
545 | .ctrlbit = S3C2412_CLKCON_USBH, | 521 | .ctrlbit = S3C2412_CLKCON_USBH, |
546 | }, { | 522 | }, { |
547 | .name = "usb-device", | 523 | .name = "usb-device", |
548 | .id = -1, | ||
549 | .parent = &clk_h, | 524 | .parent = &clk_h, |
550 | .enable = s3c2412_clkcon_enable, | 525 | .enable = s3c2412_clkcon_enable, |
551 | .ctrlbit = S3C2412_CLKCON_USBD, | 526 | .ctrlbit = S3C2412_CLKCON_USBD, |
552 | }, { | 527 | }, { |
553 | .name = "timers", | 528 | .name = "timers", |
554 | .id = -1, | ||
555 | .parent = &clk_p, | 529 | .parent = &clk_p, |
556 | .enable = s3c2412_clkcon_enable, | 530 | .enable = s3c2412_clkcon_enable, |
557 | .ctrlbit = S3C2412_CLKCON_PWMT, | 531 | .ctrlbit = S3C2412_CLKCON_PWMT, |
558 | }, { | 532 | }, { |
559 | .name = "uart", | 533 | .name = "uart", |
560 | .id = 0, | 534 | .devname = "s3c2412-uart.0", |
561 | .parent = &clk_p, | 535 | .parent = &clk_p, |
562 | .enable = s3c2412_clkcon_enable, | 536 | .enable = s3c2412_clkcon_enable, |
563 | .ctrlbit = S3C2412_CLKCON_UART0, | 537 | .ctrlbit = S3C2412_CLKCON_UART0, |
564 | }, { | 538 | }, { |
565 | .name = "uart", | 539 | .name = "uart", |
566 | .id = 1, | 540 | .devname = "s3c2412-uart.1", |
567 | .parent = &clk_p, | 541 | .parent = &clk_p, |
568 | .enable = s3c2412_clkcon_enable, | 542 | .enable = s3c2412_clkcon_enable, |
569 | .ctrlbit = S3C2412_CLKCON_UART1, | 543 | .ctrlbit = S3C2412_CLKCON_UART1, |
570 | }, { | 544 | }, { |
571 | .name = "uart", | 545 | .name = "uart", |
572 | .id = 2, | 546 | .devname = "s3c2412-uart.2", |
573 | .parent = &clk_p, | 547 | .parent = &clk_p, |
574 | .enable = s3c2412_clkcon_enable, | 548 | .enable = s3c2412_clkcon_enable, |
575 | .ctrlbit = S3C2412_CLKCON_UART2, | 549 | .ctrlbit = S3C2412_CLKCON_UART2, |
576 | }, { | 550 | }, { |
577 | .name = "rtc", | 551 | .name = "rtc", |
578 | .id = -1, | ||
579 | .parent = &clk_p, | 552 | .parent = &clk_p, |
580 | .enable = s3c2412_clkcon_enable, | 553 | .enable = s3c2412_clkcon_enable, |
581 | .ctrlbit = S3C2412_CLKCON_RTC, | 554 | .ctrlbit = S3C2412_CLKCON_RTC, |
582 | }, { | 555 | }, { |
583 | .name = "watchdog", | 556 | .name = "watchdog", |
584 | .id = -1, | ||
585 | .parent = &clk_p, | 557 | .parent = &clk_p, |
586 | .ctrlbit = 0, | 558 | .ctrlbit = 0, |
587 | }, { | 559 | }, { |
588 | .name = "usb-bus-gadget", | 560 | .name = "usb-bus-gadget", |
589 | .id = -1, | ||
590 | .parent = &clk_usb_bus, | 561 | .parent = &clk_usb_bus, |
591 | .enable = s3c2412_clkcon_enable, | 562 | .enable = s3c2412_clkcon_enable, |
592 | .ctrlbit = S3C2412_CLKCON_USB_DEV48, | 563 | .ctrlbit = S3C2412_CLKCON_USB_DEV48, |
593 | }, { | 564 | }, { |
594 | .name = "usb-bus-host", | 565 | .name = "usb-bus-host", |
595 | .id = -1, | ||
596 | .parent = &clk_usb_bus, | 566 | .parent = &clk_usb_bus, |
597 | .enable = s3c2412_clkcon_enable, | 567 | .enable = s3c2412_clkcon_enable, |
598 | .ctrlbit = S3C2412_CLKCON_USB_HOST48, | 568 | .ctrlbit = S3C2412_CLKCON_USB_HOST48, |