[ARM] 4157/2: S3C24XX: move arch/arch/mach-s3c2410 into cpu components

The following patch and script moves the arch/arm/mach-s3c2410
directory into arch/arm/plat-s3c24xx for the generic core code
and inti arch/arm/mach-s3c{cpu} for the cpu/machine support files

Include directory include/asm-arm/plat-s3c24xx is added for the
core include files.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

9 files changed, 1707 insertions, 0 deletions

diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
new file mode 100644
index 000000000000..6d629de84cdb
--- /dev/null
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -0,0 +1,58 @@
+# arch/arm/mach-s3c2412/Kconfig
+#
+# Copyright 2007 Simtec Electronics
+#
+# Licensed under GPLv2
+
+config CPU_S3C2412
+        bool
+        depends on ARCH_S3C2410
+        select S3C2412_PM if PM
+        select S3C2412_DMA if S3C2410_DMA
+        help
+          Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
+
+config CPU_S3C2412_ONLY
+        bool
+        depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
+                   !CPU_S3C2440 && !CPU_S3C2442 && CPU_S3C2412
+        default y if CPU_S3C2412
+
+config S3C2412_DMA
+        bool
+        depends on CPU_S3C2412
+        help
+          Internal config node for S3C2412 DMA support
+
+config S3C2412_PM
+        bool
+        help
+          Internal config node to apply S3C2412 power management
+
+
+menu "S3C2412 Machines"
+
+config MACH_SMDK2413
+        bool "SMDK2413"
+        select CPU_S3C2412
+        select MACH_S3C2413
+        select MACH_SMDK
+        help
+          Say Y here if you are using an SMDK2413
+
+config MACH_S3C2413
+        bool
+        help
+          Internal node for S3C2413 version of SMDK2413, so that
+          machine_is_s3c2413() will work when MACH_SMDK2413 is
+          selected
+
+config MACH_VSTMS
+        bool "VMSTMS"
+        select CPU_S3C2412
+        help
+          Say Y here if you are using an VSTMS board
+
+
+endmenu
+
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
new file mode 100644
index 000000000000..f8e011691b31
--- /dev/null
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -0,0 +1,21 @@
+# arch/arm/mach-s3c2412/Makefile
+#
+# Copyright 2007 Simtec Electronics
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o
+obj-$(CONFIG_CPU_S3C2412)       += irq.o
+obj-$(CONFIG_CPU_S3C2412)       += clock.o
+obj-$(CONFIG_S3C2412_DMA)       += dma.o
+obj-$(CONFIG_S3C2412_PM)        += pm.o
+
+# Machine support
+
+obj-$(CONFIG_MACH_SMDK2413)     += mach-smdk2413.o
+obj-$(CONFIG_MACH_VSTMS)        += mach-vstms.o
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
new file mode 100644
index 000000000000..6a8e4448770b
--- /dev/null
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -0,0 +1,716 @@
+/* linux/arch/arm/mach-s3c2412/clock.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412,S3C2413 Clock control support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/map.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+#include <asm/arch/regs-serial.h>
+#include <asm/arch/regs-clock.h>
+#include <asm/arch/regs-gpio.h>
+
+#include <asm/plat-s3c24xx/s3c2412.h>
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+/* We currently have to assume that the system is running
+ * from the XTPll input, and that all ***REFCLKs are being
+ * fed from it, as we cannot read the state of OM[4] from
+ * software.
+ *
+ * It would be possible for each board initialisation to
+ * set the correct muxing at initialisation
+*/
+
+static int s3c2412_clkcon_enable(struct clk *clk, int enable)
+{
+        unsigned int clocks = clk->ctrlbit;
+        unsigned long clkcon;
+
+        clkcon = __raw_readl(S3C2410_CLKCON);
+
+        if (enable)
+                clkcon |= clocks;
+        else
+                clkcon &= ~clocks;
+
+        __raw_writel(clkcon, S3C2410_CLKCON);
+
+        return 0;
+}
+
+static int s3c2412_upll_enable(struct clk *clk, int enable)
+{
+        unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
+        unsigned long orig = upllcon;
+
+        if (!enable)
+                upllcon |= S3C2412_PLLCON_OFF;
+        else
+                upllcon &= ~S3C2412_PLLCON_OFF;
+
+        __raw_writel(upllcon, S3C2410_UPLLCON);
+
+        /* allow ~150uS for the PLL to settle and lock */
+
+        if (enable && (orig & S3C2412_PLLCON_OFF))
+                udelay(150);
+
+        return 0;
+}
+
+/* clock selections */
+
+/* CPU EXTCLK input */
+static struct clk clk_ext = {
+        .name           = "extclk",
+        .id             = -1,
+};
+
+static struct clk clk_erefclk = {
+        .name           = "erefclk",
+        .id             = -1,
+};
+
+static struct clk clk_urefclk = {
+        .name           = "urefclk",
+        .id             = -1,
+};
+
+static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_urefclk)
+                clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
+        else if (parent == &clk_upll)
+                clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+
+static struct clk clk_usysclk = {
+        .name           = "usysclk",
+        .id             = -1,
+        .parent         = &clk_xtal,
+        .set_parent     = s3c2412_setparent_usysclk,
+};
+
+static struct clk clk_mrefclk = {
+        .name           = "mrefclk",
+        .parent         = &clk_xtal,
+        .id             = -1,
+};
+
+static struct clk clk_mdivclk = {
+        .name           = "mdivclk",
+        .parent         = &clk_xtal,
+        .id             = -1,
+};
+
+static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_usysclk)
+                clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
+        else if (parent == &clk_h)
+                clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+
+static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
+                                              unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        int div;
+
+        if (rate > parent_rate)
+                return parent_rate;
+
+        div = parent_rate / rate;
+        if (div > 2)
+                div = 2;
+
+        return parent_rate / div;
+}
+
+static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
+
+        return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
+}
+
+static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
+
+        rate = s3c2412_roundrate_usbsrc(clk, rate);
+
+        if ((parent_rate / rate) == 2)
+                clkdivn |= S3C2412_CLKDIVN_USB48DIV;
+        else
+                clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
+
+        __raw_writel(clkdivn, S3C2410_CLKDIVN);
+        return 0;
+}
+
+static struct clk clk_usbsrc = {
+        .name           = "usbsrc",
+        .id             = -1,
+        .get_rate       = s3c2412_getrate_usbsrc,
+        .set_rate       = s3c2412_setrate_usbsrc,
+        .round_rate     = s3c2412_roundrate_usbsrc,
+        .set_parent     = s3c2412_setparent_usbsrc,
+};
+
+static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_mdivclk)
+                clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
+        else if (parent == &clk_upll)
+                clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+
+static struct clk clk_msysclk = {
+        .name           = "msysclk",
+        .id             = -1,
+        .set_parent     = s3c2412_setparent_msysclk,
+};
+
+/* these next clocks have an divider immediately after them,
+ * so we can register them with their divider and leave out the
+ * intermediate clock stage
+*/
+static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
+                                              unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        int div;
+
+        if (rate > parent_rate)
+                return parent_rate;
+
+        /* note, we remove the +/- 1 calculations as they cancel out */
+
+        div = (rate / parent_rate);
+
+        if (div < 1)
+                div = 1;
+        else if (div > 16)
+                div = 16;
+
+        return parent_rate / div;
+}
+
+static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_erefclk)
+                clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
+        else if (parent == &clk_mpll)
+                clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+
+static unsigned long s3c2412_getrate_uart(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
+
+        div &= S3C2412_CLKDIVN_UARTDIV_MASK;
+        div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
+
+        return parent_rate / (div + 1);
+}
+
+static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
+
+        rate = s3c2412_roundrate_clksrc(clk, rate);
+
+        clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
+        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
+
+        __raw_writel(clkdivn, S3C2410_CLKDIVN);
+        return 0;
+}
+
+static struct clk clk_uart = {
+        .name           = "uartclk",
+        .id             = -1,
+        .get_rate       = s3c2412_getrate_uart,
+        .set_rate       = s3c2412_setrate_uart,
+        .set_parent     = s3c2412_setparent_uart,
+        .round_rate     = s3c2412_roundrate_clksrc,
+};
+
+static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_erefclk)
+                clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
+        else if (parent == &clk_mpll)
+                clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+
+static unsigned long s3c2412_getrate_i2s(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
+
+        div &= S3C2412_CLKDIVN_I2SDIV_MASK;
+        div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
+
+        return parent_rate / (div + 1);
+}
+
+static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
+
+        rate = s3c2412_roundrate_clksrc(clk, rate);
+
+        clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
+        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
+
+        __raw_writel(clkdivn, S3C2410_CLKDIVN);
+        return 0;
+}
+
+static struct clk clk_i2s = {
+        .name           = "i2sclk",
+        .id             = -1,
+        .get_rate       = s3c2412_getrate_i2s,
+        .set_rate       = s3c2412_setrate_i2s,
+        .set_parent     = s3c2412_setparent_i2s,
+        .round_rate     = s3c2412_roundrate_clksrc,
+};
+
+static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_usysclk)
+                clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
+        else if (parent == &clk_h)
+                clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+static unsigned long s3c2412_getrate_cam(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
+
+        div &= S3C2412_CLKDIVN_CAMDIV_MASK;
+        div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
+
+        return parent_rate / (div + 1);
+}
+
+static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
+
+        rate = s3c2412_roundrate_clksrc(clk, rate);
+
+        clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
+        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
+
+        __raw_writel(clkdivn, S3C2410_CLKDIVN);
+        return 0;
+}
+
+static struct clk clk_cam = {
+        .name           = "camif-upll", /* same as 2440 name */
+        .id             = -1,
+        .get_rate       = s3c2412_getrate_cam,
+        .set_rate       = s3c2412_setrate_cam,
+        .set_parent     = s3c2412_setparent_cam,
+        .round_rate     = s3c2412_roundrate_clksrc,
+};
+
+/* standard clock definitions */
+
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "nand",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_NAND,
+        }, {
+                .name           = "sdi",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_SDI,
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_ADC,
+        }, {
+                .name           = "i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_IIC,
+        }, {
+                .name           = "iis",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_IIS,
+        }, {
+                .name           = "spi",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_SPI,
+        }
+};
+
+static struct clk init_clocks[] = {
+        {
+                .name           = "dma",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_DMA0,
+        }, {
+                .name           = "dma",
+                .id             = 1,
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_DMA1,
+        }, {
+                .name           = "dma",
+                .id             = 2,
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_DMA2,
+        }, {
+                .name           = "dma",
+                .id             = 3,
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_DMA3,
+        }, {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_LCDC,
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_GPIO,
+        }, {
+                .name           = "usb-host",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_USBH,
+        }, {
+                .name           = "usb-device",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_USBD,
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_PWMT,
+        }, {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_UART0,
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_UART1,
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_UART2,
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_RTC,
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_p,
+                .ctrlbit        = 0,
+        }, {
+                .name           = "usb-bus-gadget",
+                .id             = -1,
+                .parent         = &clk_usb_bus,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_USB_DEV48,
+        }, {
+                .name           = "usb-bus-host",
+                .id             = -1,
+                .parent         = &clk_usb_bus,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_USB_HOST48,
+        }
+};
+
+/* clocks to add where we need to check their parentage */
+
+struct clk_init {
+        struct clk      *clk;
+        unsigned int     bit;
+        struct clk      *src_0;
+        struct clk      *src_1;
+};
+
+static struct clk_init clks_src[] __initdata = {
+        {
+                .clk    = &clk_usysclk,
+                .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
+                .src_0  = &clk_urefclk,
+                .src_1  = &clk_upll,
+        }, {
+                .clk    = &clk_i2s,
+                .bit    = S3C2412_CLKSRC_I2SCLK_MPLL,
+                .src_0  = &clk_erefclk,
+                .src_1  = &clk_mpll,
+        }, {
+                .clk    = &clk_cam,
+                .bit    = S3C2412_CLKSRC_CAMCLK_HCLK,
+                .src_0  = &clk_usysclk,
+                .src_1  = &clk_h,
+        }, {
+                .clk    = &clk_msysclk,
+                .bit    = S3C2412_CLKSRC_MSYSCLK_MPLL,
+                .src_0  = &clk_mdivclk,
+                .src_1  = &clk_mpll,
+        }, {
+                .clk    = &clk_uart,
+                .bit    = S3C2412_CLKSRC_UARTCLK_MPLL,
+                .src_0  = &clk_erefclk,
+                .src_1  = &clk_mpll,
+        }, {
+                .clk    = &clk_usbsrc,
+                .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
+                .src_0  = &clk_usysclk,
+                .src_1  = &clk_h,
+        },
+};
+
+/* s3c2412_clk_initparents
+ *
+ * Initialise the parents for the clocks that we get at start-time
+*/
+
+static void __init s3c2412_clk_initparents(void)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+        struct clk_init *cip = clks_src;
+        struct clk *src;
+        int ptr;
+        int ret;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
+                ret = s3c24xx_register_clock(cip->clk);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               cip->clk->name, ret);
+                }
+
+                src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
+
+                printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
+                clk_set_parent(cip->clk, src);
+        }
+}
+
+/* clocks to add straight away */
+
+static struct clk *clks[] __initdata = {
+        &clk_ext,
+        &clk_usb_bus,
+        &clk_erefclk,
+        &clk_urefclk,
+        &clk_mrefclk,
+};
+
+int __init s3c2412_baseclk_add(void)
+{
+        unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        clk_upll.enable = s3c2412_upll_enable;
+        clk_usb_bus.parent = &clk_usbsrc;
+        clk_usb_bus.rate = 0x0;
+
+        s3c2412_clk_initparents();
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
+                clkp = clks[ptr];
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+
+        /* ensure usb bus clock is within correct rate of 48MHz */
+
+        if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
+                printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
+
+                /* for the moment, let's use the UPLL, and see if we can
+                 * get 48MHz */
+
+                clk_set_parent(&clk_usysclk, &clk_upll);
+                clk_set_parent(&clk_usbsrc, &clk_usysclk);
+                clk_set_rate(&clk_usbsrc, 48*1000*1000);
+        }
+
+        printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
+               (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
+               print_mhz(clk_get_rate(&clk_upll)),
+               print_mhz(clk_get_rate(&clk_usb_bus)));
+
+        /* register clocks from clock array */
+
+        clkp = init_clocks;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
+                /* ensure that we note the clock state */
+
+                clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+
+        /* We must be careful disabling the clocks we are not intending to
+         * be using at boot time, as subsytems such as the LCD which do
+         * their own DMA requests to the bus can cause the system to lockup
+         * if they where in the middle of requesting bus access.
+         *
+         * Disabling the LCD clock if the LCD is active is very dangerous,
+         * and therefore the bootloader should be careful to not enable
+         * the LCD clock if it is not needed.
+        */
+
+        /* install (and disable) the clocks we do not need immediately */
+
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+
+                s3c2412_clkcon_enable(clkp, 0);
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
new file mode 100644
index 000000000000..28b598287fae
--- /dev/null
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -0,0 +1,161 @@
+/* linux/arch/arm/mach-s3c2412/dma.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412 DMA selection
+ *
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+
+#include <asm/dma.h>
+#include <asm/arch/dma.h>
+#include <asm/io.h>
+
+#include <asm/plat-s3c24xx/dma.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+#include <asm/arch/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-ac97.h>
+#include <asm/arch/regs-mem.h>
+#include <asm/arch/regs-lcd.h>
+#include <asm/arch/regs-sdi.h>
+#include <asm/arch/regs-iis.h>
+#include <asm/arch/regs-spi.h>
+
+#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
+
+static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
+        [DMACH_XD0] = {
+                .name           = "xdreq0",
+                .channels       = MAP(S3C2412_DMAREQSEL_XDREQ0),
+        },
+        [DMACH_XD1] = {
+                .name           = "xdreq1",
+                .channels       = MAP(S3C2412_DMAREQSEL_XDREQ1),
+        },
+        [DMACH_SDI] = {
+                .name           = "sdi",
+                .channels       = MAP(S3C2412_DMAREQSEL_SDI),
+                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
+                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
+        },
+        [DMACH_SPI0] = {
+                .name           = "spi0",
+                .channels       = MAP(S3C2412_DMAREQSEL_SPI0TX),
+                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
+                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
+        },
+        [DMACH_SPI1] = {
+                .name           = "spi1",
+                .channels       = MAP(S3C2412_DMAREQSEL_SPI1TX),
+                .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
+                .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
+        },
+        [DMACH_UART0] = {
+                .name           = "uart0",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART0_0),
+                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
+        },
+        [DMACH_UART1] = {
+                .name           = "uart1",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART1_0),
+                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
+        },
+        [DMACH_UART2] = {
+                .name           = "uart2",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART2_0),
+                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
+        },
+        [DMACH_UART0_SRC2] = {
+                .name           = "uart0",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART0_1),
+                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
+        },
+        [DMACH_UART1_SRC2] = {
+                .name           = "uart1",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART1_1),
+                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
+        },
+        [DMACH_UART2_SRC2] = {
+                .name           = "uart2",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART2_1),
+                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
+        },
+        [DMACH_TIMER] = {
+                .name           = "timer",
+                .channels       = MAP(S3C2412_DMAREQSEL_TIMER),
+        },
+        [DMACH_I2S_IN] = {
+                .name           = "i2s-sdi",
+                .channels       = MAP(S3C2412_DMAREQSEL_I2SRX),
+                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
+        },
+        [DMACH_I2S_OUT] = {
+                .name           = "i2s-sdo",
+                .channels       = MAP(S3C2412_DMAREQSEL_I2STX),
+                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
+        },
+        [DMACH_USB_EP1] = {
+                .name           = "usb-ep1",
+                .channels       = MAP(S3C2412_DMAREQSEL_USBEP1),
+        },
+        [DMACH_USB_EP2] = {
+                .name           = "usb-ep2",
+                .channels       = MAP(S3C2412_DMAREQSEL_USBEP2),
+        },
+        [DMACH_USB_EP3] = {
+                .name           = "usb-ep3",
+                .channels       = MAP(S3C2412_DMAREQSEL_USBEP3),
+        },
+        [DMACH_USB_EP4] = {
+                .name           = "usb-ep4",
+                .channels       = MAP(S3C2412_DMAREQSEL_USBEP4),
+        },
+};
+
+static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
+                               struct s3c24xx_dma_map *map)
+{
+        writel(map->channels[0] | S3C2412_DMAREQSEL_HW,
+               chan->regs + S3C2412_DMA_DMAREQSEL);
+}
+
+static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
+        .select         = s3c2412_dma_select,
+        .dcon_mask      = 0,
+        .map            = s3c2412_dma_mappings,
+        .map_size       = ARRAY_SIZE(s3c2412_dma_mappings),
+};
+
+static int s3c2412_dma_add(struct sys_device *sysdev)
+{
+        return s3c24xx_dma_init_map(&s3c2412_dma_sel);
+}
+
+static struct sysdev_driver s3c2412_dma_driver = {
+        .add    = s3c2412_dma_add,
+};
+
+static int __init s3c2412_dma_init(void)
+{
+        return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
+}
+
+arch_initcall(s3c2412_dma_init);
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
new file mode 100644
index 000000000000..e89dbdcb1b7b
--- /dev/null
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -0,0 +1,133 @@
+/* linux/arch/arm/mach-s3c2412/irq.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/ptrace.h>
+#include <linux/sysdev.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/mach/irq.h>
+
+#include <asm/arch/regs-irq.h>
+#include <asm/arch/regs-gpio.h>
+
+#include <asm/plat-s3c24xx/cpu.h>
+#include <asm/plat-s3c24xx/irq.h>
+#include <asm/plat-s3c24xx/pm.h>
+
+/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
+ * having them turn up in both the INT* and the EINT* registers. Whilst
+ * both show the status, they both now need to be acked when the IRQs
+ * go off.
+*/
+
+static void
+s3c2412_irq_mask(unsigned int irqno)
+{
+        unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+        unsigned long mask;
+
+        mask = __raw_readl(S3C2410_INTMSK);
+        __raw_writel(mask | bitval, S3C2410_INTMSK);
+
+        mask = __raw_readl(S3C2412_EINTMASK);
+        __raw_writel(mask | bitval, S3C2412_EINTMASK);
+}
+
+static inline void
+s3c2412_irq_ack(unsigned int irqno)
+{
+        unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+
+        __raw_writel(bitval, S3C2412_EINTPEND);
+        __raw_writel(bitval, S3C2410_SRCPND);
+        __raw_writel(bitval, S3C2410_INTPND);
+}
+
+static inline void
+s3c2412_irq_maskack(unsigned int irqno)
+{
+        unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+        unsigned long mask;
+
+        mask = __raw_readl(S3C2410_INTMSK);
+        __raw_writel(mask|bitval, S3C2410_INTMSK);
+
+        mask = __raw_readl(S3C2412_EINTMASK);
+        __raw_writel(mask | bitval, S3C2412_EINTMASK);
+
+        __raw_writel(bitval, S3C2412_EINTPEND);
+        __raw_writel(bitval, S3C2410_SRCPND);
+        __raw_writel(bitval, S3C2410_INTPND);
+}
+
+static void
+s3c2412_irq_unmask(unsigned int irqno)
+{
+        unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+        unsigned long mask;
+
+        mask = __raw_readl(S3C2412_EINTMASK);
+        __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
+
+        mask = __raw_readl(S3C2410_INTMSK);
+        __raw_writel(mask & ~bitval, S3C2410_INTMSK);
+}
+
+static struct irq_chip s3c2412_irq_eint0t4 = {
+        .ack       = s3c2412_irq_ack,
+        .mask      = s3c2412_irq_mask,
+        .unmask    = s3c2412_irq_unmask,
+        .set_wake  = s3c_irq_wake,
+        .set_type  = s3c_irqext_type,
+};
+
+static int s3c2412_irq_add(struct sys_device *sysdev)
+{
+        unsigned int irqno;
+
+        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
+                set_irq_chip(irqno, &s3c2412_irq_eint0t4);
+                set_irq_handler(irqno, handle_edge_irq);
+                set_irq_flags(irqno, IRQF_VALID);
+        }
+
+        return 0;
+}
+
+static struct sysdev_driver s3c2412_irq_driver = {
+        .add            = s3c2412_irq_add,
+        .suspend        = s3c24xx_irq_suspend,
+        .resume         = s3c24xx_irq_resume,
+};
+
+static int s3c2412_irq_init(void)
+{
+        return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver);
+}
+
+arch_initcall(s3c2412_irq_init);
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
new file mode 100644
index 000000000000..32b15617ef2a
--- /dev/null
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -0,0 +1,140 @@
+/* linux/arch/arm/mach-s3c2412/mach-smdk2413.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Thanks to Dimity Andric (TomTom) and Steven Ryu (Samsung) for the
+ * loans of SMDK2413 to work with.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/hardware/iomd.h>
+#include <asm/setup.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+//#include <asm/debug-ll.h>
+#include <asm/arch/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-lcd.h>
+
+#include <asm/arch/idle.h>
+#include <asm/arch/fb.h>
+
+#include <asm/plat-s3c24xx/s3c2410.h>
+#include <asm/plat-s3c24xx/s3c2412.h>
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+#include <asm/plat-s3c24xx/common-smdk.h>
+
+static struct map_desc smdk2413_iodesc[] __initdata = {
+};
+
+static struct s3c2410_uartcfg smdk2413_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        /* IR port */
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x43,
+                .ufcon       = 0x51,
+        }
+};
+
+static struct platform_device *smdk2413_devices[] __initdata = {
+        &s3c_device_usb,
+        //&s3c_device_lcd,
+        &s3c_device_wdt,
+        &s3c_device_i2c,
+        &s3c_device_iis,
+};
+
+static struct s3c24xx_board smdk2413_board __initdata = {
+        .devices       = smdk2413_devices,
+        .devices_count = ARRAY_SIZE(smdk2413_devices)
+};
+
+static void __init smdk2413_fixup(struct machine_desc *desc,
+                                  struct tag *tags, char **cmdline,
+                                  struct meminfo *mi)
+{
+        if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
+                mi->nr_banks=1;
+                mi->bank[0].start = 0x30000000;
+                mi->bank[0].size = SZ_64M;
+                mi->bank[0].node = 0;
+        }
+}
+
+static void __init smdk2413_map_io(void)
+{
+        s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
+        s3c24xx_set_board(&smdk2413_board);
+}
+
+static void __init smdk2413_machine_init(void)
+{
+        smdk_machine_init();
+}
+
+MACHINE_START(S3C2413, "S3C2413")
+        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .fixup          = smdk2413_fixup,
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = smdk2413_map_io,
+        .init_machine   = smdk2413_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
+
+MACHINE_START(SMDK2413, "SMDK2413")
+        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .fixup          = smdk2413_fixup,
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = smdk2413_map_io,
+        .init_machine   = smdk2413_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
new file mode 100644
index 000000000000..f1afb707ff16
--- /dev/null
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -0,0 +1,169 @@
+/* linux/arch/arm/mach-s3c2412/mach-vstms.c
+ *
+ * (C) 2006 Thomas Gleixner <tglx@linutronix.de>
+ *
+ * Derived from mach-smdk2413.c - (C) 2006 Simtec Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/hardware/iomd.h>
+#include <asm/setup.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-lcd.h>
+
+#include <asm/arch/idle.h>
+#include <asm/arch/fb.h>
+
+#include <asm/arch/nand.h>
+
+#include <asm/plat-s3c24xx/s3c2410.h>
+#include <asm/plat-s3c24xx/s3c2412.h>
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+
+static struct map_desc vstms_iodesc[] __initdata = {
+};
+
+static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        }
+};
+
+static struct mtd_partition vstms_nand_part[] = {
+        [0] = {
+                .name   = "Boot Agent",
+                .size   = 0x7C000,
+                .offset = 0,
+        },
+        [1] = {
+                .name   = "UBoot Config",
+                .offset = 0x7C000,
+                .size   = 0x4000,
+        },
+        [2] = {
+                .name   = "Kernel",
+                .offset = 0x80000,
+                .size   = 0x200000,
+        },
+        [3] = {
+                .name   = "RFS",
+                .offset = 0x280000,
+                .size   = 0x3d80000,
+        },
+};
+
+static struct s3c2410_nand_set vstms_nand_sets[] = {
+        [0] = {
+                .name           = "NAND",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(vstms_nand_part),
+                .partitions     = vstms_nand_part,
+        },
+};
+
+/* choose a set of timings which should suit most 512Mbit
+ * chips and beyond.
+*/
+
+static struct s3c2410_platform_nand vstms_nand_info = {
+        .tacls          = 20,
+        .twrph0         = 60,
+        .twrph1         = 20,
+        .nr_sets        = ARRAY_SIZE(vstms_nand_sets),
+        .sets           = vstms_nand_sets,
+};
+
+static struct platform_device *vstms_devices[] __initdata = {
+        &s3c_device_usb,
+        &s3c_device_wdt,
+        &s3c_device_i2c,
+        &s3c_device_iis,
+        &s3c_device_rtc,
+        &s3c_device_nand,
+};
+
+static struct s3c24xx_board vstms_board __initdata = {
+        .devices       = vstms_devices,
+        .devices_count = ARRAY_SIZE(vstms_devices)
+};
+
+static void __init vstms_fixup(struct machine_desc *desc,
+                                  struct tag *tags, char **cmdline,
+                                  struct meminfo *mi)
+{
+        if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
+                mi->nr_banks=1;
+                mi->bank[0].start = 0x30000000;
+                mi->bank[0].size = SZ_64M;
+                mi->bank[0].node = 0;
+        }
+}
+
+static void __init vstms_map_io(void)
+{
+        s3c_device_nand.dev.platform_data = &vstms_nand_info;
+
+        s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
+        s3c24xx_set_board(&vstms_board);
+}
+
+MACHINE_START(VSTMS, "VSTMS")
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .fixup          = vstms_fixup,
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = vstms_map_io,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
new file mode 100644
index 000000000000..8988dac388a9
--- /dev/null
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -0,0 +1,128 @@
+/* linux/arch/arm/mach-s3c2412/pm.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://armlinux.simtec.co.uk/.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+#include <linux/platform_device.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <asm/arch/regs-power.h>
+#include <asm/arch/regs-gpioj.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-dsc.h>
+
+#include <asm/plat-s3c24xx/cpu.h>
+#include <asm/plat-s3c24xx/pm.h>
+
+#include <asm/plat-s3c24xx/s3c2412.h>
+
+static void s3c2412_cpu_suspend(void)
+{
+        unsigned long tmp;
+
+        /* set our standby method to sleep */
+
+        tmp = __raw_readl(S3C2412_PWRCFG);
+        tmp |= S3C2412_PWRCFG_STANDBYWFI_SLEEP;
+        __raw_writel(tmp, S3C2412_PWRCFG);
+
+        /* issue the standby signal into the pm unit. Note, we
+         * issue a write-buffer drain just in case */
+
+        tmp = 0;
+
+        asm("b 1f\n\t"
+            ".align 5\n\t"
+            "1:\n\t"
+            "mcr p15, 0, %0, c7, c10, 4\n\t"
+            "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
+
+        /* we should never get past here */
+
+        panic("sleep resumed to originator?");
+}
+
+static void s3c2412_pm_prepare(void)
+{
+}
+
+static int s3c2412_pm_add(struct sys_device *sysdev)
+{
+        pm_cpu_prep = s3c2412_pm_prepare;
+        pm_cpu_sleep = s3c2412_cpu_suspend;
+
+        return 0;
+}
+
+static struct sleep_save s3c2412_sleep[] = {
+        SAVE_ITEM(S3C2412_DSC0),
+        SAVE_ITEM(S3C2412_DSC1),
+        SAVE_ITEM(S3C2413_GPJDAT),
+        SAVE_ITEM(S3C2413_GPJCON),
+        SAVE_ITEM(S3C2413_GPJUP),
+
+        /* save the PWRCFG to get back to original sleep method */
+
+        SAVE_ITEM(S3C2412_PWRCFG),
+
+        /* save the sleep configuration anyway, just in case these
+         * get damaged during wakeup */
+
+        SAVE_ITEM(S3C2412_GPBSLPCON),
+        SAVE_ITEM(S3C2412_GPCSLPCON),
+        SAVE_ITEM(S3C2412_GPDSLPCON),
+        SAVE_ITEM(S3C2412_GPESLPCON),
+        SAVE_ITEM(S3C2412_GPFSLPCON),
+        SAVE_ITEM(S3C2412_GPGSLPCON),
+        SAVE_ITEM(S3C2412_GPHSLPCON),
+        SAVE_ITEM(S3C2413_GPJSLPCON),
+};
+
+static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state)
+{
+        s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
+        return 0;
+}
+
+static int s3c2412_pm_resume(struct sys_device *dev)
+{
+        unsigned long tmp;
+
+        tmp = __raw_readl(S3C2412_PWRCFG);
+        tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
+        tmp |=  S3C2412_PWRCFG_STANDBYWFI_IDLE;
+        __raw_writel(tmp, S3C2412_PWRCFG);
+
+        s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
+        return 0;
+}
+
+static struct sysdev_driver s3c2412_pm_driver = {
+        .add            = s3c2412_pm_add,
+        .suspend        = s3c2412_pm_suspend,
+        .resume         = s3c2412_pm_resume,
+};
+
+static __init int s3c2412_pm_init(void)
+{
+        return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver);
+}
+
+arch_initcall(s3c2412_pm_init);
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
new file mode 100644
index 000000000000..aafe0bc593f1
--- /dev/null
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -0,0 +1,181 @@
+/* linux/arch/arm/mach-s3c2412/s3c2412.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://armlinux.simtec.co.uk/.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/proc-fns.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <asm/arch/idle.h>
+
+#include <asm/arch/regs-clock.h>
+#include <asm/arch/regs-serial.h>
+#include <asm/arch/regs-power.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-gpioj.h>
+#include <asm/arch/regs-dsc.h>
+
+#include <asm/plat-s3c24xx/s3c2412.h>
+#include <asm/plat-s3c24xx/cpu.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/pm.h>
+
+#ifndef CONFIG_CPU_S3C2412_ONLY
+void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
+
+static inline void s3c2412_init_gpio2(void)
+{
+        s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
+}
+#else
+#define s3c2412_init_gpio2() do { } while(0)
+#endif
+
+/* Initial IO mappings */
+
+static struct map_desc s3c2412_iodesc[] __initdata = {
+        IODESC_ENT(CLKPWR),
+        IODESC_ENT(LCD),
+        IODESC_ENT(TIMER),
+        IODESC_ENT(WATCHDOG),
+};
+
+/* uart registration process */
+
+void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
+
+        /* rename devices that are s3c2412/s3c2413 specific */
+        s3c_device_sdi.name  = "s3c2412-sdi";
+        s3c_device_lcd.name  = "s3c2412-lcd";
+        s3c_device_nand.name = "s3c2412-nand";
+}
+
+/* s3c2412_idle
+ *
+ * use the standard idle call by ensuring the idle mode
+ * in power config, then issuing the idle co-processor
+ * instruction
+*/
+
+static void s3c2412_idle(void)
+{
+        unsigned long tmp;
+
+        /* ensure our idle mode is to go to idle */
+
+        tmp = __raw_readl(S3C2412_PWRCFG);
+        tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
+        tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
+        __raw_writel(tmp, S3C2412_PWRCFG);
+
+        cpu_do_idle();
+}
+
+/* s3c2412_map_io
+ *
+ * register the standard cpu IO areas, and any passed in from the
+ * machine specific initialisation.
+*/
+
+void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
+{
+        /* move base of IO */
+
+        s3c2412_init_gpio2();
+
+        /* set our idle function */
+
+        s3c24xx_idle = s3c2412_idle;
+
+        /* register our io-tables */
+
+        iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
+        iotable_init(mach_desc, mach_size);
+}
+
+void __init s3c2412_init_clocks(int xtal)
+{
+        unsigned long tmp;
+        unsigned long fclk;
+        unsigned long hclk;
+        unsigned long pclk;
+
+        /* now we've got our machine bits initialised, work out what
+         * clocks we've got */
+
+        fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
+
+        tmp = __raw_readl(S3C2410_CLKDIVN);
+
+        /* work out clock scalings */
+
+        hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
+        hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1);
+        pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
+
+        /* print brieft summary of clocks, etc */
+
+        printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
+               print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
+
+        /* initialise the clocks here, to allow other things like the
+         * console to use them
+         */
+
+        s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
+        s3c2412_baseclk_add();
+}
+
+/* need to register class before we actually register the device, and
+ * we also need to ensure that it has been initialised before any of the
+ * drivers even try to use it (even if not on an s3c2412 based system)
+ * as a driver which may support both 2410 and 2440 may try and use it.
+*/
+
+struct sysdev_class s3c2412_sysclass = {
+        set_kset_name("s3c2412-core"),
+};
+
+static int __init s3c2412_core_init(void)
+{
+        return sysdev_class_register(&s3c2412_sysclass);
+}
+
+core_initcall(s3c2412_core_init);
+
+static struct sys_device s3c2412_sysdev = {
+        .cls            = &s3c2412_sysclass,
+};
+
+int __init s3c2412_init(void)
+{
+        printk("S3C2412: Initialising architecture\n");
+
+        return sysdev_register(&s3c2412_sysdev);
+}