diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2005-09-04 14:43:13 -0400 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2005-09-04 14:43:13 -0400 |
commit | 7801907b8c4a49f8ec033d13a938751114a97a55 (patch) | |
tree | c8f3cb07b2f224313519fbc7157d1f647f74d107 /arch/arm/mach-s3c2410 | |
parent | e24da5d316667a91b3a19b5761a211946ec649bb (diff) |
[ARM] Change irq_chip wake/type methods to set_wake/set_type
This is part of Thomas Gleixner's generic IRQ patch, which converts
ARM to use the generic IRQ subsystem. Here, we rename two of the
irq_chip methods - wake becomes set_wake, and type becomes set_type.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r-- | arch/arm/mach-s3c2410/irq.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 973a5fe6769c..67138797866a 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c | |||
@@ -184,14 +184,14 @@ struct irqchip s3c_irq_level_chip = { | |||
184 | .ack = s3c_irq_maskack, | 184 | .ack = s3c_irq_maskack, |
185 | .mask = s3c_irq_mask, | 185 | .mask = s3c_irq_mask, |
186 | .unmask = s3c_irq_unmask, | 186 | .unmask = s3c_irq_unmask, |
187 | .wake = s3c_irq_wake | 187 | .set_wake = s3c_irq_wake |
188 | }; | 188 | }; |
189 | 189 | ||
190 | static struct irqchip s3c_irq_chip = { | 190 | static struct irqchip s3c_irq_chip = { |
191 | .ack = s3c_irq_ack, | 191 | .ack = s3c_irq_ack, |
192 | .mask = s3c_irq_mask, | 192 | .mask = s3c_irq_mask, |
193 | .unmask = s3c_irq_unmask, | 193 | .unmask = s3c_irq_unmask, |
194 | .wake = s3c_irq_wake | 194 | .set_wake = s3c_irq_wake |
195 | }; | 195 | }; |
196 | 196 | ||
197 | /* S3C2410_EINTMASK | 197 | /* S3C2410_EINTMASK |
@@ -350,16 +350,16 @@ static struct irqchip s3c_irqext_chip = { | |||
350 | .mask = s3c_irqext_mask, | 350 | .mask = s3c_irqext_mask, |
351 | .unmask = s3c_irqext_unmask, | 351 | .unmask = s3c_irqext_unmask, |
352 | .ack = s3c_irqext_ack, | 352 | .ack = s3c_irqext_ack, |
353 | .type = s3c_irqext_type, | 353 | .set_type = s3c_irqext_type, |
354 | .wake = s3c_irqext_wake | 354 | .set_wake = s3c_irqext_wake |
355 | }; | 355 | }; |
356 | 356 | ||
357 | static struct irqchip s3c_irq_eint0t4 = { | 357 | static struct irqchip s3c_irq_eint0t4 = { |
358 | .ack = s3c_irq_ack, | 358 | .ack = s3c_irq_ack, |
359 | .mask = s3c_irq_mask, | 359 | .mask = s3c_irq_mask, |
360 | .unmask = s3c_irq_unmask, | 360 | .unmask = s3c_irq_unmask, |
361 | .wake = s3c_irq_wake, | 361 | .set_wake = s3c_irq_wake, |
362 | .type = s3c_irqext_type, | 362 | .set_type = s3c_irqext_type, |
363 | }; | 363 | }; |
364 | 364 | ||
365 | /* mask values for the parent registers for each of the interrupt types */ | 365 | /* mask values for the parent registers for each of the interrupt types */ |