Merge linux-2.6 with linux-acpi-2.6

10 files changed, 380 insertions, 57 deletions

diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index d4d03d0daaec..06807c6ee68a 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -2,6 +2,13 @@ if ARCH_S3C2410
 
 menu "S3C24XX Implementations"
 
+config MACH_ANUBIS
+        bool "Simtec Electronics ANUBIS"
+        select CPU_S3C2440
+        help
+          Say Y gere if you are using the Simtec Electronics ANUBIS
+          development system
+
 config ARCH_BAST
         bool "Simtec Electronics BAST (EB2410ITX)"
         select CPU_S3C2410
@@ -11,6 +18,14 @@ config ARCH_BAST
 
           Product page: <http://www.simtec.co.uk/products/EB2410ITX/>.
 
+config BAST_PC104_IRQ
+        bool "BAST PC104 IRQ support"
+        depends on ARCH_BAST
+        default y
+        help
+          Say Y here to enable the PC104 IRQ routing on the
+          Simtec BAST (EB2410ITX)
+
 config ARCH_H1940
         bool "IPAQ H1940"
         select CPU_S3C2410
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 55ed7c7e57da..b4f1e051c768 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -26,8 +26,13 @@ obj-$(CONFIG_CPU_S3C2440)  += s3c2440.o s3c2440-dsc.o
 obj-$(CONFIG_CPU_S3C2440)  += s3c2440-irq.o
 obj-$(CONFIG_CPU_S3C2440)  += s3c2440-clock.o
 
+# bast extras
+
+obj-$(CONFIG_BAST_PC104_IRQ)    += bast-irq.o
+
 # machine specific support
 
+obj-$(CONFIG_MACH_ANUBIS)       += mach-anubis.o
 obj-$(CONFIG_ARCH_BAST)         += mach-bast.o usb-simtec.o
 obj-$(CONFIG_ARCH_H1940)        += mach-h1940.o
 obj-$(CONFIG_MACH_N30)          += mach-n30.o
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 5e5bbe893cbb..fbbeb0553006 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/bast-irq.c
  *
- * Copyright (c) 2004 Simtec Electronics
+ * Copyright (c) 2003,2005 Simtec Electronics
  *   Ben Dooks <ben@simtec.co.uk>
  *
  * http://www.simtec.co.uk/products/EB2410ITX/
@@ -21,7 +21,8 @@
  *
  * Modifications:
  *     08-Jan-2003 BJD  Moved from central IRQ code
- */
+ *     21-Aug-2005 BJD  Fixed missing code and compile errors
+*/
 
 
 #include <linux/init.h>
@@ -30,12 +31,19 @@
 #include <linux/ptrace.h>
 #include <linux/sysdev.h>
 
+#include <asm/mach-types.h>
+
 #include <asm/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
 #include <asm/mach/irq.h>
-#include <asm/hardware/s3c2410/irq.h>
+
+#include <asm/arch/regs-irq.h>
+#include <asm/arch/bast-map.h>
+#include <asm/arch/bast-irq.h>
+
+#include "irq.h"
 
 #if 0
 #include <asm/debug-ll.h>
@@ -79,15 +87,15 @@ bast_pc104_mask(unsigned int irqno)
         temp = __raw_readb(BAST_VA_PC104_IRQMASK);
         temp &= ~bast_pc104_irqmasks[irqno];
         __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
-
-        if (temp == 0)
-                bast_extint_mask(IRQ_ISA);
 }
 
 static void
-bast_pc104_ack(unsigned int irqno)
+bast_pc104_maskack(unsigned int irqno)
 {
-        bast_extint_ack(IRQ_ISA);
+        struct irqdesc *desc = irq_desc + IRQ_ISA;
+
+        bast_pc104_mask(irqno);
+        desc->chip->ack(IRQ_ISA);
 }
 
 static void
@@ -98,14 +106,12 @@ bast_pc104_unmask(unsigned int irqno)
         temp = __raw_readb(BAST_VA_PC104_IRQMASK);
         temp |= bast_pc104_irqmasks[irqno];
         __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
-
-        bast_extint_unmask(IRQ_ISA);
 }
 
-static struct bast_pc104_chip = {
+static struct irqchip  bast_pc104_chip = {
         .mask        = bast_pc104_mask,
         .unmask      = bast_pc104_unmask,
-        .ack         = bast_pc104_ack
+        .ack         = bast_pc104_maskack
 };
 
 static void
@@ -119,14 +125,49 @@ bast_irq_pc104_demux(unsigned int irq,
 
         stat = __raw_readb(BAST_VA_PC104_IRQREQ) & 0xf;
 
-        for (i = 0; i < 4 && stat != 0; i++) {
-                if (stat & 1) {
-                        irqno = bast_pc104_irqs[i];
-                        desc = irq_desc + irqno;
+        if (unlikely(stat == 0)) {
+                /* ack if we get an irq with nothing (ie, startup) */
+
+                desc = irq_desc + IRQ_ISA;
+                desc->chip->ack(IRQ_ISA);
+        } else {
+                /* handle the IRQ */
+
+                for (i = 0; stat != 0; i++, stat >>= 1) {
+                        if (stat & 1) {
+                                irqno = bast_pc104_irqs[i];
 
-                        desc->handle(irqno, desc, regs);
+                                desc_handle_irq(irqno, irq_desc + irqno, regs);
+                        }
                 }
+        }
+}
 
-                stat >>= 1;
+static __init int bast_irq_init(void)
+{
+        unsigned int i;
+
+        if (machine_is_bast()) {
+                printk(KERN_INFO "BAST PC104 IRQ routing, (c) 2005 Simtec Electronics\n");
+
+                /* zap all the IRQs */
+
+                __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
+
+                set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
+
+                /* reigster our IRQs */
+
+                for (i = 0; i < 4; i++) {
+                        unsigned int irqno = bast_pc104_irqs[i];
+
+                        set_irq_chip(irqno, &bast_pc104_chip);
+                        set_irq_handler(irqno, do_level_IRQ);
+                        set_irq_flags(irqno, IRQF_VALID);
+                }
         }
+
+        return 0;
 }
+
+arch_initcall(bast_irq_init);
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 973a5fe6769c..66d8c068e940 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -184,14 +184,14 @@ struct irqchip s3c_irq_level_chip = {
         .ack       = s3c_irq_maskack,
         .mask      = s3c_irq_mask,
         .unmask    = s3c_irq_unmask,
-        .wake      = s3c_irq_wake
+        .set_wake          = s3c_irq_wake
 };
 
 static struct irqchip s3c_irq_chip = {
         .ack       = s3c_irq_ack,
         .mask      = s3c_irq_mask,
         .unmask    = s3c_irq_unmask,
-        .wake      = s3c_irq_wake
+        .set_wake          = s3c_irq_wake
 };
 
 /* S3C2410_EINTMASK
@@ -350,16 +350,16 @@ static struct irqchip s3c_irqext_chip = {
         .mask       = s3c_irqext_mask,
         .unmask     = s3c_irqext_unmask,
         .ack        = s3c_irqext_ack,
-        .type       = s3c_irqext_type,
-        .wake       = s3c_irqext_wake
+        .set_type    = s3c_irqext_type,
+        .set_wake    = s3c_irqext_wake
 };
 
 static struct irqchip s3c_irq_eint0t4 = {
         .ack       = s3c_irq_ack,
         .mask      = s3c_irq_mask,
         .unmask    = s3c_irq_unmask,
-        .wake      = s3c_irq_wake,
-        .type      = s3c_irqext_type,
+        .set_wake  = s3c_irq_wake,
+        .set_type  = s3c_irqext_type,
 };
 
 /* mask values for the parent registers for each of the interrupt types */
@@ -496,11 +496,11 @@ static void s3c_irq_demux_adc(unsigned int irq,
         if (subsrc != 0) {
                 if (subsrc & 1) {
                         mydesc = irq_desc + IRQ_TC;
-                        mydesc->handle( IRQ_TC, mydesc, regs);
+                        desc_handle_irq(IRQ_TC, mydesc, regs);
                 }
                 if (subsrc & 2) {
                         mydesc = irq_desc + IRQ_ADC;
-                        mydesc->handle(IRQ_ADC, mydesc, regs);
+                        desc_handle_irq(IRQ_ADC, mydesc, regs);
                 }
         }
 }
@@ -529,17 +529,17 @@ static void s3c_irq_demux_uart(unsigned int start,
                 desc = irq_desc + start;
 
                 if (subsrc & 1)
-                        desc->handle(start, desc, regs);
+                        desc_handle_irq(start, desc, regs);
 
                 desc++;
 
                 if (subsrc & 2)
-                        desc->handle(start+1, desc, regs);
+                        desc_handle_irq(start+1, desc, regs);
 
                 desc++;
 
                 if (subsrc & 4)
-                        desc->handle(start+2, desc, regs);
+                        desc_handle_irq(start+2, desc, regs);
         }
 }
 
diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c
new file mode 100644
index 000000000000..f87aa0b669ad
--- /dev/null
+++ b/arch/arm/mach-s3c2410/mach-anubis.c
@@ -0,0 +1,270 @@
+/* linux/arch/arm/mach-s3c2410/mach-anubis.c
+ *
+ * Copyright (c) 2003-2005 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *      02-May-2005 BJD  Copied from mach-bast.c
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/anubis-map.h>
+#include <asm/arch/anubis-irq.h>
+#include <asm/arch/anubis-cpld.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-mem.h>
+#include <asm/arch/regs-lcd.h>
+#include <asm/arch/nand.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include "clock.h"
+#include "devs.h"
+#include "cpu.h"
+
+#define COPYRIGHT ", (c) 2005 Simtec Electronics"
+
+static struct map_desc anubis_iodesc[] __initdata = {
+  /* ISA IO areas */
+
+  { (u32)S3C24XX_VA_ISA_BYTE, 0x0,         SZ_16M, MT_DEVICE },
+  { (u32)S3C24XX_VA_ISA_WORD, 0x0,         SZ_16M, MT_DEVICE },
+
+  /* we could possibly compress the next set down into a set of smaller tables
+   * pagetables, but that would mean using an L2 section, and it still means
+   * we cannot actually feed the same register to an LDR due to 16K spacing
+   */
+
+  /* CPLD control registers */
+
+  { (u32)ANUBIS_VA_CTRL1,       ANUBIS_PA_CTRL1,        SZ_4K, MT_DEVICE },
+  { (u32)ANUBIS_VA_CTRL2,       ANUBIS_PA_CTRL2,        SZ_4K, MT_DEVICE },
+
+  /* IDE drives */
+
+  { (u32)ANUBIS_IDEPRI,         S3C2410_CS3,            SZ_1M, MT_DEVICE },
+  { (u32)ANUBIS_IDEPRIAUX,      S3C2410_CS3+(1<<26),    SZ_1M, MT_DEVICE },
+
+  { (u32)ANUBIS_IDESEC,         S3C2410_CS4,            SZ_1M, MT_DEVICE },
+  { (u32)ANUBIS_IDESECAUX,      S3C2410_CS4+(1<<26),    SZ_1M, MT_DEVICE },
+};
+
+#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
+        [0] = {
+                .name           = "uclk",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        },
+        [1] = {
+                .name           = "pclk",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0.
+        }
+};
+
+
+static struct s3c2410_uartcfg anubis_uartcfgs[] = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+                .clocks      = anubis_serial_clocks,
+                .clocks_size = ARRAY_SIZE(anubis_serial_clocks)
+        },
+        [1] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+                .clocks      = anubis_serial_clocks,
+                .clocks_size = ARRAY_SIZE(anubis_serial_clocks)
+        },
+};
+
+/* NAND Flash on Anubis board */
+
+static int external_map[]   = { 2 };
+static int chip0_map[]      = { 0 };
+static int chip1_map[]      = { 1 };
+
+struct mtd_partition anubis_default_nand_part[] = {
+        [0] = {
+                .name   = "Boot Agent",
+                .size   = SZ_16K,
+                .offset = 0
+        },
+        [1] = {
+                .name   = "/boot",
+                .size   = SZ_4M - SZ_16K,
+                .offset = SZ_16K,
+        },
+        [2] = {
+                .name   = "user1",
+                .offset = SZ_4M,
+                .size   = SZ_32M - SZ_4M,
+        },
+        [3] = {
+                .name   = "user2",
+                .offset = SZ_32M,
+                .size   = MTDPART_SIZ_FULL,
+        }
+};
+
+/* the Anubis has 3 selectable slots for nand-flash, the two
+ * on-board chip areas, as well as the external slot.
+ *
+ * Note, there is no current hot-plug support for the External
+ * socket.
+*/
+
+static struct s3c2410_nand_set anubis_nand_sets[] = {
+        [1] = {
+                .name           = "External",
+                .nr_chips       = 1,
+                .nr_map         = external_map,
+                .nr_partitions  = ARRAY_SIZE(anubis_default_nand_part),
+                .partitions     = anubis_default_nand_part
+        },
+        [0] = {
+                .name           = "chip0",
+                .nr_chips       = 1,
+                .nr_map         = chip0_map,
+                .nr_partitions  = ARRAY_SIZE(anubis_default_nand_part),
+                .partitions     = anubis_default_nand_part
+        },
+        [2] = {
+                .name           = "chip1",
+                .nr_chips       = 1,
+                .nr_map         = chip1_map,
+                .nr_partitions  = ARRAY_SIZE(anubis_default_nand_part),
+                .partitions     = anubis_default_nand_part
+        },
+};
+
+static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
+{
+        unsigned int tmp;
+
+        slot = set->nr_map[slot] & 3;
+
+        pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
+                 slot, set, set->nr_map);
+
+        tmp = __raw_readb(ANUBIS_VA_CTRL1);
+        tmp &= ~ANUBIS_CTRL1_NANDSEL;
+        tmp |= slot;
+
+        pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
+
+        __raw_writeb(tmp, ANUBIS_VA_CTRL1);
+}
+
+static struct s3c2410_platform_nand anubis_nand_info = {
+        .tacls          = 25,
+        .twrph0         = 80,
+        .twrph1         = 80,
+        .nr_sets        = ARRAY_SIZE(anubis_nand_sets),
+        .sets           = anubis_nand_sets,
+        .select_chip    = anubis_nand_select,
+};
+
+
+/* Standard Anubis devices */
+
+static struct platform_device *anubis_devices[] __initdata = {
+        &s3c_device_usb,
+        &s3c_device_wdt,
+        &s3c_device_adc,
+        &s3c_device_i2c,
+        &s3c_device_rtc,
+        &s3c_device_nand,
+};
+
+static struct clk *anubis_clocks[] = {
+        &s3c24xx_dclk0,
+        &s3c24xx_dclk1,
+        &s3c24xx_clkout0,
+        &s3c24xx_clkout1,
+        &s3c24xx_uclk,
+};
+
+static struct s3c24xx_board anubis_board __initdata = {
+        .devices       = anubis_devices,
+        .devices_count = ARRAY_SIZE(anubis_devices),
+        .clocks        = anubis_clocks,
+        .clocks_count  = ARRAY_SIZE(anubis_clocks)
+};
+
+void __init anubis_map_io(void)
+{
+        /* initialise the clocks */
+
+        s3c24xx_dclk0.parent = NULL;
+        s3c24xx_dclk0.rate   = 12*1000*1000;
+
+        s3c24xx_dclk1.parent = NULL;
+        s3c24xx_dclk1.rate   = 24*1000*1000;
+
+        s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
+        s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
+
+        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
+
+        s3c_device_nand.dev.platform_data = &anubis_nand_info;
+
+        s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
+        s3c24xx_init_clocks(0);
+        s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
+        s3c24xx_set_board(&anubis_board);
+
+        /* ensure that the GPIO is setup */
+        s3c2410_gpio_setpin(S3C2410_GPA0, 1);
+}
+
+MACHINE_START(ANUBIS, "Simtec-Anubis")
+        /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
+        .phys_ram       = S3C2410_SDRAM_PA,
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .map_io         = anubis_map_io,
+        .init_irq       = s3c24xx_init_irq,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 79044d9bce38..66bf5bb2b3db 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -110,34 +110,24 @@ void __init n30_init_irq(void)
         s3c24xx_init_irq();
 }
 
-
-static int n30_usbstart_thread(void *unused)
-{
-        /* Turn off suspend on both USB ports, and switch the
-         * selectable USB port to USB device mode. */
-        writel(readl(S3C2410_MISCCR) & ~0x00003008, S3C2410_MISCCR);
-
-        /* Turn off the D+ pull up for 3 seconds so that the USB host
-         * at the other end will do a rescan of the USB bus.  */
-        s3c2410_gpio_setpin(S3C2410_GPB3, 0);
-
-        msleep_interruptible(3*HZ);
-
-        s3c2410_gpio_setpin(S3C2410_GPB3, 1);
-
-        return 0;
-}
-
+/* GPB3 is the line that controls the pull-up for the USB D+ line */
 
 void __init n30_init(void)
 {
         s3c_device_i2c.dev.platform_data = &n30_i2ccfg;
 
-        kthread_run(n30_usbstart_thread, NULL, "n30_usbstart");
+        /* Turn off suspend on both USB ports, and switch the
+         * selectable USB port to USB device mode. */
+
+        s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
+                              S3C2410_MISCCR_USBSUSPND0 |
+                              S3C2410_MISCCR_USBSUSPND1, 0x0);
 }
 
 MACHINE_START(N30, "Acer-N30")
-        /* Maintainer: Christer Weinigel <christer@weinigel.se>, Ben Dooks <ben-linux@fluff.org> */
+        /* Maintainer: Christer Weinigel <christer@weinigel.se>,
+                                Ben Dooks <ben-linux@fluff.org>
+        */
         .phys_ram       = S3C2410_SDRAM_PA,
         .phys_io        = S3C2410_PA_UART,
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
diff --git a/arch/arm/mach-s3c2410/pm-simtec.c b/arch/arm/mach-s3c2410/pm-simtec.c
index 2cb798832223..4c7ccef6c207 100644
--- a/arch/arm/mach-s3c2410/pm-simtec.c
+++ b/arch/arm/mach-s3c2410/pm-simtec.c
@@ -48,7 +48,7 @@ static __init int pm_simtec_init(void)
 
         /* check which machine we are running on */
 
-        if (!machine_is_bast() && !machine_is_vr1000())
+        if (!machine_is_bast() && !machine_is_vr1000() && !machine_is_anubis())
                 return 0;
 
         printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n");
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 13a48ee77484..fe57d966a34d 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -585,14 +585,16 @@ static int s3c2410_pm_enter(suspend_state_t state)
 
         s3c2410_pm_check_store();
 
-        // need to make some form of time-delta
-
         /* send the cpu to sleep... */
 
         __raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */
 
         s3c2410_cpu_suspend(regs_save);
 
+        /* restore the cpu state */
+
+        cpu_init();
+
         /* unset the return-from-sleep flag, to ensure reset */
 
         tmp = __raw_readl(S3C2410_GSTATUS2);
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
index 7cb9912242a3..278d0044c85d 100644
--- a/arch/arm/mach-s3c2410/s3c2440-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2440-irq.c
@@ -64,11 +64,11 @@ static void s3c_irq_demux_wdtac97(unsigned int irq,
         if (subsrc != 0) {
                 if (subsrc & 1) {
                         mydesc = irq_desc + IRQ_S3C2440_WDT;
-                        mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs);
+                        desc_handle_irq(IRQ_S3C2440_WDT, mydesc, regs);
                 }
                 if (subsrc & 2) {
                         mydesc = irq_desc + IRQ_S3C2440_AC97;
-                        mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs);
+                        desc_handle_irq(IRQ_S3C2440_AC97, mydesc, regs);
                 }
         }
 }
@@ -122,11 +122,11 @@ static void s3c_irq_demux_cam(unsigned int irq,
         if (subsrc != 0) {
                 if (subsrc & 1) {
                         mydesc = irq_desc + IRQ_S3C2440_CAM_C;
-                        mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs);
+                        desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc, regs);
                 }
                 if (subsrc & 2) {
                         mydesc = irq_desc + IRQ_S3C2440_CAM_P;
-                        mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs);
+                        desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc, regs);
                 }
         }
 }
diff --git a/arch/arm/mach-s3c2410/time.c b/arch/arm/mach-s3c2410/time.c
index 765a3a9ae032..c0acfb2ad790 100644
--- a/arch/arm/mach-s3c2410/time.c
+++ b/arch/arm/mach-s3c2410/time.c
@@ -164,7 +164,7 @@ static void s3c2410_timer_setup (void)
 
         /* configure the system for whichever machine is in use */
 
-        if (machine_is_bast() || machine_is_vr1000()) {
+        if (machine_is_bast() || machine_is_vr1000() || machine_is_anubis()) {
                 /* timer is at 12MHz, scaler is 1 */
                 timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
                 tcnt = 12000000 / HZ;