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authorBen Dooks <ben-linux@fluff.org>2008-04-15 19:12:39 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-04-17 12:04:40 -0400
commitd96a980441a70168a8ead0a0f23c4c63725da5fa (patch)
tree098551e6498fa641caaff62e352d21d7d9383c84 /arch/arm/mach-s3c2410
parent1017be88d341c05adc8d790d8092781b7330dafd (diff)
[ARM] 4986/1: S3C24XX: Simtec machines need UCLK as parent to DCLK
All current Simtec designs source the DCLK outputs from the UPLL. This means the DCLK's parent must be set to UPLL so that anything enabling and disabling an UPLL sourced clock does not shutdown the DCLK due to missing open counts. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index b45fb65889d2..518727d0dfcc 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -592,10 +592,10 @@ static void __init bast_map_io(void)
592{ 592{
593 /* initialise the clocks */ 593 /* initialise the clocks */
594 594
595 s3c24xx_dclk0.parent = NULL; 595 s3c24xx_dclk0.parent = &clk_upll;
596 s3c24xx_dclk0.rate = 12*1000*1000; 596 s3c24xx_dclk0.rate = 12*1000*1000;
597 597
598 s3c24xx_dclk1.parent = NULL; 598 s3c24xx_dclk1.parent = &clk_upll;
599 s3c24xx_dclk1.rate = 24*1000*1000; 599 s3c24xx_dclk1.rate = 24*1000*1000;
600 600
601 s3c24xx_clkout0.parent = &s3c24xx_dclk0; 601 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 3aade7b78fe5..c56423373ff3 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -393,7 +393,7 @@ static void __init vr1000_map_io(void)
393{ 393{
394 /* initialise clock sources */ 394 /* initialise clock sources */
395 395
396 s3c24xx_dclk0.parent = NULL; 396 s3c24xx_dclk0.parent = &clk_upll;
397 s3c24xx_dclk0.rate = 12*1000*1000; 397 s3c24xx_dclk0.rate = 12*1000*1000;
398 398
399 s3c24xx_dclk1.parent = NULL; 399 s3c24xx_dclk1.parent = NULL;