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authorBen Dooks <ben-linux@fluff.org>2008-12-18 09:52:00 -0500
committerBen Dooks <ben-linux@fluff.org>2008-12-18 09:52:00 -0500
commitc6ad115876763e4f15055982ecb9579cb7abab5f (patch)
tree75d2b0f5f31540ff8a2dcdde9e0f087b25c68868 /arch/arm/mach-s3c2410
parent1d19fdba149f4db055902c30b27adfb7d1ead058 (diff)
parent28ab44c5be60a9b91021a7cc7b4e202775c04764 (diff)
Merge branch 'next-s3c24xx' into next-merged
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r--arch/arm/mach-s3c2410/Kconfig7
-rw-r--r--arch/arm/mach-s3c2410/Makefile1
-rw-r--r--arch/arm/mach-s3c2410/clock.c276
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-clock.h33
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h7
-rw-r--r--arch/arm/mach-s3c2410/include/mach/spi.h7
-rw-r--r--arch/arm/mach-s3c2410/include/mach/timex.h26
-rw-r--r--arch/arm/mach-s3c2410/include/mach/vmalloc.h20
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c8
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c27
10 files changed, 33 insertions, 379 deletions
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 7315569fbfd7..63a30d1dd425 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -33,11 +33,6 @@ config S3C2410_GPIO
33 help 33 help
34 GPIO code for S3C2410 and similar processors 34 GPIO code for S3C2410 and similar processors
35 35
36config S3C2410_CLOCK
37 bool
38 help
39 Clock code for the S3C2410, and similar processors
40
41config SIMTEC_NOR 36config SIMTEC_NOR
42 bool 37 bool
43 help 38 help
@@ -85,6 +80,7 @@ config ARCH_BAST
85 select PM_SIMTEC if PM 80 select PM_SIMTEC if PM
86 select SIMTEC_NOR 81 select SIMTEC_NOR
87 select MACH_BAST_IDE 82 select MACH_BAST_IDE
83 select S3C24XX_DCLK
88 select ISA 84 select ISA
89 help 85 help
90 Say Y here if you are using the Simtec Electronics EB2410ITX 86 Say Y here if you are using the Simtec Electronics EB2410ITX
@@ -122,6 +118,7 @@ config MACH_TCT_HAMMER
122config MACH_VR1000 118config MACH_VR1000
123 bool "Thorcom VR1000" 119 bool "Thorcom VR1000"
124 select PM_SIMTEC if PM 120 select PM_SIMTEC if PM
121 select S3C24XX_DCLK
125 select SIMTEC_NOR 122 select SIMTEC_NOR
126 select MACH_BAST_IDE 123 select MACH_BAST_IDE
127 select CPU_S3C2410 124 select CPU_S3C2410
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 00f31f8c4e78..fca02f82711c 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
15obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o 15obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
16obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o 16obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
17obj-$(CONFIG_S3C2410_GPIO) += gpio.o 17obj-$(CONFIG_S3C2410_GPIO) += gpio.o
18obj-$(CONFIG_S3C2410_CLOCK) += clock.o
19 18
20# Machine support 19# Machine support
21 20
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
deleted file mode 100644
index 4e07943c1e29..000000000000
--- a/arch/arm/mach-s3c2410/clock.c
+++ /dev/null
@@ -1,276 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/clock.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410,S3C2440,S3C2442 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/list.h>
27#include <linux/errno.h>
28#include <linux/err.h>
29#include <linux/sysdev.h>
30#include <linux/clk.h>
31#include <linux/mutex.h>
32#include <linux/delay.h>
33#include <linux/serial_core.h>
34#include <linux/io.h>
35
36#include <asm/mach/map.h>
37
38#include <mach/hardware.h>
39
40#include <plat/regs-serial.h>
41#include <mach/regs-clock.h>
42#include <mach/regs-gpio.h>
43
44#include <plat/s3c2410.h>
45#include <plat/clock.h>
46#include <plat/cpu.h>
47
48int s3c2410_clkcon_enable(struct clk *clk, int enable)
49{
50 unsigned int clocks = clk->ctrlbit;
51 unsigned long clkcon;
52
53 clkcon = __raw_readl(S3C2410_CLKCON);
54
55 if (enable)
56 clkcon |= clocks;
57 else
58 clkcon &= ~clocks;
59
60 /* ensure none of the special function bits set */
61 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
62
63 __raw_writel(clkcon, S3C2410_CLKCON);
64
65 return 0;
66}
67
68static int s3c2410_upll_enable(struct clk *clk, int enable)
69{
70 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
71 unsigned long orig = clkslow;
72
73 if (enable)
74 clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
75 else
76 clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
77
78 __raw_writel(clkslow, S3C2410_CLKSLOW);
79
80 /* if we started the UPLL, then allow to settle */
81
82 if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
83 udelay(200);
84
85 return 0;
86}
87
88/* standard clock definitions */
89
90static struct clk init_clocks_disable[] = {
91 {
92 .name = "nand",
93 .id = -1,
94 .parent = &clk_h,
95 .enable = s3c2410_clkcon_enable,
96 .ctrlbit = S3C2410_CLKCON_NAND,
97 }, {
98 .name = "sdi",
99 .id = -1,
100 .parent = &clk_p,
101 .enable = s3c2410_clkcon_enable,
102 .ctrlbit = S3C2410_CLKCON_SDI,
103 }, {
104 .name = "adc",
105 .id = -1,
106 .parent = &clk_p,
107 .enable = s3c2410_clkcon_enable,
108 .ctrlbit = S3C2410_CLKCON_ADC,
109 }, {
110 .name = "i2c",
111 .id = -1,
112 .parent = &clk_p,
113 .enable = s3c2410_clkcon_enable,
114 .ctrlbit = S3C2410_CLKCON_IIC,
115 }, {
116 .name = "iis",
117 .id = -1,
118 .parent = &clk_p,
119 .enable = s3c2410_clkcon_enable,
120 .ctrlbit = S3C2410_CLKCON_IIS,
121 }, {
122 .name = "spi",
123 .id = -1,
124 .parent = &clk_p,
125 .enable = s3c2410_clkcon_enable,
126 .ctrlbit = S3C2410_CLKCON_SPI,
127 }
128};
129
130static struct clk init_clocks[] = {
131 {
132 .name = "lcd",
133 .id = -1,
134 .parent = &clk_h,
135 .enable = s3c2410_clkcon_enable,
136 .ctrlbit = S3C2410_CLKCON_LCDC,
137 }, {
138 .name = "gpio",
139 .id = -1,
140 .parent = &clk_p,
141 .enable = s3c2410_clkcon_enable,
142 .ctrlbit = S3C2410_CLKCON_GPIO,
143 }, {
144 .name = "usb-host",
145 .id = -1,
146 .parent = &clk_h,
147 .enable = s3c2410_clkcon_enable,
148 .ctrlbit = S3C2410_CLKCON_USBH,
149 }, {
150 .name = "usb-device",
151 .id = -1,
152 .parent = &clk_h,
153 .enable = s3c2410_clkcon_enable,
154 .ctrlbit = S3C2410_CLKCON_USBD,
155 }, {
156 .name = "timers",
157 .id = -1,
158 .parent = &clk_p,
159 .enable = s3c2410_clkcon_enable,
160 .ctrlbit = S3C2410_CLKCON_PWMT,
161 }, {
162 .name = "uart",
163 .id = 0,
164 .parent = &clk_p,
165 .enable = s3c2410_clkcon_enable,
166 .ctrlbit = S3C2410_CLKCON_UART0,
167 }, {
168 .name = "uart",
169 .id = 1,
170 .parent = &clk_p,
171 .enable = s3c2410_clkcon_enable,
172 .ctrlbit = S3C2410_CLKCON_UART1,
173 }, {
174 .name = "uart",
175 .id = 2,
176 .parent = &clk_p,
177 .enable = s3c2410_clkcon_enable,
178 .ctrlbit = S3C2410_CLKCON_UART2,
179 }, {
180 .name = "rtc",
181 .id = -1,
182 .parent = &clk_p,
183 .enable = s3c2410_clkcon_enable,
184 .ctrlbit = S3C2410_CLKCON_RTC,
185 }, {
186 .name = "watchdog",
187 .id = -1,
188 .parent = &clk_p,
189 .ctrlbit = 0,
190 }, {
191 .name = "usb-bus-host",
192 .id = -1,
193 .parent = &clk_usb_bus,
194 }, {
195 .name = "usb-bus-gadget",
196 .id = -1,
197 .parent = &clk_usb_bus,
198 },
199};
200
201/* s3c2410_baseclk_add()
202 *
203 * Add all the clocks used by the s3c2410 or compatible CPUs
204 * such as the S3C2440 and S3C2442.
205 *
206 * We cannot use a system device as we are needed before any
207 * of the init-calls that initialise the devices are actually
208 * done.
209*/
210
211int __init s3c2410_baseclk_add(void)
212{
213 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
214 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
215 struct clk *clkp;
216 struct clk *xtal;
217 int ret;
218 int ptr;
219
220 clk_upll.enable = s3c2410_upll_enable;
221
222 if (s3c24xx_register_clock(&clk_usb_bus) < 0)
223 printk(KERN_ERR "failed to register usb bus clock\n");
224
225 /* register clocks from clock array */
226
227 clkp = init_clocks;
228 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
229 /* ensure that we note the clock state */
230
231 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
232
233 ret = s3c24xx_register_clock(clkp);
234 if (ret < 0) {
235 printk(KERN_ERR "Failed to register clock %s (%d)\n",
236 clkp->name, ret);
237 }
238 }
239
240 /* We must be careful disabling the clocks we are not intending to
241 * be using at boot time, as subsystems such as the LCD which do
242 * their own DMA requests to the bus can cause the system to lockup
243 * if they where in the middle of requesting bus access.
244 *
245 * Disabling the LCD clock if the LCD is active is very dangerous,
246 * and therefore the bootloader should be careful to not enable
247 * the LCD clock if it is not needed.
248 */
249
250 /* install (and disable) the clocks we do not need immediately */
251
252 clkp = init_clocks_disable;
253 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
254
255 ret = s3c24xx_register_clock(clkp);
256 if (ret < 0) {
257 printk(KERN_ERR "Failed to register clock %s (%d)\n",
258 clkp->name, ret);
259 }
260
261 s3c2410_clkcon_enable(clkp, 0);
262 }
263
264 /* show the clock-slow value */
265
266 xtal = clk_get(NULL, "xtal");
267
268 printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
269 print_mhz(clk_get_rate(xtal) /
270 ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
271 (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
272 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
273 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
274
275 return 0;
276}
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
index b3f90aa78076..2a5d90e957fb 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
@@ -42,13 +42,6 @@
42#define S3C2410_CLKCON_IIS (1<<17) 42#define S3C2410_CLKCON_IIS (1<<17)
43#define S3C2410_CLKCON_SPI (1<<18) 43#define S3C2410_CLKCON_SPI (1<<18)
44 44
45#define S3C2410_PLLCON_MDIVSHIFT 12
46#define S3C2410_PLLCON_PDIVSHIFT 4
47#define S3C2410_PLLCON_SDIVSHIFT 0
48#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
49#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
50#define S3C2410_PLLCON_SDIVMASK 3
51
52/* DCLKCON register addresses in gpio.h */ 45/* DCLKCON register addresses in gpio.h */
53 46
54#define S3C2410_DCLKCON_DCLK0EN (1<<0) 47#define S3C2410_DCLKCON_DCLK0EN (1<<0)
@@ -76,32 +69,6 @@
76#define S3C2410_CLKSLOW_SLOWVAL(x) (x) 69#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
77#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) 70#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
78 71
79#ifndef __ASSEMBLY__
80
81#include <asm/div64.h>
82
83static inline unsigned int
84s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
85{
86 unsigned int mdiv, pdiv, sdiv;
87 uint64_t fvco;
88
89 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
90 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
91 sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
92
93 mdiv &= S3C2410_PLLCON_MDIVMASK;
94 pdiv &= S3C2410_PLLCON_PDIVMASK;
95 sdiv &= S3C2410_PLLCON_SDIVMASK;
96
97 fvco = (uint64_t)baseclk * (mdiv + 8);
98 do_div(fvco, (pdiv + 2) << sdiv);
99
100 return (unsigned int)fvco;
101}
102
103#endif /* __ASSEMBLY__ */
104
105#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) 72#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
106 73
107/* extra registers */ 74/* extra registers */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index 528080ceac44..321077613067 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -1053,13 +1053,6 @@
1053#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) 1053#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
1054#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) 1054#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
1055 1055
1056/* values for S3C2410_EXTINT0/1/2 */
1057#define S3C2410_EXTINT_LOWLEV (0x00)
1058#define S3C2410_EXTINT_HILEV (0x01)
1059#define S3C2410_EXTINT_FALLEDGE (0x02)
1060#define S3C2410_EXTINT_RISEEDGE (0x04)
1061#define S3C2410_EXTINT_BOTHEDGE (0x06)
1062
1063/* interrupt filtering conrrol for EINT16..EINT23 */ 1056/* interrupt filtering conrrol for EINT16..EINT23 */
1064#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) 1057#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
1065#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) 1058#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h
index 46d46f5b99f2..774f3adfe8ad 100644
--- a/arch/arm/mach-s3c2410/include/mach/spi.h
+++ b/arch/arm/mach-s3c2410/include/mach/spi.h
@@ -22,5 +22,12 @@ struct s3c2410_spi_info {
22 void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); 22 void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
23}; 23};
24 24
25/* Standard setup / suspend routines for SPI GPIO pins. */
26
27extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
28 int enable);
29
30extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
31 int enable);
25 32
26#endif /* __ASM_ARCH_SPI_H */ 33#endif /* __ASM_ARCH_SPI_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/mach-s3c2410/include/mach/timex.h
deleted file mode 100644
index 2a425ed0a7e0..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/timex.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - time parameters
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_TIMEX_H
14#define __ASM_ARCH_TIMEX_H
15
16/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
17 * a variable is useless. It seems as long as we make our timers an
18 * exact multiple of HZ, any value that makes a 1->1 correspondence
19 * for the time conversion functions to/from jiffies is acceptable.
20*/
21
22
23#define CLOCK_TICK_RATE 12000000
24
25
26#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
deleted file mode 100644
index 315b0078a34d..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/vmalloc.h
2 *
3 * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
4 *
5 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
6 * http://www.simtec.co.uk/products/SWLINUX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * S3C2410 vmalloc definition
13*/
14
15#ifndef __ASM_ARCH_VMALLOC_H
16#define __ASM_ARCH_VMALLOC_H
17
18#define VMALLOC_END (0xE0000000)
19
20#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 32d550fcff4d..836508b829bb 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -43,6 +43,7 @@
43#include <plat/clock.h> 43#include <plat/clock.h>
44#include <plat/devs.h> 44#include <plat/devs.h>
45#include <plat/cpu.h> 45#include <plat/cpu.h>
46#include <plat/pll.h>
46#include <plat/pm.h> 47#include <plat/pm.h>
47 48
48static struct map_desc h1940_iodesc[] __initdata = { 49static struct map_desc h1940_iodesc[] __initdata = {
@@ -223,10 +224,9 @@ static void __init h1940_init(void)
223 S3C2410_MISCCR_USBSUSPND0 | 224 S3C2410_MISCCR_USBSUSPND0 |
224 S3C2410_MISCCR_USBSUSPND1, 0x0); 225 S3C2410_MISCCR_USBSUSPND1, 0x0);
225 226
226 tmp = ( 227 tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
227 0x78 << S3C2410_PLLCON_MDIVSHIFT) 228 | (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
228 | (0x02 << S3C2410_PLLCON_PDIVSHIFT) 229 | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
229 | (0x03 << S3C2410_PLLCON_SDIVSHIFT);
230 writel(tmp, S3C2410_UPLLCON); 230 writel(tmp, S3C2410_UPLLCON);
231 231
232 platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); 232 platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index ac79b536c4c3..feb141b1f915 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -16,6 +16,7 @@
16#include <linux/list.h> 16#include <linux/list.h>
17#include <linux/timer.h> 17#include <linux/timer.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/clk.h>
19#include <linux/sysdev.h> 20#include <linux/sysdev.h>
20#include <linux/serial_core.h> 21#include <linux/serial_core.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
@@ -28,6 +29,8 @@
28#include <mach/hardware.h> 29#include <mach/hardware.h>
29#include <asm/irq.h> 30#include <asm/irq.h>
30 31
32#include <plat/cpu-freq.h>
33
31#include <mach/regs-clock.h> 34#include <mach/regs-clock.h>
32#include <plat/regs-serial.h> 35#include <plat/regs-serial.h>
33 36
@@ -35,6 +38,7 @@
35#include <plat/cpu.h> 38#include <plat/cpu.h>
36#include <plat/devs.h> 39#include <plat/devs.h>
37#include <plat/clock.h> 40#include <plat/clock.h>
41#include <plat/pll.h>
38 42
39/* Initial IO mappings */ 43/* Initial IO mappings */
40 44
@@ -59,25 +63,28 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
59 * machine specific initialisation. 63 * machine specific initialisation.
60*/ 64*/
61 65
62void __init s3c2410_map_io(struct map_desc *mach_desc, int mach_size) 66void __init s3c2410_map_io(void)
63{ 67{
64 /* register our io-tables */
65
66 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); 68 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
67 iotable_init(mach_desc, mach_size);
68} 69}
69 70
70void __init s3c2410_init_clocks(int xtal) 71void __init_or_cpufreq s3c2410_setup_clocks(void)
71{ 72{
73 struct clk *xtal_clk;
72 unsigned long tmp; 74 unsigned long tmp;
75 unsigned long xtal;
73 unsigned long fclk; 76 unsigned long fclk;
74 unsigned long hclk; 77 unsigned long hclk;
75 unsigned long pclk; 78 unsigned long pclk;
76 79
80 xtal_clk = clk_get(NULL, "xtal");
81 xtal = clk_get_rate(xtal_clk);
82 clk_put(xtal_clk);
83
77 /* now we've got our machine bits initialised, work out what 84 /* now we've got our machine bits initialised, work out what
78 * clocks we've got */ 85 * clocks we've got */
79 86
80 fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); 87 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
81 88
82 tmp = __raw_readl(S3C2410_CLKDIVN); 89 tmp = __raw_readl(S3C2410_CLKDIVN);
83 90
@@ -95,7 +102,13 @@ void __init s3c2410_init_clocks(int xtal)
95 * console to use them 102 * console to use them
96 */ 103 */
97 104
98 s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); 105 s3c24xx_setup_clocks(fclk, hclk, pclk);
106}
107
108void __init s3c2410_init_clocks(int xtal)
109{
110 s3c24xx_register_baseclocks(xtal);
111 s3c2410_setup_clocks();
99 s3c2410_baseclk_add(); 112 s3c2410_baseclk_add();
100} 113}
101 114
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 13:36:14 -0500