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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-03-26 18:44:43 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-03-26 18:44:43 -0400
commitf5f0e17a8475dee913f362510e6a8ab987d27b9f (patch)
treeebe44e7774400730f6c15cd5a84187113c274e3d /arch/arm/mach-s3c2410
parent2f3ec501ba1e1a68ab9d413f143bdc8f46417fc1 (diff)
parentfff94cd9f5527bbba13aa5ea5719d16531ca8e65 (diff)
Merge branch 'next-s3c-pm' of git://aeryn.fluff.org.uk/bjdooks/linux into devel
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-nrs.h23
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio.h3
-rw-r--r--arch/arm/mach-s3c2410/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h11
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c2
-rw-r--r--arch/arm/mach-s3c2410/pm.c13
7 files changed, 33 insertions, 23 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
new file mode 100644
index 000000000000..ce1ec69806a1
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -0,0 +1,23 @@
1/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2410 - GPIO bank numbering
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
15
16#define S3C2410_GPIO_BANKA (32*0)
17#define S3C2410_GPIO_BANKB (32*1)
18#define S3C2410_GPIO_BANKC (32*2)
19#define S3C2410_GPIO_BANKD (32*3)
20#define S3C2410_GPIO_BANKE (32*4)
21#define S3C2410_GPIO_BANKF (32*5)
22#define S3C2410_GPIO_BANKG (32*6)
23#define S3C2410_GPIO_BANKH (32*7)
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index 00476a573bbe..51a88cf9526b 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -23,3 +23,6 @@
23#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) 23#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
24 24
25#include <asm-generic/gpio.h> 25#include <asm-generic/gpio.h>
26#include <mach/gpio-nrs.h>
27
28#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 49efce8cd4a7..2a2384ffa7b1 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -80,7 +80,7 @@
80#define IRQ_EINT22 S3C2410_IRQ(50) 80#define IRQ_EINT22 S3C2410_IRQ(50)
81#define IRQ_EINT23 S3C2410_IRQ(51) 81#define IRQ_EINT23 S3C2410_IRQ(51)
82 82
83 83#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
84#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) 84#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
85 85
86#define IRQ_LCD_FIFO S3C2410_IRQ(52) 86#define IRQ_LCD_FIFO S3C2410_IRQ(52)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index 321077613067..35a03df473fc 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -14,16 +14,7 @@
14#ifndef __ASM_ARCH_REGS_GPIO_H 14#ifndef __ASM_ARCH_REGS_GPIO_H
15#define __ASM_ARCH_REGS_GPIO_H 15#define __ASM_ARCH_REGS_GPIO_H
16 16
17#define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) 17#include <mach/gpio-nrs.h>
18
19#define S3C2410_GPIO_BANKA (32*0)
20#define S3C2410_GPIO_BANKB (32*1)
21#define S3C2410_GPIO_BANKC (32*2)
22#define S3C2410_GPIO_BANKD (32*3)
23#define S3C2410_GPIO_BANKE (32*4)
24#define S3C2410_GPIO_BANKF (32*5)
25#define S3C2410_GPIO_BANKG (32*6)
26#define S3C2410_GPIO_BANKH (32*7)
27 18
28#ifdef CONFIG_CPU_S3C2400 19#ifdef CONFIG_CPU_S3C2400
29#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) 20#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x)
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 821a1668c3ac..7a7c4da4c256 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -203,7 +203,7 @@ static void __init h1940_map_io(void)
203#ifdef CONFIG_PM_H1940 203#ifdef CONFIG_PM_H1940
204 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); 204 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
205#endif 205#endif
206 s3c2410_pm_init(); 206 s3c_pm_init();
207} 207}
208 208
209static void __init h1940_init_irq(void) 209static void __init h1940_init_irq(void)
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 9678a53ceeb1..9f1ba9b63f70 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -355,7 +355,7 @@ static void __init qt2410_machine_init(void)
355 s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); 355 s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
356 356
357 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); 357 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
358 s3c2410_pm_init(); 358 s3c_pm_init();
359} 359}
360 360
361MACHINE_START(QT2410, "QT2410") 361MACHINE_START(QT2410, "QT2410")
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index a6970f613192..87fc481d92d4 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -37,21 +37,14 @@
37#include <plat/cpu.h> 37#include <plat/cpu.h>
38#include <plat/pm.h> 38#include <plat/pm.h>
39 39
40#ifdef CONFIG_S3C2410_PM_DEBUG
41extern void pm_dbg(const char *fmt, ...);
42#define DBG(fmt...) pm_dbg(fmt)
43#else
44#define DBG(fmt...) printk(KERN_DEBUG fmt)
45#endif
46
47static void s3c2410_pm_prepare(void) 40static void s3c2410_pm_prepare(void)
48{ 41{
49 /* ensure at least GSTATUS3 has the resume address */ 42 /* ensure at least GSTATUS3 has the resume address */
50 43
51 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3); 44 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
52 45
53 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); 46 S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
54 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); 47 S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
55 48
56 if (machine_is_h1940()) { 49 if (machine_is_h1940()) {
57 void *base = phys_to_virt(H1940_SUSPEND_CHECK); 50 void *base = phys_to_virt(H1940_SUSPEND_CHECK);