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authorBen Dooks <ben-linux@fluff.org>2007-02-11 12:31:01 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-11 12:36:09 -0500
commita21765a70ec06be175d3997320a83fa66fcc8955 (patch)
tree24bdbf437a9bd5b7c1af05898f5aa25dccf67fe9 /arch/arm/mach-s3c2410
parentd19494b187b20e363f9b434b9ceab4159ac88324 (diff)
[ARM] 4157/2: S3C24XX: move arch/arch/mach-s3c2410 into cpu components
The following patch and script moves the arch/arm/mach-s3c2410 directory into arch/arm/plat-s3c24xx for the generic core code and inti arch/arm/mach-s3c{cpu} for the cpu/machine support files Include directory include/asm-arm/plat-s3c24xx is added for the core include files. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r--arch/arm/mach-s3c2410/Kconfig356
-rw-r--r--arch/arm/mach-s3c2410/Makefile95
-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c2
-rw-r--r--arch/arm/mach-s3c2410/bast.h2
-rw-r--r--arch/arm/mach-s3c2410/clock.c565
-rw-r--r--arch/arm/mach-s3c2410/clock.h63
-rw-r--r--arch/arm/mach-s3c2410/common-smdk.c200
-rw-r--r--arch/arm/mach-s3c2410/common-smdk.h15
-rw-r--r--arch/arm/mach-s3c2410/cpu.c357
-rw-r--r--arch/arm/mach-s3c2410/cpu.h69
-rw-r--r--arch/arm/mach-s3c2410/devs.c585
-rw-r--r--arch/arm/mach-s3c2410/devs.h51
-rw-r--r--arch/arm/mach-s3c2410/dma.c1528
-rw-r--r--arch/arm/mach-s3c2410/dma.h45
-rw-r--r--arch/arm/mach-s3c2410/gpio.c165
-rw-r--r--arch/arm/mach-s3c2410/irq.c775
-rw-r--r--arch/arm/mach-s3c2410/irq.h107
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c6
-rw-r--r--arch/arm/mach-s3c2410/mach-anubis.c325
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c6
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c8
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c8
-rw-r--r--arch/arm/mach-s3c2410/mach-nexcoder.c158
-rw-r--r--arch/arm/mach-s3c2410/mach-osiris.c303
-rw-r--r--arch/arm/mach-s3c2410/mach-otom.c8
-rw-r--r--arch/arm/mach-s3c2410/mach-rx3715.c244
-rw-r--r--arch/arm/mach-s3c2410/mach-smdk2410.c8
-rw-r--r--arch/arm/mach-s3c2410/mach-smdk2413.c140
-rw-r--r--arch/arm/mach-s3c2410/mach-smdk2440.c208
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c6
-rw-r--r--arch/arm/mach-s3c2410/mach-vstms.c169
-rw-r--r--arch/arm/mach-s3c2410/pm-simtec.c66
-rw-r--r--arch/arm/mach-s3c2410/pm.c653
-rw-r--r--arch/arm/mach-s3c2410/pm.h73
-rw-r--r--arch/arm/mach-s3c2410/s3c2400-gpio.c42
-rw-r--r--arch/arm/mach-s3c2410/s3c2400.h31
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-clock.c276
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-dma.c161
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-gpio.c71
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-irq.c48
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-pm.c156
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-sleep.S68
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c8
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.h31
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-clock.c716
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-dma.c161
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-irq.c133
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-pm.c128
-rw-r--r--arch/arm/mach-s3c2410/s3c2412.c181
-rw-r--r--arch/arm/mach-s3c2410/s3c2412.h29
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-clock.c170
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-dma.c165
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-dsc.c54
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-irq.c130
-rw-r--r--arch/arm/mach-s3c2410/s3c2440.c52
-rw-r--r--arch/arm/mach-s3c2410/s3c2440.h17
-rw-r--r--arch/arm/mach-s3c2410/s3c2442-clock.c171
-rw-r--r--arch/arm/mach-s3c2410/s3c2442.c34
-rw-r--r--arch/arm/mach-s3c2410/s3c2442.h17
-rw-r--r--arch/arm/mach-s3c2410/s3c244x-irq.c146
-rw-r--r--arch/arm/mach-s3c2410/s3c244x.c184
-rw-r--r--arch/arm/mach-s3c2410/s3c244x.h25
-rw-r--r--arch/arm/mach-s3c2410/sleep.S151
-rw-r--r--arch/arm/mach-s3c2410/time.c262
-rw-r--r--arch/arm/mach-s3c2410/usb-simtec.c2
65 files changed, 573 insertions, 10616 deletions
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 0ab590ec4582..016b53f5d6fc 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -1,54 +1,51 @@
1if ARCH_S3C2410 1# arch/arm/mach-s3c2410/Kconfig
2#
3# Copyright 2007 Simtec Electronics
4#
5# Licensed under GPLv2
2 6
3menu "S3C24XX Implementations" 7config CPU_S3C2410
8 bool
9 depends on ARCH_S3C2410
10 select S3C2410_CLOCK
11 select S3C2410_GPIO
12 select S3C2410_PM if PM
13 help
14 Support for S3C2410 and S3C2410A family from the S3C24XX line
15 of Samsung Mobile CPUs.
4 16
5config MACH_AML_M5900 17config CPU_S3C2410_DMA
6 bool "AML M5900 Series" 18 bool
7 select CPU_S3C2410 19 depends on S3C2410_DMA && (CPU_S3C2410 || CPU_S3C2442)
8 select PM_SIMTEC if PM 20 default y if CPU_S3C2410 || CPU_S3C2442
9 help 21 help
10 Say Y here if you are using the American Microsystems M5900 Series 22 DMA device selection for S3C2410 and compatible CPUs
11 <http://www.amltd.com>
12 23
13config MACH_ANUBIS 24config S3C2410_PM
14 bool "Simtec Electronics ANUBIS" 25 bool
15 select CPU_S3C2440
16 select PM_SIMTEC if PM
17 help 26 help
18 Say Y here if you are using the Simtec Electronics ANUBIS 27 Power Management code common to S3C2410 and better
19 development system
20 28
21config MACH_OSIRIS 29config S3C2410_GPIO
22 bool "Simtec IM2440D20 (OSIRIS) module" 30 bool
23 select CPU_S3C2440
24 select PM_SIMTEC if PM
25 help 31 help
26 Say Y here if you are using the Simtec IM2440D20 module, also 32 GPIO code for S3C2410 and similar processors
27 known as the Osiris.
28 33
29config ARCH_BAST 34config S3C2410_CLOCK
30 bool "Simtec Electronics BAST (EB2410ITX)" 35 bool
31 select CPU_S3C2410
32 select PM_SIMTEC if PM
33 select ISA
34 help 36 help
35 Say Y here if you are using the Simtec Electronics EB2410ITX 37 Clock code for the S3C2410, and similar processors
36 development board (also known as BAST)
37 38
38 Product page: <http://www.simtec.co.uk/products/EB2410ITX/>.
39 39
40config BAST_PC104_IRQ 40menu "S3C2410 Machines"
41 bool "BAST PC104 IRQ support"
42 depends on ARCH_BAST
43 default y
44 help
45 Say Y here to enable the PC104 IRQ routing on the
46 Simtec BAST (EB2410ITX)
47 41
48config PM_H1940 42config ARCH_SMDK2410
49 bool 43 bool "SMDK2410/A9M2410"
44 select CPU_S3C2410
45 select MACH_SMDK
50 help 46 help
51 Internal node for H1940 and related PM 47 Say Y here if you are using the SMDK2410 or the derived module A9M2410
48 <http://www.fsforth.de>
52 49
53config ARCH_H1940 50config ARCH_H1940
54 bool "IPAQ H1940" 51 bool "IPAQ H1940"
@@ -57,7 +54,10 @@ config ARCH_H1940
57 help 54 help
58 Say Y here if you are using the HP IPAQ H1940 55 Say Y here if you are using the HP IPAQ H1940
59 56
60 <http://www.handhelds.org/projects/h1940.html>. 57config PM_H1940
58 bool
59 help
60 Internal node for H1940 and related PM
61 61
62config MACH_N30 62config MACH_N30
63 bool "Acer N30" 63 bool "Acer N30"
@@ -65,53 +65,36 @@ config MACH_N30
65 help 65 help
66 Say Y here if you are using the Acer N30 66 Say Y here if you are using the Acer N30
67 67
68 <http://zoo.weinigel.se/n30>. 68config ARCH_BAST
69 69 bool "Simtec Electronics BAST (EB2410ITX)"
70config MACH_SMDK
71 bool
72 help
73 Common machine code for SMDK2410 and SMDK2440
74
75config ARCH_SMDK2410
76 bool "SMDK2410/A9M2410"
77 select CPU_S3C2410 70 select CPU_S3C2410
78 select MACH_SMDK 71 select PM_SIMTEC if PM
72 select ISA
79 help 73 help
80 Say Y here if you are using the SMDK2410 or the derived module A9M2410 74 Say Y here if you are using the Simtec Electronics EB2410ITX
81 <http://www.fsforth.de> 75 development board (also known as BAST)
82 76
83config ARCH_S3C2440 77config MACH_OTOM
84 bool "SMDK2440" 78 bool "NexVision OTOM Board"
85 select CPU_S3C2440 79 select CPU_S3C2410
86 select MACH_SMDK
87 help 80 help
88 Say Y here if you are using the SMDK2440. 81 Say Y here if you are using the Nex Vision OTOM board
89
90config SMDK2440_CPU2440
91 bool "SMDK2440 with S3C2440 CPU module"
92 depends on ARCH_S3C2440
93 default y if ARCH_S3C2440
94 select CPU_S3C2440
95
96config SMDK2440_CPU2442
97 bool "SMDM2440 with S3C2442 CPU module"
98 depends on ARCH_S3C2440
99 select CPU_S3C2442
100 82
101config MACH_S3C2413 83config MACH_AML_M5900
102 bool 84 bool "AML M5900 Series"
85 select CPU_S3C2410
86 select PM_SIMTEC if PM
103 help 87 help
104 Internal node for S3C2413 version of SMDK2413, so that 88 Say Y here if you are using the American Microsystems M5900 Series
105 machine_is_s3c2413() will work when MACH_SMDK2413 is 89 <http://www.amltd.com>
106 selected
107 90
108config MACH_SMDK2413 91config BAST_PC104_IRQ
109 bool "SMDK2413" 92 bool "BAST PC104 IRQ support"
110 select CPU_S3C2412 93 depends on ARCH_BAST
111 select MACH_S3C2413 94 default y
112 select MACH_SMDK
113 help 95 help
114 Say Y here if you are using an SMDK2413 96 Say Y here to enable the PC104 IRQ routing on the
97 Simtec BAST (EB2410ITX)
115 98
116config MACH_VR1000 99config MACH_VR1000
117 bool "Thorcom VR1000" 100 bool "Thorcom VR1000"
@@ -120,223 +103,6 @@ config MACH_VR1000
120 help 103 help
121 Say Y here if you are using the Thorcom VR1000 board. 104 Say Y here if you are using the Thorcom VR1000 board.
122 105
123 This linux port is currently being maintained by Simtec, on behalf
124 of Thorcom. Any queries, please contact Thorcom first.
125
126config MACH_RX3715
127 bool "HP iPAQ rx3715"
128 select CPU_S3C2440
129 select PM_H1940 if PM
130 help
131 Say Y here if you are using the HP iPAQ rx3715.
132
133 See <http://www.handhelds.org/projects/rx3715.html> for more
134 information on this project
135
136config MACH_OTOM
137 bool "NexVision OTOM Board"
138 select CPU_S3C2410
139 help
140 Say Y here if you are using the Nex Vision OTOM board
141
142config MACH_NEXCODER_2440
143 bool "NexVision NEXCODER 2440 Light Board"
144 select CPU_S3C2440
145 help
146 Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
147
148config MACH_VSTMS
149 bool "VMSTMS"
150 select CPU_S3C2412
151 help
152 Say Y here if you are using an VSTMS board
153 106
154endmenu 107endmenu
155 108
156config S3C2410_CLOCK
157 bool
158 help
159 Clock code for the S3C2410, and similar processors
160
161config S3C2410_GPIO
162 bool
163 help
164 GPIO code for S3C2410 and similar processors
165
166config S3C2410_PM
167 bool
168 help
169 Power Management code common to S3C2410 and better
170
171config CPU_S3C2410_DMA
172 bool
173 depends on S3C2410_DMA && (CPU_S3C2410 || CPU_S3C2442)
174 default y if CPU_S3C2410 || CPU_S3C2442
175 help
176 DMA device selection for S3C2410 and compatible CPUs
177
178config CPU_S3C2410
179 bool
180 depends on ARCH_S3C2410
181 select S3C2410_CLOCK
182 select S3C2410_GPIO
183 select S3C2410_PM if PM
184 help
185 Support for S3C2410 and S3C2410A family from the S3C24XX line
186 of Samsung Mobile CPUs.
187
188# internal node to signify if we are only dealing with an S3C2412
189
190config CPU_S3C2412_ONLY
191 bool
192 depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
193 !CPU_S3C2440 && !CPU_S3C2442 && CPU_S3C2412
194 default y if CPU_S3C2412
195
196config S3C2412_PM
197 bool
198 help
199 Internal config node to apply S3C2412 power management
200
201config S3C2412_DMA
202 bool
203 depends on CPU_S3C2412
204 help
205 Internal config node for S3C2412 DMA support
206
207config CPU_S3C2412
208 bool
209 depends on ARCH_S3C2410
210 select S3C2412_PM if PM
211 select S3C2412_DMA if S3C2410_DMA
212 help
213 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
214
215config CPU_S3C244X
216 bool
217 depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
218 help
219 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
220
221config S3C2440_DMA
222 bool
223 depends on ARCH_S3C2410 && CPU_S3C24405B
224 help
225 Support for S3C2440 specific DMA code5A
226
227config CPU_S3C2440
228 bool
229 depends on ARCH_S3C2410
230 select S3C2410_CLOCK
231 select S3C2410_PM if PM
232 select S3C2410_GPIO
233 select S3C2440_DMA if S3C2410_DMA
234 select CPU_S3C244X
235 help
236 Support for S3C2440 Samsung Mobile CPU based systems.
237
238config CPU_S3C2442
239 bool
240 depends on ARCH_S3C2420
241 select S3C2410_CLOCK
242 select S3C2410_GPIO
243 select S3C2410_PM if PM
244 select CPU_S3C244X
245 help
246 Support for S3C2442 Samsung Mobile CPU based systems.
247
248comment "S3C2410 Boot"
249
250config S3C2410_BOOT_WATCHDOG
251 bool "S3C2410 Initialisation watchdog"
252 depends on ARCH_S3C2410 && S3C2410_WATCHDOG
253 help
254 Say y to enable the watchdog during the kernel decompression
255 stage. If the kernel fails to uncompress, then the watchdog
256 will trigger a reset and the system should restart.
257
258 Although this uses the same hardware unit as the kernel watchdog
259 driver, it is not a replacement for it. If you use this option,
260 you will have to use the watchdg driver to either stop the timeout
261 or restart it. If you do not, then your kernel will reboot after
262 startup.
263
264 The driver uses a fixed timeout value, so the exact time till the
265 system resets depends on the value of PCLK. The timeout on an
266 200MHz s3c2410 should be about 30 seconds.
267
268config S3C2410_BOOT_ERROR_RESET
269 bool "S3C2410 Reboot on decompression error"
270 depends on ARCH_S3C2410
271 help
272 Say y here to use the watchdog to reset the system if the
273 kernel decompressor detects an error during decompression.
274
275
276comment "S3C2410 Setup"
277
278config S3C2410_DMA
279 bool "S3C2410 DMA support"
280 depends on ARCH_S3C2410
281 help
282 S3C2410 DMA support. This is needed for drivers like sound which
283 use the S3C2410's DMA system to move data to and from the
284 peripheral blocks.
285
286config S3C2410_DMA_DEBUG
287 bool "S3C2410 DMA support debug"
288 depends on ARCH_S3C2410 && S3C2410_DMA
289 help
290 Enable debugging output for the DMA code. This option sends info
291 to the kernel log, at priority KERN_DEBUG.
292
293 Note, it is easy to create and fill the log buffer in a small
294 amount of time, as well as using an significant percentage of
295 the CPU time doing so.
296
297config S3C2410_PM_DEBUG
298 bool "S3C2410 PM Suspend debug"
299 depends on ARCH_S3C2410 && PM
300 help
301 Say Y here if you want verbose debugging from the PM Suspend and
302 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
303 for more information.
304
305config S3C2410_PM_CHECK
306 bool "S3C2410 PM Suspend Memory CRC"
307 depends on ARCH_S3C2410 && PM && CRC32
308 help
309 Enable the PM code's memory area checksum over sleep. This option
310 will generate CRCs of all blocks of memory, and store them before
311 going to sleep. The blocks are then checked on resume for any
312 errors.
313
314config S3C2410_PM_CHECK_CHUNKSIZE
315 int "S3C2410 PM Suspend CRC Chunksize (KiB)"
316 depends on ARCH_S3C2410 && PM && S3C2410_PM_CHECK
317 default 64
318 help
319 Set the chunksize in Kilobytes of the CRC for checking memory
320 corruption over suspend and resume. A smaller value will mean that
321 the CRC data block will take more memory, but wil identify any
322 faults with better precision.
323
324config PM_SIMTEC
325 bool
326 help
327 Common power management code for systems that are
328 compatible with the Simtec style of power management
329
330config S3C2410_LOWLEVEL_UART_PORT
331 int "S3C2410 UART to use for low-level messages"
332 default 0
333 help
334 Choice of which UART port to use for the low-level messages,
335 such as the `Uncompressing...` at start time. The value of
336 this configuration should be between zero and two. The port
337 must have been initialised by the boot-loader before use.
338
339 Note, this does not affect the port used by the debug messages,
340 which is a separate configuration.
341
342endif
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 1cc5febdaabd..b33ac5b84773 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -1,85 +1,30 @@
1 1# arch/arm/mach-s3c2410/Makefile
2# 2#
3# Makefile for the linux kernel. 3# Copyright 2007 Simtec Electronics
4# 4#
5# Licensed under GPLv2
5 6
6# Object file lists. 7obj-y :=
7 8obj-m :=
8obj-y := cpu.o irq.o time.o gpio.o clock.o devs.o 9obj-n :=
9obj-m := 10obj- :=
10obj-n :=
11obj- :=
12
13# DMA
14obj-$(CONFIG_S3C2410_DMA) += dma.o
15
16# S3C2400 support files
17obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o
18
19# S3C2410 support files
20 11
21obj-$(CONFIG_CPU_S3C2410) += s3c2410.o 12obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
22obj-$(CONFIG_CPU_S3C2410) += s3c2410-irq.o 13obj-$(CONFIG_CPU_S3C2410) += irq.o
23 14obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
24obj-$(CONFIG_S3C2410_PM) += s3c2410-pm.o s3c2410-sleep.o 15obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
25obj-$(CONFIG_S3C2410_GPIO) += s3c2410-gpio.o 16obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
26obj-$(CONFIG_CPU_S3C2410_DMA) += s3c2410-dma.o 17obj-$(CONFIG_S3C2410_GPIO) += gpio.o
27 18obj-$(CONFIG_S3C2410_CLOCK) += clock.o
28# Power Management support
29
30obj-$(CONFIG_PM) += pm.o sleep.o
31obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
32obj-$(CONFIG_PM_H1940) += pm-h1940.o
33
34# S3C2412 support
35obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
36obj-$(CONFIG_CPU_S3C2412) += s3c2412-irq.o
37obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o
38
39obj-$(CONFIG_S3C2412_PM) += s3c2412-pm.o
40obj-$(CONFIG_S3C2412_DMA) += s3c2412-dma.o
41
42#
43# S3C244X support
44
45obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
46obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o
47
48# Clock control
49
50obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
51
52# S3C2440 support
53 19
54obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o 20# Machine support
55obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o
56obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o
57obj-$(CONFIG_S3C2440_DMA) += s3c2440-dma.o
58 21
59# S3C2442 support 22obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o
60
61obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
62obj-$(CONFIG_CPU_S3C2442) += s3c2442-clock.o
63
64# bast extras
65
66obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o
67
68# machine specific support
69
70obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o
71obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o
72obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o
73obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o
74obj-$(CONFIG_ARCH_H1940) += mach-h1940.o 23obj-$(CONFIG_ARCH_H1940) += mach-h1940.o
24obj-$(CONFIG_PM_H1940) += pm-h1940.o
75obj-$(CONFIG_MACH_N30) += mach-n30.o 25obj-$(CONFIG_MACH_N30) += mach-n30.o
76obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o 26obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o
77obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o
78obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
79obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o
80obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o
81obj-$(CONFIG_MACH_OTOM) += mach-otom.o 27obj-$(CONFIG_MACH_OTOM) += mach-otom.o
82obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o 28obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o
83obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o 29obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o
84 30obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o
85obj-$(CONFIG_MACH_SMDK) += common-smdk.o \ No newline at end of file
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 379efe70778c..daeba427d781 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -39,7 +39,7 @@
39#include <asm/arch/bast-map.h> 39#include <asm/arch/bast-map.h>
40#include <asm/arch/bast-irq.h> 40#include <asm/arch/bast-irq.h>
41 41
42#include "irq.h" 42#include <asm/plat-s3c24xx/irq.h>
43 43
44#if 0 44#if 0
45#include <asm/debug-ll.h> 45#include <asm/debug-ll.h>
diff --git a/arch/arm/mach-s3c2410/bast.h b/arch/arm/mach-s3c2410/bast.h
index e5d03311752c..e98543742eb9 100644
--- a/arch/arm/mach-s3c2410/bast.h
+++ b/arch/arm/mach-s3c2410/bast.h
@@ -1,2 +1,2 @@
1 1/* linux/arch/arm/mach-s3c2410/bast.h
2extern void bast_init_irq(void); 2extern void bast_init_irq(void);
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index e13fb6778890..5b4831c4c1d8 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -1,15 +1,9 @@
1/* linux/arch/arm/mach-s3c2410/clock.c 1/* linux/arch/arm/mach-s3c2410/clock.c
2 * 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics 3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * S3C24XX Core clock control support 6 * S3C2410,S3C2440,S3C2442 Clock control support
7 *
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
9 **
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
12 *
13 * 7 *
14 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -32,418 +26,251 @@
32#include <linux/list.h> 26#include <linux/list.h>
33#include <linux/errno.h> 27#include <linux/errno.h>
34#include <linux/err.h> 28#include <linux/err.h>
35#include <linux/platform_device.h>
36#include <linux/sysdev.h> 29#include <linux/sysdev.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/clk.h> 30#include <linux/clk.h>
40#include <linux/mutex.h> 31#include <linux/mutex.h>
41#include <linux/delay.h> 32#include <linux/delay.h>
33#include <linux/serial_core.h>
34
35#include <asm/mach/map.h>
42 36
43#include <asm/hardware.h> 37#include <asm/hardware.h>
44#include <asm/irq.h>
45#include <asm/io.h> 38#include <asm/io.h>
46 39
40#include <asm/arch/regs-serial.h>
47#include <asm/arch/regs-clock.h> 41#include <asm/arch/regs-clock.h>
48#include <asm/arch/regs-gpio.h> 42#include <asm/arch/regs-gpio.h>
49 43
50#include "clock.h" 44#include <asm/plat-s3c24xx/s3c2410.h>
51#include "cpu.h" 45#include <asm/plat-s3c24xx/clock.h>
52 46#include <asm/plat-s3c24xx/cpu.h>
53/* clock information */
54 47
55static LIST_HEAD(clocks); 48int s3c2410_clkcon_enable(struct clk *clk, int enable)
56
57DEFINE_MUTEX(clocks_mutex);
58
59/* enable and disable calls for use with the clk struct */
60
61static int clk_null_enable(struct clk *clk, int enable)
62{ 49{
63 return 0; 50 unsigned int clocks = clk->ctrlbit;
64} 51 unsigned long clkcon;
65
66/* Clock API calls */
67 52
68struct clk *clk_get(struct device *dev, const char *id) 53 clkcon = __raw_readl(S3C2410_CLKCON);
69{
70 struct clk *p;
71 struct clk *clk = ERR_PTR(-ENOENT);
72 int idno;
73 54
74 if (dev == NULL || dev->bus != &platform_bus_type) 55 if (enable)
75 idno = -1; 56 clkcon |= clocks;
76 else 57 else
77 idno = to_platform_device(dev)->id; 58 clkcon &= ~clocks;
78
79 mutex_lock(&clocks_mutex);
80
81 list_for_each_entry(p, &clocks, list) {
82 if (p->id == idno &&
83 strcmp(id, p->name) == 0 &&
84 try_module_get(p->owner)) {
85 clk = p;
86 break;
87 }
88 }
89
90 /* check for the case where a device was supplied, but the
91 * clock that was being searched for is not device specific */
92
93 if (IS_ERR(clk)) {
94 list_for_each_entry(p, &clocks, list) {
95 if (p->id == -1 && strcmp(id, p->name) == 0 &&
96 try_module_get(p->owner)) {
97 clk = p;
98 break;
99 }
100 }
101 }
102 59
103 mutex_unlock(&clocks_mutex); 60 /* ensure none of the special function bits set */
104 return clk; 61 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
105}
106 62
107void clk_put(struct clk *clk) 63 __raw_writel(clkcon, S3C2410_CLKCON);
108{
109 module_put(clk->owner);
110}
111 64
112int clk_enable(struct clk *clk)
113{
114 if (IS_ERR(clk) || clk == NULL)
115 return -EINVAL;
116
117 clk_enable(clk->parent);
118
119 mutex_lock(&clocks_mutex);
120
121 if ((clk->usage++) == 0)
122 (clk->enable)(clk, 1);
123
124 mutex_unlock(&clocks_mutex);
125 return 0; 65 return 0;
126} 66}
127 67
128void clk_disable(struct clk *clk) 68static int s3c2410_upll_enable(struct clk *clk, int enable)
129{
130 if (IS_ERR(clk) || clk == NULL)
131 return;
132
133 mutex_lock(&clocks_mutex);
134
135 if ((--clk->usage) == 0)
136 (clk->enable)(clk, 0);
137
138 mutex_unlock(&clocks_mutex);
139 clk_disable(clk->parent);
140}
141
142
143unsigned long clk_get_rate(struct clk *clk)
144{
145 if (IS_ERR(clk))
146 return 0;
147
148 if (clk->rate != 0)
149 return clk->rate;
150
151 if (clk->get_rate != NULL)
152 return (clk->get_rate)(clk);
153
154 if (clk->parent != NULL)
155 return clk_get_rate(clk->parent);
156
157 return clk->rate;
158}
159
160long clk_round_rate(struct clk *clk, unsigned long rate)
161{
162 if (!IS_ERR(clk) && clk->round_rate)
163 return (clk->round_rate)(clk, rate);
164
165 return rate;
166}
167
168int clk_set_rate(struct clk *clk, unsigned long rate)
169{
170 int ret;
171
172 if (IS_ERR(clk))
173 return -EINVAL;
174
175 mutex_lock(&clocks_mutex);
176 ret = (clk->set_rate)(clk, rate);
177 mutex_unlock(&clocks_mutex);
178
179 return ret;
180}
181
182struct clk *clk_get_parent(struct clk *clk)
183{ 69{
184 return clk->parent; 70 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
185} 71 unsigned long orig = clkslow;
186
187int clk_set_parent(struct clk *clk, struct clk *parent)
188{
189 int ret = 0;
190
191 if (IS_ERR(clk))
192 return -EINVAL;
193
194 mutex_lock(&clocks_mutex);
195
196 if (clk->set_parent)
197 ret = (clk->set_parent)(clk, parent);
198
199 mutex_unlock(&clocks_mutex);
200
201 return ret;
202}
203
204EXPORT_SYMBOL(clk_get);
205EXPORT_SYMBOL(clk_put);
206EXPORT_SYMBOL(clk_enable);
207EXPORT_SYMBOL(clk_disable);
208EXPORT_SYMBOL(clk_get_rate);
209EXPORT_SYMBOL(clk_round_rate);
210EXPORT_SYMBOL(clk_set_rate);
211EXPORT_SYMBOL(clk_get_parent);
212EXPORT_SYMBOL(clk_set_parent);
213
214/* base clocks */
215
216struct clk clk_xtal = {
217 .name = "xtal",
218 .id = -1,
219 .rate = 0,
220 .parent = NULL,
221 .ctrlbit = 0,
222};
223
224struct clk clk_mpll = {
225 .name = "mpll",
226 .id = -1,
227};
228
229struct clk clk_upll = {
230 .name = "upll",
231 .id = -1,
232 .parent = NULL,
233 .ctrlbit = 0,
234};
235
236struct clk clk_f = {
237 .name = "fclk",
238 .id = -1,
239 .rate = 0,
240 .parent = &clk_mpll,
241 .ctrlbit = 0,
242};
243
244struct clk clk_h = {
245 .name = "hclk",
246 .id = -1,
247 .rate = 0,
248 .parent = NULL,
249 .ctrlbit = 0,
250};
251
252struct clk clk_p = {
253 .name = "pclk",
254 .id = -1,
255 .rate = 0,
256 .parent = NULL,
257 .ctrlbit = 0,
258};
259
260struct clk clk_usb_bus = {
261 .name = "usb-bus",
262 .id = -1,
263 .rate = 0,
264 .parent = &clk_upll,
265};
266
267/* clocks that could be registered by external code */
268
269static int s3c24xx_dclk_enable(struct clk *clk, int enable)
270{
271 unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
272 72
273 if (enable) 73 if (enable)
274 dclkcon |= clk->ctrlbit; 74 clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
275 else 75 else
276 dclkcon &= ~clk->ctrlbit; 76 clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
277 77
278 __raw_writel(dclkcon, S3C24XX_DCLKCON); 78 __raw_writel(clkslow, S3C2410_CLKSLOW);
279 79
280 return 0; 80 /* if we started the UPLL, then allow to settle */
281}
282 81
283static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) 82 if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
284{ 83 udelay(200);
285 unsigned long dclkcon;
286 unsigned int uclk;
287
288 if (parent == &clk_upll)
289 uclk = 1;
290 else if (parent == &clk_p)
291 uclk = 0;
292 else
293 return -EINVAL;
294
295 clk->parent = parent;
296
297 dclkcon = __raw_readl(S3C24XX_DCLKCON);
298
299 if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
300 if (uclk)
301 dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
302 else
303 dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
304 } else {
305 if (uclk)
306 dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
307 else
308 dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
309 }
310
311 __raw_writel(dclkcon, S3C24XX_DCLKCON);
312 84
313 return 0; 85 return 0;
314} 86}
315 87
316 88/* standard clock definitions */
317static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) 89
318{ 90static struct clk init_clocks_disable[] = {
319 unsigned long mask; 91 {
320 unsigned long source; 92 .name = "nand",
321 93 .id = -1,
322 /* calculate the MISCCR setting for the clock */ 94 .parent = &clk_h,
323 95 .enable = s3c2410_clkcon_enable,
324 if (parent == &clk_xtal) 96 .ctrlbit = S3C2410_CLKCON_NAND,
325 source = S3C2410_MISCCR_CLK0_MPLL; 97 }, {
326 else if (parent == &clk_upll) 98 .name = "sdi",
327 source = S3C2410_MISCCR_CLK0_UPLL; 99 .id = -1,
328 else if (parent == &clk_f) 100 .parent = &clk_p,
329 source = S3C2410_MISCCR_CLK0_FCLK; 101 .enable = s3c2410_clkcon_enable,
330 else if (parent == &clk_h) 102 .ctrlbit = S3C2410_CLKCON_SDI,
331 source = S3C2410_MISCCR_CLK0_HCLK; 103 }, {
332 else if (parent == &clk_p) 104 .name = "adc",
333 source = S3C2410_MISCCR_CLK0_PCLK; 105 .id = -1,
334 else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) 106 .parent = &clk_p,
335 source = S3C2410_MISCCR_CLK0_DCLK0; 107 .enable = s3c2410_clkcon_enable,
336 else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) 108 .ctrlbit = S3C2410_CLKCON_ADC,
337 source = S3C2410_MISCCR_CLK0_DCLK0; 109 }, {
338 else 110 .name = "i2c",
339 return -EINVAL; 111 .id = -1,
340 112 .parent = &clk_p,
341 clk->parent = parent; 113 .enable = s3c2410_clkcon_enable,
342 114 .ctrlbit = S3C2410_CLKCON_IIC,
343 if (clk == &s3c24xx_dclk0) 115 }, {
344 mask = S3C2410_MISCCR_CLK0_MASK; 116 .name = "iis",
345 else { 117 .id = -1,
346 source <<= 4; 118 .parent = &clk_p,
347 mask = S3C2410_MISCCR_CLK1_MASK; 119 .enable = s3c2410_clkcon_enable,
120 .ctrlbit = S3C2410_CLKCON_IIS,
121 }, {
122 .name = "spi",
123 .id = -1,
124 .parent = &clk_p,
125 .enable = s3c2410_clkcon_enable,
126 .ctrlbit = S3C2410_CLKCON_SPI,
348 } 127 }
349
350 s3c2410_modify_misccr(mask, source);
351 return 0;
352}
353
354/* external clock definitions */
355
356struct clk s3c24xx_dclk0 = {
357 .name = "dclk0",
358 .id = -1,
359 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
360 .enable = s3c24xx_dclk_enable,
361 .set_parent = s3c24xx_dclk_setparent,
362};
363
364struct clk s3c24xx_dclk1 = {
365 .name = "dclk1",
366 .id = -1,
367 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
368 .enable = s3c24xx_dclk_enable,
369 .set_parent = s3c24xx_dclk_setparent,
370}; 128};
371 129
372struct clk s3c24xx_clkout0 = { 130static struct clk init_clocks[] = {
373 .name = "clkout0", 131 {
374 .id = -1, 132 .name = "lcd",
375 .set_parent = s3c24xx_clkout_setparent, 133 .id = -1,
134 .parent = &clk_h,
135 .enable = s3c2410_clkcon_enable,
136 .ctrlbit = S3C2410_CLKCON_LCDC,
137 }, {
138 .name = "gpio",
139 .id = -1,
140 .parent = &clk_p,
141 .enable = s3c2410_clkcon_enable,
142 .ctrlbit = S3C2410_CLKCON_GPIO,
143 }, {
144 .name = "usb-host",
145 .id = -1,
146 .parent = &clk_h,
147 .enable = s3c2410_clkcon_enable,
148 .ctrlbit = S3C2410_CLKCON_USBH,
149 }, {
150 .name = "usb-device",
151 .id = -1,
152 .parent = &clk_h,
153 .enable = s3c2410_clkcon_enable,
154 .ctrlbit = S3C2410_CLKCON_USBD,
155 }, {
156 .name = "timers",
157 .id = -1,
158 .parent = &clk_p,
159 .enable = s3c2410_clkcon_enable,
160 .ctrlbit = S3C2410_CLKCON_PWMT,
161 }, {
162 .name = "uart",
163 .id = 0,
164 .parent = &clk_p,
165 .enable = s3c2410_clkcon_enable,
166 .ctrlbit = S3C2410_CLKCON_UART0,
167 }, {
168 .name = "uart",
169 .id = 1,
170 .parent = &clk_p,
171 .enable = s3c2410_clkcon_enable,
172 .ctrlbit = S3C2410_CLKCON_UART1,
173 }, {
174 .name = "uart",
175 .id = 2,
176 .parent = &clk_p,
177 .enable = s3c2410_clkcon_enable,
178 .ctrlbit = S3C2410_CLKCON_UART2,
179 }, {
180 .name = "rtc",
181 .id = -1,
182 .parent = &clk_p,
183 .enable = s3c2410_clkcon_enable,
184 .ctrlbit = S3C2410_CLKCON_RTC,
185 }, {
186 .name = "watchdog",
187 .id = -1,
188 .parent = &clk_p,
189 .ctrlbit = 0,
190 }, {
191 .name = "usb-bus-host",
192 .id = -1,
193 .parent = &clk_usb_bus,
194 }, {
195 .name = "usb-bus-gadget",
196 .id = -1,
197 .parent = &clk_usb_bus,
198 },
376}; 199};
377 200
378struct clk s3c24xx_clkout1 = { 201/* s3c2410_baseclk_add()
379 .name = "clkout1", 202 *
380 .id = -1, 203 * Add all the clocks used by the s3c2410 or compatible CPUs
381 .set_parent = s3c24xx_clkout_setparent, 204 * such as the S3C2440 and S3C2442.
382}; 205 *
383 206 * We cannot use a system device as we are needed before any
384struct clk s3c24xx_uclk = { 207 * of the init-calls that initialise the devices are actually
385 .name = "uclk", 208 * done.
386 .id = -1, 209*/
387};
388
389/* initialise the clock system */
390
391int s3c24xx_register_clock(struct clk *clk)
392{
393 clk->owner = THIS_MODULE;
394
395 if (clk->enable == NULL)
396 clk->enable = clk_null_enable;
397
398 /* add to the list of available clocks */
399
400 mutex_lock(&clocks_mutex);
401 list_add(&clk->list, &clocks);
402 mutex_unlock(&clocks_mutex);
403
404 return 0;
405}
406
407/* initalise all the clocks */
408 210
409int __init s3c24xx_setup_clocks(unsigned long xtal, 211int __init s3c2410_baseclk_add(void)
410 unsigned long fclk,
411 unsigned long hclk,
412 unsigned long pclk)
413{ 212{
414 printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); 213 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
214 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
215 struct clk *clkp;
216 struct clk *xtal;
217 int ret;
218 int ptr;
415 219
416 /* initialise the main system clocks */ 220 clk_upll.enable = s3c2410_upll_enable;
417 221
418 clk_xtal.rate = xtal; 222 if (s3c24xx_register_clock(&clk_usb_bus) < 0)
419 clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); 223 printk(KERN_ERR "failed to register usb bus clock\n");
420 224
421 clk_mpll.rate = fclk; 225 /* register clocks from clock array */
422 clk_h.rate = hclk;
423 clk_p.rate = pclk;
424 clk_f.rate = fclk;
425 226
426 /* assume uart clocks are correctly setup */ 227 clkp = init_clocks;
228 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
229 /* ensure that we note the clock state */
427 230
428 /* register our clocks */ 231 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
429 232
430 if (s3c24xx_register_clock(&clk_xtal) < 0) 233 ret = s3c24xx_register_clock(clkp);
431 printk(KERN_ERR "failed to register master xtal\n"); 234 if (ret < 0) {
235 printk(KERN_ERR "Failed to register clock %s (%d)\n",
236 clkp->name, ret);
237 }
238 }
432 239
433 if (s3c24xx_register_clock(&clk_mpll) < 0) 240 /* We must be careful disabling the clocks we are not intending to
434 printk(KERN_ERR "failed to register mpll clock\n"); 241 * be using at boot time, as subsytems such as the LCD which do
242 * their own DMA requests to the bus can cause the system to lockup
243 * if they where in the middle of requesting bus access.
244 *
245 * Disabling the LCD clock if the LCD is active is very dangerous,
246 * and therefore the bootloader should be careful to not enable
247 * the LCD clock if it is not needed.
248 */
249
250 /* install (and disable) the clocks we do not need immediately */
251
252 clkp = init_clocks_disable;
253 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
254
255 ret = s3c24xx_register_clock(clkp);
256 if (ret < 0) {
257 printk(KERN_ERR "Failed to register clock %s (%d)\n",
258 clkp->name, ret);
259 }
435 260
436 if (s3c24xx_register_clock(&clk_upll) < 0) 261 s3c2410_clkcon_enable(clkp, 0);
437 printk(KERN_ERR "failed to register upll clock\n"); 262 }
438 263
439 if (s3c24xx_register_clock(&clk_f) < 0) 264 /* show the clock-slow value */
440 printk(KERN_ERR "failed to register cpu fclk\n");
441 265
442 if (s3c24xx_register_clock(&clk_h) < 0) 266 xtal = clk_get(NULL, "xtal");
443 printk(KERN_ERR "failed to register cpu hclk\n");
444 267
445 if (s3c24xx_register_clock(&clk_p) < 0) 268 printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
446 printk(KERN_ERR "failed to register cpu pclk\n"); 269 print_mhz(clk_get_rate(xtal) /
270 ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
271 (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
272 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
273 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
447 274
448 return 0; 275 return 0;
449} 276}
diff --git a/arch/arm/mach-s3c2410/clock.h b/arch/arm/mach-s3c2410/clock.h
deleted file mode 100644
index 7f0ea03e1d49..000000000000
--- a/arch/arm/mach-s3c2410/clock.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * linux/arch/arm/mach-s3c2410/clock.h
3 *
4 * Copyright (c) 2004-2005 Simtec Electronics
5 * http://www.simtec.co.uk/products/SWLINUX/
6 * Written by Ben Dooks, <ben@simtec.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct clk {
14 struct list_head list;
15 struct module *owner;
16 struct clk *parent;
17 const char *name;
18 int id;
19 int usage;
20 unsigned long rate;
21 unsigned long ctrlbit;
22
23 int (*enable)(struct clk *, int enable);
24 int (*set_rate)(struct clk *c, unsigned long rate);
25 unsigned long (*get_rate)(struct clk *c);
26 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
27 int (*set_parent)(struct clk *c, struct clk *parent);
28};
29
30/* other clocks which may be registered by board support */
31
32extern struct clk s3c24xx_dclk0;
33extern struct clk s3c24xx_dclk1;
34extern struct clk s3c24xx_clkout0;
35extern struct clk s3c24xx_clkout1;
36extern struct clk s3c24xx_uclk;
37
38extern struct clk clk_usb_bus;
39
40/* core clock support */
41
42extern struct clk clk_f;
43extern struct clk clk_h;
44extern struct clk clk_p;
45extern struct clk clk_mpll;
46extern struct clk clk_upll;
47extern struct clk clk_xtal;
48
49/* exports for arch/arm/mach-s3c2410
50 *
51 * Please DO NOT use these outside of arch/arm/mach-s3c2410
52*/
53
54extern struct mutex clocks_mutex;
55
56extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
57
58extern int s3c24xx_register_clock(struct clk *clk);
59
60extern int s3c24xx_setup_clocks(unsigned long xtal,
61 unsigned long fclk,
62 unsigned long hclk,
63 unsigned long pclk);
diff --git a/arch/arm/mach-s3c2410/common-smdk.c b/arch/arm/mach-s3c2410/common-smdk.c
deleted file mode 100644
index a40eaa656177..000000000000
--- a/arch/arm/mach-s3c2410/common-smdk.c
+++ /dev/null
@@ -1,200 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/common-smdk.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Common code for SMDK2410 and SMDK2440 boards
7 *
8 * http://www.fluff.org/ben/smdk2440/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/nand.h>
25#include <linux/mtd/nand_ecc.h>
26#include <linux/mtd/partitions.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/irq.h>
31
32#include <asm/hardware.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35
36#include <asm/arch/regs-gpio.h>
37#include <asm/arch/leds-gpio.h>
38
39#include <asm/arch/nand.h>
40
41#include "common-smdk.h"
42#include "devs.h"
43#include "pm.h"
44
45/* LED devices */
46
47static struct s3c24xx_led_platdata smdk_pdata_led4 = {
48 .gpio = S3C2410_GPF4,
49 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
50 .name = "led4",
51 .def_trigger = "timer",
52};
53
54static struct s3c24xx_led_platdata smdk_pdata_led5 = {
55 .gpio = S3C2410_GPF5,
56 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
57 .name = "led5",
58 .def_trigger = "nand-disk",
59};
60
61static struct s3c24xx_led_platdata smdk_pdata_led6 = {
62 .gpio = S3C2410_GPF6,
63 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
64 .name = "led6",
65};
66
67static struct s3c24xx_led_platdata smdk_pdata_led7 = {
68 .gpio = S3C2410_GPF7,
69 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
70 .name = "led7",
71};
72
73static struct platform_device smdk_led4 = {
74 .name = "s3c24xx_led",
75 .id = 0,
76 .dev = {
77 .platform_data = &smdk_pdata_led4,
78 },
79};
80
81static struct platform_device smdk_led5 = {
82 .name = "s3c24xx_led",
83 .id = 1,
84 .dev = {
85 .platform_data = &smdk_pdata_led5,
86 },
87};
88
89static struct platform_device smdk_led6 = {
90 .name = "s3c24xx_led",
91 .id = 2,
92 .dev = {
93 .platform_data = &smdk_pdata_led6,
94 },
95};
96
97static struct platform_device smdk_led7 = {
98 .name = "s3c24xx_led",
99 .id = 3,
100 .dev = {
101 .platform_data = &smdk_pdata_led7,
102 },
103};
104
105/* NAND parititon from 2.4.18-swl5 */
106
107static struct mtd_partition smdk_default_nand_part[] = {
108 [0] = {
109 .name = "Boot Agent",
110 .size = SZ_16K,
111 .offset = 0,
112 },
113 [1] = {
114 .name = "S3C2410 flash partition 1",
115 .offset = 0,
116 .size = SZ_2M,
117 },
118 [2] = {
119 .name = "S3C2410 flash partition 2",
120 .offset = SZ_4M,
121 .size = SZ_4M,
122 },
123 [3] = {
124 .name = "S3C2410 flash partition 3",
125 .offset = SZ_8M,
126 .size = SZ_2M,
127 },
128 [4] = {
129 .name = "S3C2410 flash partition 4",
130 .offset = SZ_1M * 10,
131 .size = SZ_4M,
132 },
133 [5] = {
134 .name = "S3C2410 flash partition 5",
135 .offset = SZ_1M * 14,
136 .size = SZ_1M * 10,
137 },
138 [6] = {
139 .name = "S3C2410 flash partition 6",
140 .offset = SZ_1M * 24,
141 .size = SZ_1M * 24,
142 },
143 [7] = {
144 .name = "S3C2410 flash partition 7",
145 .offset = SZ_1M * 48,
146 .size = SZ_16M,
147 }
148};
149
150static struct s3c2410_nand_set smdk_nand_sets[] = {
151 [0] = {
152 .name = "NAND",
153 .nr_chips = 1,
154 .nr_partitions = ARRAY_SIZE(smdk_default_nand_part),
155 .partitions = smdk_default_nand_part,
156 },
157};
158
159/* choose a set of timings which should suit most 512Mbit
160 * chips and beyond.
161*/
162
163static struct s3c2410_platform_nand smdk_nand_info = {
164 .tacls = 20,
165 .twrph0 = 60,
166 .twrph1 = 20,
167 .nr_sets = ARRAY_SIZE(smdk_nand_sets),
168 .sets = smdk_nand_sets,
169};
170
171/* devices we initialise */
172
173static struct platform_device __initdata *smdk_devs[] = {
174 &s3c_device_nand,
175 &smdk_led4,
176 &smdk_led5,
177 &smdk_led6,
178 &smdk_led7,
179};
180
181void __init smdk_machine_init(void)
182{
183 /* Configure the LEDs (even if we have no LED support)*/
184
185 s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP);
186 s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP);
187 s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP);
188 s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP);
189
190 s3c2410_gpio_setpin(S3C2410_GPF4, 1);
191 s3c2410_gpio_setpin(S3C2410_GPF5, 1);
192 s3c2410_gpio_setpin(S3C2410_GPF6, 1);
193 s3c2410_gpio_setpin(S3C2410_GPF7, 1);
194
195 s3c_device_nand.dev.platform_data = &smdk_nand_info;
196
197 platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
198
199 s3c2410_pm_init();
200}
diff --git a/arch/arm/mach-s3c2410/common-smdk.h b/arch/arm/mach-s3c2410/common-smdk.h
deleted file mode 100644
index 0e3a3be330a3..000000000000
--- a/arch/arm/mach-s3c2410/common-smdk.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/common-smdk.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Common code for SMDK2410 and SMDK2440 boards
7 *
8 * http://www.fluff.org/ben/smdk2440/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern void smdk_machine_init(void);
diff --git a/arch/arm/mach-s3c2410/cpu.c b/arch/arm/mach-s3c2410/cpu.c
deleted file mode 100644
index ae1f5bb63f7a..000000000000
--- a/arch/arm/mach-s3c2410/cpu.c
+++ /dev/null
@@ -1,357 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/cpu.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX CPU Support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/serial_core.h>
30#include <linux/platform_device.h>
31
32#include <asm/hardware.h>
33#include <asm/irq.h>
34#include <asm/io.h>
35#include <asm/delay.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39
40#include <asm/arch/regs-gpio.h>
41#include <asm/arch/regs-serial.h>
42
43#include "cpu.h"
44#include "devs.h"
45#include "clock.h"
46#include "s3c2400.h"
47#include "s3c2410.h"
48#include "s3c2412.h"
49#include "s3c244x.h"
50#include "s3c2440.h"
51#include "s3c2442.h"
52
53struct cpu_table {
54 unsigned long idcode;
55 unsigned long idmask;
56 void (*map_io)(struct map_desc *mach_desc, int size);
57 void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
58 void (*init_clocks)(int xtal);
59 int (*init)(void);
60 const char *name;
61};
62
63/* table of supported CPUs */
64
65static const char name_s3c2400[] = "S3C2400";
66static const char name_s3c2410[] = "S3C2410";
67static const char name_s3c2412[] = "S3C2412";
68static const char name_s3c2440[] = "S3C2440";
69static const char name_s3c2442[] = "S3C2442";
70static const char name_s3c2410a[] = "S3C2410A";
71static const char name_s3c2440a[] = "S3C2440A";
72
73static struct cpu_table cpu_ids[] __initdata = {
74 {
75 .idcode = 0x32410000,
76 .idmask = 0xffffffff,
77 .map_io = s3c2410_map_io,
78 .init_clocks = s3c2410_init_clocks,
79 .init_uarts = s3c2410_init_uarts,
80 .init = s3c2410_init,
81 .name = name_s3c2410
82 },
83 {
84 .idcode = 0x32410002,
85 .idmask = 0xffffffff,
86 .map_io = s3c2410_map_io,
87 .init_clocks = s3c2410_init_clocks,
88 .init_uarts = s3c2410_init_uarts,
89 .init = s3c2410_init,
90 .name = name_s3c2410a
91 },
92 {
93 .idcode = 0x32440000,
94 .idmask = 0xffffffff,
95 .map_io = s3c244x_map_io,
96 .init_clocks = s3c244x_init_clocks,
97 .init_uarts = s3c244x_init_uarts,
98 .init = s3c2440_init,
99 .name = name_s3c2440
100 },
101 {
102 .idcode = 0x32440001,
103 .idmask = 0xffffffff,
104 .map_io = s3c244x_map_io,
105 .init_clocks = s3c244x_init_clocks,
106 .init_uarts = s3c244x_init_uarts,
107 .init = s3c2440_init,
108 .name = name_s3c2440a
109 },
110 {
111 .idcode = 0x32440aaa,
112 .idmask = 0xffffffff,
113 .map_io = s3c244x_map_io,
114 .init_clocks = s3c244x_init_clocks,
115 .init_uarts = s3c244x_init_uarts,
116 .init = s3c2442_init,
117 .name = name_s3c2442
118 },
119 {
120 .idcode = 0x32412001,
121 .idmask = 0xffffffff,
122 .map_io = s3c2412_map_io,
123 .init_clocks = s3c2412_init_clocks,
124 .init_uarts = s3c2412_init_uarts,
125 .init = s3c2412_init,
126 .name = name_s3c2412,
127 },
128 { /* a newer version of the s3c2412 */
129 .idcode = 0x32412003,
130 .idmask = 0xffffffff,
131 .map_io = s3c2412_map_io,
132 .init_clocks = s3c2412_init_clocks,
133 .init_uarts = s3c2412_init_uarts,
134 .init = s3c2412_init,
135 .name = name_s3c2412,
136 },
137 {
138 .idcode = 0x0, /* S3C2400 doesn't have an idcode */
139 .idmask = 0xffffffff,
140 .map_io = s3c2400_map_io,
141 .init_clocks = s3c2400_init_clocks,
142 .init_uarts = s3c2400_init_uarts,
143 .init = s3c2400_init,
144 .name = name_s3c2400
145 },
146};
147
148/* minimal IO mapping */
149
150static struct map_desc s3c_iodesc[] __initdata = {
151 IODESC_ENT(GPIO),
152 IODESC_ENT(IRQ),
153 IODESC_ENT(MEMCTRL),
154 IODESC_ENT(UART)
155};
156
157
158static struct cpu_table *
159s3c_lookup_cpu(unsigned long idcode)
160{
161 struct cpu_table *tab;
162 int count;
163
164 tab = cpu_ids;
165 for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
166 if ((idcode & tab->idmask) == tab->idcode)
167 return tab;
168 }
169
170 return NULL;
171}
172
173/* board information */
174
175static struct s3c24xx_board *board;
176
177void s3c24xx_set_board(struct s3c24xx_board *b)
178{
179 int i;
180
181 board = b;
182
183 if (b->clocks_count != 0) {
184 struct clk **ptr = b->clocks;
185
186 for (i = b->clocks_count; i > 0; i--, ptr++)
187 s3c24xx_register_clock(*ptr);
188 }
189}
190
191/* cpu information */
192
193static struct cpu_table *cpu;
194
195static unsigned long s3c24xx_read_idcode_v5(void)
196{
197#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
198 return __raw_readl(S3C2412_GSTATUS1);
199#else
200 return 1UL; /* don't look like an 2400 */
201#endif
202}
203
204static unsigned long s3c24xx_read_idcode_v4(void)
205{
206#ifndef CONFIG_CPU_S3C2400
207 return __raw_readl(S3C2410_GSTATUS1);
208#else
209 return 0UL;
210#endif
211}
212
213void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
214{
215 unsigned long idcode = 0x0;
216
217 /* initialise the io descriptors we need for initialisation */
218 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
219
220 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
221 idcode = s3c24xx_read_idcode_v5();
222 } else {
223 idcode = s3c24xx_read_idcode_v4();
224 }
225
226 cpu = s3c_lookup_cpu(idcode);
227
228 if (cpu == NULL) {
229 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
230 panic("Unknown S3C24XX CPU");
231 }
232
233 printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
234
235 if (cpu->map_io == NULL || cpu->init == NULL) {
236 printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
237 panic("Unsupported S3C24XX CPU");
238 }
239
240 (cpu->map_io)(mach_desc, size);
241}
242
243/* s3c24xx_init_clocks
244 *
245 * Initialise the clock subsystem and associated information from the
246 * given master crystal value.
247 *
248 * xtal = 0 -> use default PLL crystal value (normally 12MHz)
249 * != 0 -> PLL crystal value in Hz
250*/
251
252void __init s3c24xx_init_clocks(int xtal)
253{
254 if (xtal == 0)
255 xtal = 12*1000*1000;
256
257 if (cpu == NULL)
258 panic("s3c24xx_init_clocks: no cpu setup?\n");
259
260 if (cpu->init_clocks == NULL)
261 panic("s3c24xx_init_clocks: cpu has no clock init\n");
262 else
263 (cpu->init_clocks)(xtal);
264}
265
266/* uart management */
267
268static int nr_uarts __initdata = 0;
269
270static struct s3c2410_uartcfg uart_cfgs[3];
271
272/* s3c24xx_init_uartdevs
273 *
274 * copy the specified platform data and configuration into our central
275 * set of devices, before the data is thrown away after the init process.
276 *
277 * This also fills in the array passed to the serial driver for the
278 * early initialisation of the console.
279*/
280
281void __init s3c24xx_init_uartdevs(char *name,
282 struct s3c24xx_uart_resources *res,
283 struct s3c2410_uartcfg *cfg, int no)
284{
285 struct platform_device *platdev;
286 struct s3c2410_uartcfg *cfgptr = uart_cfgs;
287 struct s3c24xx_uart_resources *resp;
288 int uart;
289
290 memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
291
292 for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
293 platdev = s3c24xx_uart_src[cfgptr->hwport];
294
295 resp = res + cfgptr->hwport;
296
297 s3c24xx_uart_devs[uart] = platdev;
298
299 platdev->name = name;
300 platdev->resource = resp->resources;
301 platdev->num_resources = resp->nr_resources;
302
303 platdev->dev.platform_data = cfgptr;
304 }
305
306 nr_uarts = no;
307}
308
309void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
310{
311 if (cpu == NULL)
312 return;
313
314 if (cpu->init_uarts == NULL) {
315 printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
316 } else
317 (cpu->init_uarts)(cfg, no);
318}
319
320static int __init s3c_arch_init(void)
321{
322 int ret;
323
324 // do the correct init for cpu
325
326 if (cpu == NULL)
327 panic("s3c_arch_init: NULL cpu\n");
328
329 ret = (cpu->init)();
330 if (ret != 0)
331 return ret;
332
333 ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
334 if (ret != 0)
335 return ret;
336
337 if (board != NULL) {
338 struct platform_device **ptr = board->devices;
339 int i;
340
341 for (i = 0; i < board->devices_count; i++, ptr++) {
342 ret = platform_device_register(*ptr);
343
344 if (ret) {
345 printk(KERN_ERR "s3c24xx: failed to add board device %s (%d) @%p\n", (*ptr)->name, ret, *ptr);
346 }
347 }
348
349 /* mask any error, we may not need all these board
350 * devices */
351 ret = 0;
352 }
353
354 return ret;
355}
356
357arch_initcall(s3c_arch_init);
diff --git a/arch/arm/mach-s3c2410/cpu.h b/arch/arm/mach-s3c2410/cpu.h
deleted file mode 100644
index be42e4032a6d..000000000000
--- a/arch/arm/mach-s3c2410/cpu.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/* arch/arm/mach-s3c2410/cpu.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* todo - fix when rmk changes iodescs to use `void __iomem *` */
14
15#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
16
17#ifndef MHZ
18#define MHZ (1000*1000)
19#endif
20
21#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
22
23/* forward declaration */
24struct s3c24xx_uart_resources;
25struct platform_device;
26struct s3c2410_uartcfg;
27struct map_desc;
28
29/* core initialisation functions */
30
31extern void s3c24xx_init_irq(void);
32
33extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
34
35extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
36
37extern void s3c24xx_init_clocks(int xtal);
38
39extern void s3c24xx_init_uartdevs(char *name,
40 struct s3c24xx_uart_resources *res,
41 struct s3c2410_uartcfg *cfg, int no);
42
43/* the board structure is used at first initialsation time
44 * to get info such as the devices to register for this
45 * board. This is done because platfrom_add_devices() cannot
46 * be called from the map_io entry.
47*/
48
49struct s3c24xx_board {
50 struct platform_device **devices;
51 unsigned int devices_count;
52
53 struct clk **clocks;
54 unsigned int clocks_count;
55};
56
57extern void s3c24xx_set_board(struct s3c24xx_board *board);
58
59/* timer for 2410/2440 */
60
61struct sys_timer;
62extern struct sys_timer s3c24xx_timer;
63
64/* system device classes */
65
66extern struct sysdev_class s3c2410_sysclass;
67extern struct sysdev_class s3c2412_sysclass;
68extern struct sysdev_class s3c2440_sysclass;
69extern struct sysdev_class s3c2442_sysclass;
diff --git a/arch/arm/mach-s3c2410/devs.c b/arch/arm/mach-s3c2410/devs.c
deleted file mode 100644
index faccde2092d2..000000000000
--- a/arch/arm/mach-s3c2410/devs.c
+++ /dev/null
@@ -1,585 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/devs.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Base S3C24XX platform device definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26#include <asm/arch/fb.h>
27#include <asm/hardware.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30
31#include <asm/arch/regs-serial.h>
32
33#include "devs.h"
34#include "cpu.h"
35
36/* Serial port registrations */
37
38static struct resource s3c2410_uart0_resource[] = {
39 [0] = {
40 .start = S3C2410_PA_UART0,
41 .end = S3C2410_PA_UART0 + 0x3fff,
42 .flags = IORESOURCE_MEM,
43 },
44 [1] = {
45 .start = IRQ_S3CUART_RX0,
46 .end = IRQ_S3CUART_ERR0,
47 .flags = IORESOURCE_IRQ,
48 }
49};
50
51static struct resource s3c2410_uart1_resource[] = {
52 [0] = {
53 .start = S3C2410_PA_UART1,
54 .end = S3C2410_PA_UART1 + 0x3fff,
55 .flags = IORESOURCE_MEM,
56 },
57 [1] = {
58 .start = IRQ_S3CUART_RX1,
59 .end = IRQ_S3CUART_ERR1,
60 .flags = IORESOURCE_IRQ,
61 }
62};
63
64static struct resource s3c2410_uart2_resource[] = {
65 [0] = {
66 .start = S3C2410_PA_UART2,
67 .end = S3C2410_PA_UART2 + 0x3fff,
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = IRQ_S3CUART_RX2,
72 .end = IRQ_S3CUART_ERR2,
73 .flags = IORESOURCE_IRQ,
74 }
75};
76
77struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
78 [0] = {
79 .resources = s3c2410_uart0_resource,
80 .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
81 },
82 [1] = {
83 .resources = s3c2410_uart1_resource,
84 .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
85 },
86 [2] = {
87 .resources = s3c2410_uart2_resource,
88 .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
89 },
90};
91
92/* yart devices */
93
94static struct platform_device s3c24xx_uart_device0 = {
95 .id = 0,
96};
97
98static struct platform_device s3c24xx_uart_device1 = {
99 .id = 1,
100};
101
102static struct platform_device s3c24xx_uart_device2 = {
103 .id = 2,
104};
105
106struct platform_device *s3c24xx_uart_src[3] = {
107 &s3c24xx_uart_device0,
108 &s3c24xx_uart_device1,
109 &s3c24xx_uart_device2,
110};
111
112struct platform_device *s3c24xx_uart_devs[3] = {
113};
114
115/* USB Host Controller */
116
117static struct resource s3c_usb_resource[] = {
118 [0] = {
119 .start = S3C24XX_PA_USBHOST,
120 .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
121 .flags = IORESOURCE_MEM,
122 },
123 [1] = {
124 .start = IRQ_USBH,
125 .end = IRQ_USBH,
126 .flags = IORESOURCE_IRQ,
127 }
128};
129
130static u64 s3c_device_usb_dmamask = 0xffffffffUL;
131
132struct platform_device s3c_device_usb = {
133 .name = "s3c2410-ohci",
134 .id = -1,
135 .num_resources = ARRAY_SIZE(s3c_usb_resource),
136 .resource = s3c_usb_resource,
137 .dev = {
138 .dma_mask = &s3c_device_usb_dmamask,
139 .coherent_dma_mask = 0xffffffffUL
140 }
141};
142
143EXPORT_SYMBOL(s3c_device_usb);
144
145/* LCD Controller */
146
147static struct resource s3c_lcd_resource[] = {
148 [0] = {
149 .start = S3C24XX_PA_LCD,
150 .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
151 .flags = IORESOURCE_MEM,
152 },
153 [1] = {
154 .start = IRQ_LCD,
155 .end = IRQ_LCD,
156 .flags = IORESOURCE_IRQ,
157 }
158
159};
160
161static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
162
163struct platform_device s3c_device_lcd = {
164 .name = "s3c2410-lcd",
165 .id = -1,
166 .num_resources = ARRAY_SIZE(s3c_lcd_resource),
167 .resource = s3c_lcd_resource,
168 .dev = {
169 .dma_mask = &s3c_device_lcd_dmamask,
170 .coherent_dma_mask = 0xffffffffUL
171 }
172};
173
174EXPORT_SYMBOL(s3c_device_lcd);
175
176void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
177{
178 struct s3c2410fb_mach_info *npd;
179
180 npd = kmalloc(sizeof(*npd), GFP_KERNEL);
181 if (npd) {
182 memcpy(npd, pd, sizeof(*npd));
183 s3c_device_lcd.dev.platform_data = npd;
184 } else {
185 printk(KERN_ERR "no memory for LCD platform data\n");
186 }
187}
188
189/* NAND Controller */
190
191static struct resource s3c_nand_resource[] = {
192 [0] = {
193 .start = S3C2410_PA_NAND,
194 .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
195 .flags = IORESOURCE_MEM,
196 }
197};
198
199struct platform_device s3c_device_nand = {
200 .name = "s3c2410-nand",
201 .id = -1,
202 .num_resources = ARRAY_SIZE(s3c_nand_resource),
203 .resource = s3c_nand_resource,
204};
205
206EXPORT_SYMBOL(s3c_device_nand);
207
208/* USB Device (Gadget)*/
209
210static struct resource s3c_usbgadget_resource[] = {
211 [0] = {
212 .start = S3C24XX_PA_USBDEV,
213 .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
214 .flags = IORESOURCE_MEM,
215 },
216 [1] = {
217 .start = IRQ_USBD,
218 .end = IRQ_USBD,
219 .flags = IORESOURCE_IRQ,
220 }
221
222};
223
224struct platform_device s3c_device_usbgadget = {
225 .name = "s3c2410-usbgadget",
226 .id = -1,
227 .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
228 .resource = s3c_usbgadget_resource,
229};
230
231EXPORT_SYMBOL(s3c_device_usbgadget);
232
233/* Watchdog */
234
235static struct resource s3c_wdt_resource[] = {
236 [0] = {
237 .start = S3C24XX_PA_WATCHDOG,
238 .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
239 .flags = IORESOURCE_MEM,
240 },
241 [1] = {
242 .start = IRQ_WDT,
243 .end = IRQ_WDT,
244 .flags = IORESOURCE_IRQ,
245 }
246
247};
248
249struct platform_device s3c_device_wdt = {
250 .name = "s3c2410-wdt",
251 .id = -1,
252 .num_resources = ARRAY_SIZE(s3c_wdt_resource),
253 .resource = s3c_wdt_resource,
254};
255
256EXPORT_SYMBOL(s3c_device_wdt);
257
258/* I2C */
259
260static struct resource s3c_i2c_resource[] = {
261 [0] = {
262 .start = S3C24XX_PA_IIC,
263 .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
264 .flags = IORESOURCE_MEM,
265 },
266 [1] = {
267 .start = IRQ_IIC,
268 .end = IRQ_IIC,
269 .flags = IORESOURCE_IRQ,
270 }
271
272};
273
274struct platform_device s3c_device_i2c = {
275 .name = "s3c2410-i2c",
276 .id = -1,
277 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
278 .resource = s3c_i2c_resource,
279};
280
281EXPORT_SYMBOL(s3c_device_i2c);
282
283/* IIS */
284
285static struct resource s3c_iis_resource[] = {
286 [0] = {
287 .start = S3C24XX_PA_IIS,
288 .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
289 .flags = IORESOURCE_MEM,
290 }
291};
292
293static u64 s3c_device_iis_dmamask = 0xffffffffUL;
294
295struct platform_device s3c_device_iis = {
296 .name = "s3c2410-iis",
297 .id = -1,
298 .num_resources = ARRAY_SIZE(s3c_iis_resource),
299 .resource = s3c_iis_resource,
300 .dev = {
301 .dma_mask = &s3c_device_iis_dmamask,
302 .coherent_dma_mask = 0xffffffffUL
303 }
304};
305
306EXPORT_SYMBOL(s3c_device_iis);
307
308/* RTC */
309
310static struct resource s3c_rtc_resource[] = {
311 [0] = {
312 .start = S3C24XX_PA_RTC,
313 .end = S3C24XX_PA_RTC + 0xff,
314 .flags = IORESOURCE_MEM,
315 },
316 [1] = {
317 .start = IRQ_RTC,
318 .end = IRQ_RTC,
319 .flags = IORESOURCE_IRQ,
320 },
321 [2] = {
322 .start = IRQ_TICK,
323 .end = IRQ_TICK,
324 .flags = IORESOURCE_IRQ
325 }
326};
327
328struct platform_device s3c_device_rtc = {
329 .name = "s3c2410-rtc",
330 .id = -1,
331 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
332 .resource = s3c_rtc_resource,
333};
334
335EXPORT_SYMBOL(s3c_device_rtc);
336
337/* ADC */
338
339static struct resource s3c_adc_resource[] = {
340 [0] = {
341 .start = S3C24XX_PA_ADC,
342 .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
343 .flags = IORESOURCE_MEM,
344 },
345 [1] = {
346 .start = IRQ_TC,
347 .end = IRQ_TC,
348 .flags = IORESOURCE_IRQ,
349 },
350 [2] = {
351 .start = IRQ_ADC,
352 .end = IRQ_ADC,
353 .flags = IORESOURCE_IRQ,
354 }
355
356};
357
358struct platform_device s3c_device_adc = {
359 .name = "s3c2410-adc",
360 .id = -1,
361 .num_resources = ARRAY_SIZE(s3c_adc_resource),
362 .resource = s3c_adc_resource,
363};
364
365/* SDI */
366
367static struct resource s3c_sdi_resource[] = {
368 [0] = {
369 .start = S3C2410_PA_SDI,
370 .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
371 .flags = IORESOURCE_MEM,
372 },
373 [1] = {
374 .start = IRQ_SDI,
375 .end = IRQ_SDI,
376 .flags = IORESOURCE_IRQ,
377 }
378
379};
380
381struct platform_device s3c_device_sdi = {
382 .name = "s3c2410-sdi",
383 .id = -1,
384 .num_resources = ARRAY_SIZE(s3c_sdi_resource),
385 .resource = s3c_sdi_resource,
386};
387
388EXPORT_SYMBOL(s3c_device_sdi);
389
390/* SPI (0) */
391
392static struct resource s3c_spi0_resource[] = {
393 [0] = {
394 .start = S3C24XX_PA_SPI,
395 .end = S3C24XX_PA_SPI + 0x1f,
396 .flags = IORESOURCE_MEM,
397 },
398 [1] = {
399 .start = IRQ_SPI0,
400 .end = IRQ_SPI0,
401 .flags = IORESOURCE_IRQ,
402 }
403
404};
405
406static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
407
408struct platform_device s3c_device_spi0 = {
409 .name = "s3c2410-spi",
410 .id = 0,
411 .num_resources = ARRAY_SIZE(s3c_spi0_resource),
412 .resource = s3c_spi0_resource,
413 .dev = {
414 .dma_mask = &s3c_device_spi0_dmamask,
415 .coherent_dma_mask = 0xffffffffUL
416 }
417};
418
419EXPORT_SYMBOL(s3c_device_spi0);
420
421/* SPI (1) */
422
423static struct resource s3c_spi1_resource[] = {
424 [0] = {
425 .start = S3C24XX_PA_SPI + 0x20,
426 .end = S3C24XX_PA_SPI + 0x20 + 0x1f,
427 .flags = IORESOURCE_MEM,
428 },
429 [1] = {
430 .start = IRQ_SPI1,
431 .end = IRQ_SPI1,
432 .flags = IORESOURCE_IRQ,
433 }
434
435};
436
437static u64 s3c_device_spi1_dmamask = 0xffffffffUL;
438
439struct platform_device s3c_device_spi1 = {
440 .name = "s3c2410-spi",
441 .id = 1,
442 .num_resources = ARRAY_SIZE(s3c_spi1_resource),
443 .resource = s3c_spi1_resource,
444 .dev = {
445 .dma_mask = &s3c_device_spi1_dmamask,
446 .coherent_dma_mask = 0xffffffffUL
447 }
448};
449
450EXPORT_SYMBOL(s3c_device_spi1);
451
452/* pwm timer blocks */
453
454static struct resource s3c_timer0_resource[] = {
455 [0] = {
456 .start = S3C24XX_PA_TIMER + 0x0C,
457 .end = S3C24XX_PA_TIMER + 0x0C + 0xB,
458 .flags = IORESOURCE_MEM,
459 },
460 [1] = {
461 .start = IRQ_TIMER0,
462 .end = IRQ_TIMER0,
463 .flags = IORESOURCE_IRQ,
464 }
465
466};
467
468struct platform_device s3c_device_timer0 = {
469 .name = "s3c2410-timer",
470 .id = 0,
471 .num_resources = ARRAY_SIZE(s3c_timer0_resource),
472 .resource = s3c_timer0_resource,
473};
474
475EXPORT_SYMBOL(s3c_device_timer0);
476
477/* timer 1 */
478
479static struct resource s3c_timer1_resource[] = {
480 [0] = {
481 .start = S3C24XX_PA_TIMER + 0x18,
482 .end = S3C24XX_PA_TIMER + 0x23,
483 .flags = IORESOURCE_MEM,
484 },
485 [1] = {
486 .start = IRQ_TIMER1,
487 .end = IRQ_TIMER1,
488 .flags = IORESOURCE_IRQ,
489 }
490
491};
492
493struct platform_device s3c_device_timer1 = {
494 .name = "s3c2410-timer",
495 .id = 1,
496 .num_resources = ARRAY_SIZE(s3c_timer1_resource),
497 .resource = s3c_timer1_resource,
498};
499
500EXPORT_SYMBOL(s3c_device_timer1);
501
502/* timer 2 */
503
504static struct resource s3c_timer2_resource[] = {
505 [0] = {
506 .start = S3C24XX_PA_TIMER + 0x24,
507 .end = S3C24XX_PA_TIMER + 0x2F,
508 .flags = IORESOURCE_MEM,
509 },
510 [1] = {
511 .start = IRQ_TIMER2,
512 .end = IRQ_TIMER2,
513 .flags = IORESOURCE_IRQ,
514 }
515
516};
517
518struct platform_device s3c_device_timer2 = {
519 .name = "s3c2410-timer",
520 .id = 2,
521 .num_resources = ARRAY_SIZE(s3c_timer2_resource),
522 .resource = s3c_timer2_resource,
523};
524
525EXPORT_SYMBOL(s3c_device_timer2);
526
527/* timer 3 */
528
529static struct resource s3c_timer3_resource[] = {
530 [0] = {
531 .start = S3C24XX_PA_TIMER + 0x30,
532 .end = S3C24XX_PA_TIMER + 0x3B,
533 .flags = IORESOURCE_MEM,
534 },
535 [1] = {
536 .start = IRQ_TIMER3,
537 .end = IRQ_TIMER3,
538 .flags = IORESOURCE_IRQ,
539 }
540
541};
542
543struct platform_device s3c_device_timer3 = {
544 .name = "s3c2410-timer",
545 .id = 3,
546 .num_resources = ARRAY_SIZE(s3c_timer3_resource),
547 .resource = s3c_timer3_resource,
548};
549
550EXPORT_SYMBOL(s3c_device_timer3);
551
552#ifdef CONFIG_CPU_S3C2440
553
554/* Camif Controller */
555
556static struct resource s3c_camif_resource[] = {
557 [0] = {
558 .start = S3C2440_PA_CAMIF,
559 .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
560 .flags = IORESOURCE_MEM,
561 },
562 [1] = {
563 .start = IRQ_CAM,
564 .end = IRQ_CAM,
565 .flags = IORESOURCE_IRQ,
566 }
567
568};
569
570static u64 s3c_device_camif_dmamask = 0xffffffffUL;
571
572struct platform_device s3c_device_camif = {
573 .name = "s3c2440-camif",
574 .id = -1,
575 .num_resources = ARRAY_SIZE(s3c_camif_resource),
576 .resource = s3c_camif_resource,
577 .dev = {
578 .dma_mask = &s3c_device_camif_dmamask,
579 .coherent_dma_mask = 0xffffffffUL
580 }
581};
582
583EXPORT_SYMBOL(s3c_device_camif);
584
585#endif // CONFIG_CPU_S32440
diff --git a/arch/arm/mach-s3c2410/devs.h b/arch/arm/mach-s3c2410/devs.h
deleted file mode 100644
index 14fb0bade716..000000000000
--- a/arch/arm/mach-s3c2410/devs.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/* arch/arm/mach-s3c2410/devs.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2410 standard platform devices
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12#include <linux/platform_device.h>
13
14struct s3c24xx_uart_resources {
15 struct resource *resources;
16 unsigned long nr_resources;
17};
18
19extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
20
21extern struct platform_device *s3c24xx_uart_devs[];
22extern struct platform_device *s3c24xx_uart_src[];
23
24extern struct platform_device s3c_device_usb;
25extern struct platform_device s3c_device_lcd;
26extern struct platform_device s3c_device_wdt;
27extern struct platform_device s3c_device_i2c;
28extern struct platform_device s3c_device_iis;
29extern struct platform_device s3c_device_rtc;
30extern struct platform_device s3c_device_adc;
31extern struct platform_device s3c_device_sdi;
32
33extern struct platform_device s3c_device_spi0;
34extern struct platform_device s3c_device_spi1;
35
36extern struct platform_device s3c_device_nand;
37
38extern struct platform_device s3c_device_timer0;
39extern struct platform_device s3c_device_timer1;
40extern struct platform_device s3c_device_timer2;
41extern struct platform_device s3c_device_timer3;
42
43extern struct platform_device s3c_device_usbgadget;
44
45/* s3c2440 specific devices */
46
47#ifdef CONFIG_CPU_S3C2440
48
49extern struct platform_device s3c_device_camif;
50
51#endif
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index fa860e716b4f..22c613600caa 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s3c2410/dma.c 1/* linux/arch/arm/mach-s3c2410/dma.c
2 * 2 *
3 * Copyright (c) 2003-2005,2006 Simtec Electronics 3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * S3C2410 DMA core 6 * S3C2410 DMA selection
7 * 7 *
8 * http://armlinux.simtec.co.uk/ 8 * http://armlinux.simtec.co.uk/
9 * 9 *
@@ -12,1430 +12,150 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13*/ 13*/
14 14
15 15#include <linux/kernel.h>
16#ifdef CONFIG_S3C2410_DMA_DEBUG
17#define DEBUG
18#endif
19
20#include <linux/module.h>
21#include <linux/init.h> 16#include <linux/init.h>
22#include <linux/sched.h>
23#include <linux/spinlock.h>
24#include <linux/interrupt.h>
25#include <linux/sysdev.h> 17#include <linux/sysdev.h>
26#include <linux/slab.h> 18#include <linux/serial_core.h>
27#include <linux/errno.h>
28#include <linux/delay.h>
29 19
30#include <asm/system.h>
31#include <asm/irq.h>
32#include <asm/hardware.h>
33#include <asm/io.h>
34#include <asm/dma.h> 20#include <asm/dma.h>
35 21#include <asm/arch/dma.h>
36#include <asm/mach/dma.h> 22#include <asm/plat-s3c24xx/dma.h>
37#include <asm/arch/map.h> 23
38 24#include <asm/plat-s3c24xx/cpu.h>
39#include "dma.h" 25
40 26#include <asm/arch/regs-serial.h>
41/* io map for dma */ 27#include <asm/arch/regs-gpio.h>
42static void __iomem *dma_base; 28#include <asm/arch/regs-ac97.h>
43static struct kmem_cache *dma_kmem; 29#include <asm/arch/regs-mem.h>
44 30#include <asm/arch/regs-lcd.h>
45struct s3c24xx_dma_selection dma_sel; 31#include <asm/arch/regs-sdi.h>
46 32#include <asm/arch/regs-iis.h>
47/* dma channel state information */ 33#include <asm/arch/regs-spi.h>
48struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; 34
49 35static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
50/* debugging functions */ 36 [DMACH_XD0] = {
51 37 .name = "xdreq0",
52#define BUF_MAGIC (0xcafebabe) 38 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
53 39 },
54#define dmawarn(fmt...) printk(KERN_DEBUG fmt) 40 [DMACH_XD1] = {
55 41 .name = "xdreq1",
56#define dma_regaddr(chan, reg) ((chan)->regs + (reg)) 42 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
57 43 },
58#if 1 44 [DMACH_SDI] = {
59#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg)) 45 .name = "sdi",
60#else 46 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
61static inline void 47 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
62dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val) 48 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
63{ 49 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
64 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg); 50 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
65 writel(val, dma_regaddr(chan, reg)); 51 },
66} 52 [DMACH_SPI0] = {
67#endif 53 .name = "spi0",
68 54 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
69#define dma_rdreg(chan, reg) readl((chan)->regs + (reg)) 55 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
70 56 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
71/* captured register state for debug */ 57 },
72 58 [DMACH_SPI1] = {
73struct s3c2410_dma_regstate { 59 .name = "spi1",
74 unsigned long dcsrc; 60 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
75 unsigned long disrc; 61 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
76 unsigned long dstat; 62 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
77 unsigned long dcon; 63 },
78 unsigned long dmsktrig; 64 [DMACH_UART0] = {
65 .name = "uart0",
66 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
67 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
68 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
69 },
70 [DMACH_UART1] = {
71 .name = "uart1",
72 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
73 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
74 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
75 },
76 [DMACH_UART2] = {
77 .name = "uart2",
78 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
79 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
80 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
81 },
82 [DMACH_TIMER] = {
83 .name = "timer",
84 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
85 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
86 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
87 },
88 [DMACH_I2S_IN] = {
89 .name = "i2s-sdi",
90 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
91 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
92 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
93 },
94 [DMACH_I2S_OUT] = {
95 .name = "i2s-sdo",
96 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
97 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
98 },
99 [DMACH_USB_EP1] = {
100 .name = "usb-ep1",
101 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
102 },
103 [DMACH_USB_EP2] = {
104 .name = "usb-ep2",
105 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
106 },
107 [DMACH_USB_EP3] = {
108 .name = "usb-ep3",
109 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
110 },
111 [DMACH_USB_EP4] = {
112 .name = "usb-ep4",
113 .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
114 },
79}; 115};
80 116
81#ifdef CONFIG_S3C2410_DMA_DEBUG 117static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
82 118 struct s3c24xx_dma_map *map)
83/* dmadbg_showregs
84 *
85 * simple debug routine to print the current state of the dma registers
86*/
87
88static void
89dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
90{
91 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
92 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
93 regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
94 regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
95 regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
96}
97
98static void
99dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
100 struct s3c2410_dma_regstate *regs)
101{
102 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
103 chan->number, fname, line,
104 regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
105 regs->dcon);
106}
107
108static void
109dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
110{
111 struct s3c2410_dma_regstate state;
112
113 dmadbg_capture(chan, &state);
114
115 printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
116 chan->number, fname, line, chan->load_state,
117 chan->curr, chan->next, chan->end);
118
119 dmadbg_dumpregs(fname, line, chan, &state);
120}
121
122static void
123dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
124{
125 struct s3c2410_dma_regstate state;
126
127 dmadbg_capture(chan, &state);
128 dmadbg_dumpregs(fname, line, chan, &state);
129}
130
131#define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan))
132#define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan))
133#else
134#define dbg_showregs(chan) do { } while(0)
135#define dbg_showchan(chan) do { } while(0)
136#endif /* CONFIG_S3C2410_DMA_DEBUG */
137
138static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
139
140/* lookup_dma_channel
141 *
142 * change the dma channel number given into a real dma channel id
143*/
144
145static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
146{
147 if (channel & DMACH_LOW_LEVEL)
148 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
149 else
150 return dma_chan_map[channel];
151}
152
153/* s3c2410_dma_stats_timeout
154 *
155 * Update DMA stats from timeout info
156*/
157
158static void
159s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
160{ 119{
161 if (stats == NULL) 120 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
162 return;
163
164 if (val > stats->timeout_longest)
165 stats->timeout_longest = val;
166 if (val < stats->timeout_shortest)
167 stats->timeout_shortest = val;
168
169 stats->timeout_avg += val;
170} 121}
171 122
172/* s3c2410_dma_waitforload 123static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
173 * 124 .select = s3c2410_dma_select,
174 * wait for the DMA engine to load a buffer, and update the state accordingly 125 .dcon_mask = 7 << 24,
175*/ 126 .map = s3c2410_dma_mappings,
176 127 .map_size = ARRAY_SIZE(s3c2410_dma_mappings),
177static int 128};
178s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
179{
180 int timeout = chan->load_timeout;
181 int took;
182
183 if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
184 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
185 return 0;
186 }
187
188 if (chan->stats != NULL)
189 chan->stats->loads++;
190
191 while (--timeout > 0) {
192 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
193 took = chan->load_timeout - timeout;
194
195 s3c2410_dma_stats_timeout(chan->stats, took);
196
197 switch (chan->load_state) {
198 case S3C2410_DMALOAD_1LOADED:
199 chan->load_state = S3C2410_DMALOAD_1RUNNING;
200 break;
201
202 default:
203 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
204 }
205
206 return 1;
207 }
208 }
209
210 if (chan->stats != NULL) {
211 chan->stats->timeout_failed++;
212 }
213
214 return 0;
215}
216
217
218
219/* s3c2410_dma_loadbuffer
220 *
221 * load a buffer, and update the channel state
222*/
223
224static inline int
225s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
226 struct s3c2410_dma_buf *buf)
227{
228 unsigned long reload;
229
230 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
231 buf, (unsigned long)buf->data, buf->size);
232
233 if (buf == NULL) {
234 dmawarn("buffer is NULL\n");
235 return -EINVAL;
236 }
237
238 /* check the state of the channel before we do anything */
239
240 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
241 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
242 }
243
244 if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
245 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
246 }
247
248 /* it would seem sensible if we are the last buffer to not bother
249 * with the auto-reload bit, so that the DMA engine will not try
250 * and load another transfer after this one has finished...
251 */
252 if (chan->load_state == S3C2410_DMALOAD_NONE) {
253 pr_debug("load_state is none, checking for noreload (next=%p)\n",
254 buf->next);
255 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
256 } else {
257 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
258 reload = S3C2410_DCON_AUTORELOAD;
259 }
260
261 if ((buf->data & 0xf0000000) != 0x30000000) {
262 dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
263 }
264
265 writel(buf->data, chan->addr_reg);
266
267 dma_wrreg(chan, S3C2410_DMA_DCON,
268 chan->dcon | reload | (buf->size/chan->xfer_unit));
269
270 chan->next = buf->next;
271
272 /* update the state of the channel */
273
274 switch (chan->load_state) {
275 case S3C2410_DMALOAD_NONE:
276 chan->load_state = S3C2410_DMALOAD_1LOADED;
277 break;
278
279 case S3C2410_DMALOAD_1RUNNING:
280 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
281 break;
282
283 default:
284 dmawarn("dmaload: unknown state %d in loadbuffer\n",
285 chan->load_state);
286 break;
287 }
288
289 return 0;
290}
291
292/* s3c2410_dma_call_op
293 *
294 * small routine to call the op routine with the given op if it has been
295 * registered
296*/
297
298static void
299s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
300{
301 if (chan->op_fn != NULL) {
302 (chan->op_fn)(chan, op);
303 }
304}
305
306/* s3c2410_dma_buffdone
307 *
308 * small wrapper to check if callback routine needs to be called, and
309 * if so, call it
310*/
311
312static inline void
313s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
314 enum s3c2410_dma_buffresult result)
315{
316#if 0
317 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
318 chan->callback_fn, buf, buf->id, buf->size, result);
319#endif
320
321 if (chan->callback_fn != NULL) {
322 (chan->callback_fn)(chan, buf->id, buf->size, result);
323 }
324}
325
326/* s3c2410_dma_start
327 *
328 * start a dma channel going
329*/
330
331static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
332{
333 unsigned long tmp;
334 unsigned long flags;
335
336 pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
337
338 local_irq_save(flags);
339
340 if (chan->state == S3C2410_DMA_RUNNING) {
341 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
342 local_irq_restore(flags);
343 return 0;
344 }
345
346 chan->state = S3C2410_DMA_RUNNING;
347
348 /* check wether there is anything to load, and if not, see
349 * if we can find anything to load
350 */
351
352 if (chan->load_state == S3C2410_DMALOAD_NONE) {
353 if (chan->next == NULL) {
354 printk(KERN_ERR "dma%d: channel has nothing loaded\n",
355 chan->number);
356 chan->state = S3C2410_DMA_IDLE;
357 local_irq_restore(flags);
358 return -EINVAL;
359 }
360
361 s3c2410_dma_loadbuffer(chan, chan->next);
362 }
363
364 dbg_showchan(chan);
365
366 /* enable the channel */
367
368 if (!chan->irq_enabled) {
369 enable_irq(chan->irq);
370 chan->irq_enabled = 1;
371 }
372
373 /* start the channel going */
374
375 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
376 tmp &= ~S3C2410_DMASKTRIG_STOP;
377 tmp |= S3C2410_DMASKTRIG_ON;
378 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
379
380 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
381
382#if 0
383 /* the dma buffer loads should take care of clearing the AUTO
384 * reloading feature */
385 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
386 tmp &= ~S3C2410_DCON_NORELOAD;
387 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
388#endif
389
390 s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
391
392 dbg_showchan(chan);
393
394 /* if we've only loaded one buffer onto the channel, then chec
395 * to see if we have another, and if so, try and load it so when
396 * the first buffer is finished, the new one will be loaded onto
397 * the channel */
398
399 if (chan->next != NULL) {
400 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
401
402 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
403 pr_debug("%s: buff not yet loaded, no more todo\n",
404 __FUNCTION__);
405 } else {
406 chan->load_state = S3C2410_DMALOAD_1RUNNING;
407 s3c2410_dma_loadbuffer(chan, chan->next);
408 }
409
410 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
411 s3c2410_dma_loadbuffer(chan, chan->next);
412 }
413 }
414
415
416 local_irq_restore(flags);
417
418 return 0;
419}
420
421/* s3c2410_dma_canload
422 *
423 * work out if we can queue another buffer into the DMA engine
424*/
425
426static int
427s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
428{
429 if (chan->load_state == S3C2410_DMALOAD_NONE ||
430 chan->load_state == S3C2410_DMALOAD_1RUNNING)
431 return 1;
432
433 return 0;
434}
435
436/* s3c2410_dma_enqueue
437 *
438 * queue an given buffer for dma transfer.
439 *
440 * id the device driver's id information for this buffer
441 * data the physical address of the buffer data
442 * size the size of the buffer in bytes
443 *
444 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
445 * is checked, and if set, the channel is started. If this flag isn't set,
446 * then an error will be returned.
447 *
448 * It is possible to queue more than one DMA buffer onto a channel at
449 * once, and the code will deal with the re-loading of the next buffer
450 * when necessary.
451*/
452
453int s3c2410_dma_enqueue(unsigned int channel, void *id,
454 dma_addr_t data, int size)
455{
456 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
457 struct s3c2410_dma_buf *buf;
458 unsigned long flags;
459
460 if (chan == NULL)
461 return -EINVAL;
462
463 pr_debug("%s: id=%p, data=%08x, size=%d\n",
464 __FUNCTION__, id, (unsigned int)data, size);
465
466 buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
467 if (buf == NULL) {
468 pr_debug("%s: out of memory (%ld alloc)\n",
469 __FUNCTION__, (long)sizeof(*buf));
470 return -ENOMEM;
471 }
472
473 //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
474 //dbg_showchan(chan);
475
476 buf->next = NULL;
477 buf->data = buf->ptr = data;
478 buf->size = size;
479 buf->id = id;
480 buf->magic = BUF_MAGIC;
481
482 local_irq_save(flags);
483
484 if (chan->curr == NULL) {
485 /* we've got nothing loaded... */
486 pr_debug("%s: buffer %p queued onto empty channel\n",
487 __FUNCTION__, buf);
488
489 chan->curr = buf;
490 chan->end = buf;
491 chan->next = NULL;
492 } else {
493 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
494 chan->number, __FUNCTION__, buf);
495
496 if (chan->end == NULL)
497 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
498 chan->number, __FUNCTION__, chan);
499
500 chan->end->next = buf;
501 chan->end = buf;
502 }
503
504 /* if necessary, update the next buffer field */
505 if (chan->next == NULL)
506 chan->next = buf;
507
508 /* check to see if we can load a buffer */
509 if (chan->state == S3C2410_DMA_RUNNING) {
510 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
511 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
512 printk(KERN_ERR "dma%d: loadbuffer:"
513 "timeout loading buffer\n",
514 chan->number);
515 dbg_showchan(chan);
516 local_irq_restore(flags);
517 return -EINVAL;
518 }
519 }
520
521 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
522 s3c2410_dma_loadbuffer(chan, chan->next);
523 }
524 } else if (chan->state == S3C2410_DMA_IDLE) {
525 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
526 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START);
527 }
528 }
529
530 local_irq_restore(flags);
531 return 0;
532}
533
534EXPORT_SYMBOL(s3c2410_dma_enqueue);
535
536static inline void
537s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
538{
539 int magicok = (buf->magic == BUF_MAGIC);
540
541 buf->magic = -1;
542
543 if (magicok) {
544 kmem_cache_free(dma_kmem, buf);
545 } else {
546 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
547 }
548}
549
550/* s3c2410_dma_lastxfer
551 *
552 * called when the system is out of buffers, to ensure that the channel
553 * is prepared for shutdown.
554*/
555
556static inline void
557s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
558{
559#if 0
560 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
561 chan->number, chan->load_state);
562#endif
563
564 switch (chan->load_state) {
565 case S3C2410_DMALOAD_NONE:
566 break;
567
568 case S3C2410_DMALOAD_1LOADED:
569 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
570 /* flag error? */
571 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
572 chan->number, __FUNCTION__);
573 return;
574 }
575 break;
576
577 case S3C2410_DMALOAD_1LOADED_1RUNNING:
578 /* I belive in this case we do not have anything to do
579 * until the next buffer comes along, and we turn off the
580 * reload */
581 return;
582
583 default:
584 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
585 chan->number, chan->load_state);
586 return;
587
588 }
589
590 /* hopefully this'll shut the damned thing up after the transfer... */
591 dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
592}
593
594
595#define dmadbg2(x...)
596
597static irqreturn_t
598s3c2410_dma_irq(int irq, void *devpw)
599{
600 struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
601 struct s3c2410_dma_buf *buf;
602
603 buf = chan->curr;
604
605 dbg_showchan(chan);
606
607 /* modify the channel state */
608
609 switch (chan->load_state) {
610 case S3C2410_DMALOAD_1RUNNING:
611 /* TODO - if we are running only one buffer, we probably
612 * want to reload here, and then worry about the buffer
613 * callback */
614
615 chan->load_state = S3C2410_DMALOAD_NONE;
616 break;
617
618 case S3C2410_DMALOAD_1LOADED:
619 /* iirc, we should go back to NONE loaded here, we
620 * had a buffer, and it was never verified as being
621 * loaded.
622 */
623
624 chan->load_state = S3C2410_DMALOAD_NONE;
625 break;
626
627 case S3C2410_DMALOAD_1LOADED_1RUNNING:
628 /* we'll worry about checking to see if another buffer is
629 * ready after we've called back the owner. This should
630 * ensure we do not wait around too long for the DMA
631 * engine to start the next transfer
632 */
633
634 chan->load_state = S3C2410_DMALOAD_1LOADED;
635 break;
636
637 case S3C2410_DMALOAD_NONE:
638 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
639 chan->number);
640 break;
641
642 default:
643 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
644 chan->number, chan->load_state);
645 break;
646 }
647
648 if (buf != NULL) {
649 /* update the chain to make sure that if we load any more
650 * buffers when we call the callback function, things should
651 * work properly */
652
653 chan->curr = buf->next;
654 buf->next = NULL;
655
656 if (buf->magic != BUF_MAGIC) {
657 printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
658 chan->number, __FUNCTION__, buf);
659 return IRQ_HANDLED;
660 }
661
662 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
663
664 /* free resouces */
665 s3c2410_dma_freebuf(buf);
666 } else {
667 }
668
669 /* only reload if the channel is still running... our buffer done
670 * routine may have altered the state by requesting the dma channel
671 * to stop or shutdown... */
672
673 /* todo: check that when the channel is shut-down from inside this
674 * function, we cope with unsetting reload, etc */
675
676 if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
677 unsigned long flags;
678
679 switch (chan->load_state) {
680 case S3C2410_DMALOAD_1RUNNING:
681 /* don't need to do anything for this state */
682 break;
683
684 case S3C2410_DMALOAD_NONE:
685 /* can load buffer immediately */
686 break;
687
688 case S3C2410_DMALOAD_1LOADED:
689 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
690 /* flag error? */
691 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
692 chan->number, __FUNCTION__);
693 return IRQ_HANDLED;
694 }
695
696 break;
697
698 case S3C2410_DMALOAD_1LOADED_1RUNNING:
699 goto no_load;
700
701 default:
702 printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
703 chan->number, chan->load_state);
704 return IRQ_HANDLED;
705 }
706
707 local_irq_save(flags);
708 s3c2410_dma_loadbuffer(chan, chan->next);
709 local_irq_restore(flags);
710 } else {
711 s3c2410_dma_lastxfer(chan);
712
713 /* see if we can stop this channel.. */
714 if (chan->load_state == S3C2410_DMALOAD_NONE) {
715 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
716 chan->number, jiffies);
717 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
718 S3C2410_DMAOP_STOP);
719 }
720 }
721
722 no_load:
723 return IRQ_HANDLED;
724}
725
726static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
727
728/* s3c2410_request_dma
729 *
730 * get control of an dma channel
731*/
732
733int s3c2410_dma_request(unsigned int channel,
734 struct s3c2410_dma_client *client,
735 void *dev)
736{
737 struct s3c2410_dma_chan *chan;
738 unsigned long flags;
739 int err;
740
741 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
742 channel, client->name, dev);
743
744 local_irq_save(flags);
745
746 chan = s3c2410_dma_map_channel(channel);
747 if (chan == NULL) {
748 local_irq_restore(flags);
749 return -EBUSY;
750 }
751
752 dbg_showchan(chan);
753
754 chan->client = client;
755 chan->in_use = 1;
756
757 if (!chan->irq_claimed) {
758 pr_debug("dma%d: %s : requesting irq %d\n",
759 channel, __FUNCTION__, chan->irq);
760
761 chan->irq_claimed = 1;
762 local_irq_restore(flags);
763
764 err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
765 client->name, (void *)chan);
766
767 local_irq_save(flags);
768
769 if (err) {
770 chan->in_use = 0;
771 chan->irq_claimed = 0;
772 local_irq_restore(flags);
773
774 printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
775 client->name, chan->irq, chan->number);
776 return err;
777 }
778
779 chan->irq_enabled = 1;
780 }
781
782 local_irq_restore(flags);
783
784 /* need to setup */
785
786 pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan);
787
788 return 0;
789}
790
791EXPORT_SYMBOL(s3c2410_dma_request);
792
793/* s3c2410_dma_free
794 *
795 * release the given channel back to the system, will stop and flush
796 * any outstanding transfers, and ensure the channel is ready for the
797 * next claimant.
798 *
799 * Note, although a warning is currently printed if the freeing client
800 * info is not the same as the registrant's client info, the free is still
801 * allowed to go through.
802*/
803 129
804int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) 130static int s3c2410_dma_add(struct sys_device *sysdev)
805{ 131{
806 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 132 return s3c24xx_dma_init_map(&s3c2410_dma_sel);
807 unsigned long flags;
808
809 if (chan == NULL)
810 return -EINVAL;
811
812 local_irq_save(flags);
813
814 if (chan->client != client) {
815 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
816 channel, chan->client, client);
817 }
818
819 /* sort out stopping and freeing the channel */
820
821 if (chan->state != S3C2410_DMA_IDLE) {
822 pr_debug("%s: need to stop dma channel %p\n",
823 __FUNCTION__, chan);
824
825 /* possibly flush the channel */
826 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
827 }
828
829 chan->client = NULL;
830 chan->in_use = 0;
831
832 if (chan->irq_claimed)
833 free_irq(chan->irq, (void *)chan);
834
835 chan->irq_claimed = 0;
836
837 if (!(channel & DMACH_LOW_LEVEL))
838 dma_chan_map[channel] = NULL;
839
840 local_irq_restore(flags);
841
842 return 0;
843} 133}
844 134
845EXPORT_SYMBOL(s3c2410_dma_free); 135#if defined(CONFIG_CPU_S3C2410)
846 136static struct sysdev_driver s3c2410_dma_driver = {
847static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan) 137 .add = s3c2410_dma_add,
848{ 138};
849 unsigned long flags;
850 unsigned long tmp;
851
852 pr_debug("%s:\n", __FUNCTION__);
853
854 dbg_showchan(chan);
855
856 local_irq_save(flags);
857
858 s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
859
860 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
861 tmp |= S3C2410_DMASKTRIG_STOP;
862 //tmp &= ~S3C2410_DMASKTRIG_ON;
863 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
864
865#if 0
866 /* should also clear interrupts, according to WinCE BSP */
867 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
868 tmp |= S3C2410_DCON_NORELOAD;
869 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
870#endif
871
872 /* should stop do this, or should we wait for flush? */
873 chan->state = S3C2410_DMA_IDLE;
874 chan->load_state = S3C2410_DMALOAD_NONE;
875
876 local_irq_restore(flags);
877
878 return 0;
879}
880 139
881void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan) 140static int __init s3c2410_dma_init(void)
882{ 141{
883 unsigned long tmp; 142 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
884 unsigned int timeout = 0x10000;
885
886 while (timeout-- > 0) {
887 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
888
889 if (!(tmp & S3C2410_DMASKTRIG_ON))
890 return;
891 }
892
893 pr_debug("dma%d: failed to stop?\n", chan->number);
894} 143}
895 144
896 145arch_initcall(s3c2410_dma_init);
897/* s3c2410_dma_flush
898 *
899 * stop the channel, and remove all current and pending transfers
900*/
901
902static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
903{
904 struct s3c2410_dma_buf *buf, *next;
905 unsigned long flags;
906
907 pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number);
908
909 dbg_showchan(chan);
910
911 local_irq_save(flags);
912
913 if (chan->state != S3C2410_DMA_IDLE) {
914 pr_debug("%s: stopping channel...\n", __FUNCTION__ );
915 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
916 }
917
918 buf = chan->curr;
919 if (buf == NULL)
920 buf = chan->next;
921
922 chan->curr = chan->next = chan->end = NULL;
923
924 if (buf != NULL) {
925 for ( ; buf != NULL; buf = next) {
926 next = buf->next;
927
928 pr_debug("%s: free buffer %p, next %p\n",
929 __FUNCTION__, buf, buf->next);
930
931 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
932 s3c2410_dma_freebuf(buf);
933 }
934 }
935
936 dbg_showregs(chan);
937
938 s3c2410_dma_waitforstop(chan);
939
940#if 0
941 /* should also clear interrupts, according to WinCE BSP */
942 {
943 unsigned long tmp;
944
945 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
946 tmp |= S3C2410_DCON_NORELOAD;
947 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
948 }
949#endif 146#endif
950 147
951 dbg_showregs(chan); 148#if defined(CONFIG_CPU_S3C2442)
952 149/* S3C2442 DMA contains the same selection table as the S3C2410 */
953 local_irq_restore(flags); 150static struct sysdev_driver s3c2442_dma_driver = {
954 151 .add = s3c2410_dma_add,
955 return 0;
956}
957
958int
959s3c2410_dma_started(struct s3c2410_dma_chan *chan)
960{
961 unsigned long flags;
962
963 local_irq_save(flags);
964
965 dbg_showchan(chan);
966
967 /* if we've only loaded one buffer onto the channel, then chec
968 * to see if we have another, and if so, try and load it so when
969 * the first buffer is finished, the new one will be loaded onto
970 * the channel */
971
972 if (chan->next != NULL) {
973 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
974
975 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
976 pr_debug("%s: buff not yet loaded, no more todo\n",
977 __FUNCTION__);
978 } else {
979 chan->load_state = S3C2410_DMALOAD_1RUNNING;
980 s3c2410_dma_loadbuffer(chan, chan->next);
981 }
982
983 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
984 s3c2410_dma_loadbuffer(chan, chan->next);
985 }
986 }
987
988
989 local_irq_restore(flags);
990
991 return 0;
992
993}
994
995int
996s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
997{
998 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
999
1000 if (chan == NULL)
1001 return -EINVAL;
1002
1003 switch (op) {
1004 case S3C2410_DMAOP_START:
1005 return s3c2410_dma_start(chan);
1006
1007 case S3C2410_DMAOP_STOP:
1008 return s3c2410_dma_dostop(chan);
1009
1010 case S3C2410_DMAOP_PAUSE:
1011 case S3C2410_DMAOP_RESUME:
1012 return -ENOENT;
1013
1014 case S3C2410_DMAOP_FLUSH:
1015 return s3c2410_dma_flush(chan);
1016
1017 case S3C2410_DMAOP_STARTED:
1018 return s3c2410_dma_started(chan);
1019
1020 case S3C2410_DMAOP_TIMEOUT:
1021 return 0;
1022
1023 }
1024
1025 return -ENOENT; /* unknown, don't bother */
1026}
1027
1028EXPORT_SYMBOL(s3c2410_dma_ctrl);
1029
1030/* DMA configuration for each channel
1031 *
1032 * DISRCC -> source of the DMA (AHB,APB)
1033 * DISRC -> source address of the DMA
1034 * DIDSTC -> destination of the DMA (AHB,APD)
1035 * DIDST -> destination address of the DMA
1036*/
1037
1038/* s3c2410_dma_config
1039 *
1040 * xfersize: size of unit in bytes (1,2,4)
1041 * dcon: base value of the DCONx register
1042*/
1043
1044int s3c2410_dma_config(dmach_t channel,
1045 int xferunit,
1046 int dcon)
1047{
1048 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1049
1050 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1051 __FUNCTION__, channel, xferunit, dcon);
1052
1053 if (chan == NULL)
1054 return -EINVAL;
1055
1056 pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon);
1057
1058 dcon |= chan->dcon & dma_sel.dcon_mask;
1059
1060 pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon);
1061
1062 switch (xferunit) {
1063 case 1:
1064 dcon |= S3C2410_DCON_BYTE;
1065 break;
1066
1067 case 2:
1068 dcon |= S3C2410_DCON_HALFWORD;
1069 break;
1070
1071 case 4:
1072 dcon |= S3C2410_DCON_WORD;
1073 break;
1074
1075 default:
1076 pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit);
1077 return -EINVAL;
1078 }
1079
1080 dcon |= S3C2410_DCON_HWTRIG;
1081 dcon |= S3C2410_DCON_INTREQ;
1082
1083 pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
1084
1085 chan->dcon = dcon;
1086 chan->xfer_unit = xferunit;
1087
1088 return 0;
1089}
1090
1091EXPORT_SYMBOL(s3c2410_dma_config);
1092
1093int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
1094{
1095 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1096
1097 if (chan == NULL)
1098 return -EINVAL;
1099
1100 pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
1101
1102 chan->flags = flags;
1103
1104 return 0;
1105}
1106
1107EXPORT_SYMBOL(s3c2410_dma_setflags);
1108
1109
1110/* do we need to protect the settings of the fields from
1111 * irq?
1112*/
1113
1114int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
1115{
1116 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1117
1118 if (chan == NULL)
1119 return -EINVAL;
1120
1121 pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
1122
1123 chan->op_fn = rtn;
1124
1125 return 0;
1126}
1127
1128EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1129
1130int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
1131{
1132 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1133
1134 if (chan == NULL)
1135 return -EINVAL;
1136
1137 pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
1138
1139 chan->callback_fn = rtn;
1140
1141 return 0;
1142}
1143
1144EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1145
1146/* s3c2410_dma_devconfig
1147 *
1148 * configure the dma source/destination hardware type and address
1149 *
1150 * source: S3C2410_DMASRC_HW: source is hardware
1151 * S3C2410_DMASRC_MEM: source is memory
1152 *
1153 * hwcfg: the value for xxxSTCn register,
1154 * bit 0: 0=increment pointer, 1=leave pointer
1155 * bit 1: 0=soucre is AHB, 1=soucre is APB
1156 *
1157 * devaddr: physical address of the source
1158*/
1159
1160int s3c2410_dma_devconfig(int channel,
1161 enum s3c2410_dmasrc source,
1162 int hwcfg,
1163 unsigned long devaddr)
1164{
1165 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1166
1167 if (chan == NULL)
1168 return -EINVAL;
1169
1170 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
1171 __FUNCTION__, (int)source, hwcfg, devaddr);
1172
1173 chan->source = source;
1174 chan->dev_addr = devaddr;
1175
1176 switch (source) {
1177 case S3C2410_DMASRC_HW:
1178 /* source is hardware */
1179 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1180 __FUNCTION__, devaddr, hwcfg);
1181 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1182 dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
1183 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1184
1185 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1186 return 0;
1187
1188 case S3C2410_DMASRC_MEM:
1189 /* source is memory */
1190 pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1191 __FUNCTION__, devaddr, hwcfg);
1192 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1193 dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
1194 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1195
1196 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1197 return 0;
1198 }
1199
1200 printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source);
1201 return -EINVAL;
1202}
1203
1204EXPORT_SYMBOL(s3c2410_dma_devconfig);
1205
1206/* s3c2410_dma_getposition
1207 *
1208 * returns the current transfer points for the dma source and destination
1209*/
1210
1211int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
1212{
1213 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1214
1215 if (chan == NULL)
1216 return -EINVAL;
1217
1218 if (src != NULL)
1219 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1220
1221 if (dst != NULL)
1222 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1223
1224 return 0;
1225}
1226
1227EXPORT_SYMBOL(s3c2410_dma_getposition);
1228
1229
1230/* system device class */
1231
1232#ifdef CONFIG_PM
1233
1234static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state)
1235{
1236 struct s3c2410_dma_chan *cp = container_of(dev, struct s3c2410_dma_chan, dev);
1237
1238 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1239
1240 if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1241 /* the dma channel is still working, which is probably
1242 * a bad thing to do over suspend/resume. We stop the
1243 * channel and assume that the client is either going to
1244 * retry after resume, or that it is broken.
1245 */
1246
1247 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1248 cp->number);
1249
1250 s3c2410_dma_dostop(cp);
1251 }
1252
1253 return 0;
1254}
1255
1256static int s3c2410_dma_resume(struct sys_device *dev)
1257{
1258 return 0;
1259}
1260
1261#else
1262#define s3c2410_dma_suspend NULL
1263#define s3c2410_dma_resume NULL
1264#endif /* CONFIG_PM */
1265
1266struct sysdev_class dma_sysclass = {
1267 set_kset_name("s3c24xx-dma"),
1268 .suspend = s3c2410_dma_suspend,
1269 .resume = s3c2410_dma_resume,
1270}; 152};
1271 153
1272/* kmem cache implementation */ 154static int __init s3c2442_dma_init(void)
1273
1274static void s3c2410_dma_cache_ctor(void *p, struct kmem_cache *c, unsigned long f)
1275{
1276 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1277}
1278
1279/* initialisation code */
1280
1281static int __init s3c2410_init_dma(void)
1282{
1283 struct s3c2410_dma_chan *cp;
1284 int channel;
1285 int ret;
1286
1287 printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
1288
1289 dma_base = ioremap(S3C24XX_PA_DMA, 0x200);
1290 if (dma_base == NULL) {
1291 printk(KERN_ERR "dma failed to remap register block\n");
1292 return -ENOMEM;
1293 }
1294
1295 printk("Registering sysclass\n");
1296
1297 ret = sysdev_class_register(&dma_sysclass);
1298 if (ret != 0) {
1299 printk(KERN_ERR "dma sysclass registration failed\n");
1300 goto err;
1301 }
1302
1303 dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0,
1304 SLAB_HWCACHE_ALIGN,
1305 s3c2410_dma_cache_ctor, NULL);
1306
1307 if (dma_kmem == NULL) {
1308 printk(KERN_ERR "dma failed to make kmem cache\n");
1309 ret = -ENOMEM;
1310 goto err;
1311 }
1312
1313 for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) {
1314 cp = &s3c2410_chans[channel];
1315
1316 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1317
1318 /* dma channel irqs are in order.. */
1319 cp->number = channel;
1320 cp->irq = channel + IRQ_DMA0;
1321 cp->regs = dma_base + (channel*0x40);
1322
1323 /* point current stats somewhere */
1324 cp->stats = &cp->stats_store;
1325 cp->stats_store.timeout_shortest = LONG_MAX;
1326
1327 /* basic channel configuration */
1328
1329 cp->load_timeout = 1<<18;
1330
1331 /* register system device */
1332
1333 cp->dev.cls = &dma_sysclass;
1334 cp->dev.id = channel;
1335 ret = sysdev_register(&cp->dev);
1336
1337 printk("DMA channel %d at %p, irq %d\n",
1338 cp->number, cp->regs, cp->irq);
1339 }
1340
1341 return 0;
1342
1343 err:
1344 kmem_cache_destroy(dma_kmem);
1345 iounmap(dma_base);
1346 dma_base = NULL;
1347 return ret;
1348}
1349
1350core_initcall(s3c2410_init_dma);
1351
1352static inline int is_channel_valid(unsigned int channel)
1353{ 155{
1354 return (channel & DMA_CH_VALID); 156 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
1355} 157}
1356 158
1357/* s3c2410_dma_map_channel() 159arch_initcall(s3c2442_dma_init);
1358 * 160#endif
1359 * turn the virtual channel number into a real, and un-used hardware
1360 * channel.
1361 *
1362 * currently this code uses first-free channel from the specified harware
1363 * map, not taking into account anything that the board setup code may
1364 * have to say about the likely peripheral set to be in use.
1365*/
1366
1367struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1368{
1369 struct s3c24xx_dma_map *ch_map;
1370 struct s3c2410_dma_chan *dmach;
1371 int ch;
1372
1373 if (dma_sel.map == NULL || channel > dma_sel.map_size)
1374 return NULL;
1375
1376 ch_map = dma_sel.map + channel;
1377
1378 for (ch = 0; ch < S3C2410_DMA_CHANNELS; ch++) {
1379 if (!is_channel_valid(ch_map->channels[ch]))
1380 continue;
1381
1382 if (s3c2410_chans[ch].in_use == 0) {
1383 printk("mapped channel %d to %d\n", channel, ch);
1384 break;
1385 }
1386 }
1387
1388 if (ch >= S3C2410_DMA_CHANNELS)
1389 return NULL;
1390
1391 /* update our channel mapping */
1392
1393 dmach = &s3c2410_chans[ch];
1394 dma_chan_map[channel] = dmach;
1395
1396 /* select the channel */
1397
1398 (dma_sel.select)(dmach, ch_map);
1399
1400 return dmach;
1401}
1402
1403static void s3c24xx_dma_show_ch(struct s3c24xx_dma_map *map, int ch)
1404{
1405 /* show the channel configuration */
1406
1407 printk("%2d: %20s, channels %c%c%c%c\n", ch, map->name,
1408 (is_channel_valid(map->channels[0]) ? '0' : '-'),
1409 (is_channel_valid(map->channels[1]) ? '1' : '-'),
1410 (is_channel_valid(map->channels[2]) ? '2' : '-'),
1411 (is_channel_valid(map->channels[3]) ? '3' : '-'));
1412}
1413
1414static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1415{
1416 if (1)
1417 s3c24xx_dma_show_ch(map, ch);
1418
1419 return 0;
1420}
1421
1422int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1423{
1424 struct s3c24xx_dma_map *nmap;
1425 size_t map_sz = sizeof(*nmap) * sel->map_size;
1426 int ptr;
1427
1428 nmap = kmalloc(map_sz, GFP_KERNEL);
1429 if (nmap == NULL)
1430 return -ENOMEM;
1431
1432 memcpy(nmap, sel->map, map_sz);
1433 memcpy(&dma_sel, sel, sizeof(*sel));
1434
1435 dma_sel.map = nmap;
1436
1437 for (ptr = 0; ptr < sel->map_size; ptr++)
1438 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1439 161
1440 return 0;
1441}
diff --git a/arch/arm/mach-s3c2410/dma.h b/arch/arm/mach-s3c2410/dma.h
deleted file mode 100644
index 0ebfe0aab80b..000000000000
--- a/arch/arm/mach-s3c2410/dma.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/* arch/arm/mach-s3c2410/dma.h
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern struct sysdev_class dma_sysclass;
14extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
15
16#define DMA_CH_VALID (1<<31)
17
18struct s3c24xx_dma_addr {
19 unsigned long from;
20 unsigned long to;
21};
22
23/* struct s3c24xx_dma_map
24 *
25 * this holds the mapping information for the channel selected
26 * to be connected to the specified device
27*/
28
29struct s3c24xx_dma_map {
30 const char *name;
31 struct s3c24xx_dma_addr hw_addr;
32
33 unsigned long channels[S3C2410_DMA_CHANNELS];
34};
35
36struct s3c24xx_dma_selection {
37 struct s3c24xx_dma_map *map;
38 unsigned long map_size;
39 unsigned long dcon_mask;
40
41 void (*select)(struct s3c2410_dma_chan *chan,
42 struct s3c24xx_dma_map *map);
43};
44
45extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index f6fb215bb48c..01e795d1146e 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s3c2410/gpio.c 1/* linux/arch/arm/mach-s3c2410/gpio.c
2 * 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics 3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * S3C24XX GPIO support 6 * S3C2410 GPIO support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -18,8 +18,7 @@
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/ 21 */
22
23 22
24#include <linux/kernel.h> 23#include <linux/kernel.h>
25#include <linux/init.h> 24#include <linux/init.h>
@@ -33,156 +32,40 @@
33 32
34#include <asm/arch/regs-gpio.h> 33#include <asm/arch/regs-gpio.h>
35 34
36void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function) 35int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
37{ 36 unsigned int config)
38 void __iomem *base = S3C24XX_GPIO_BASE(pin);
39 unsigned long mask;
40 unsigned long con;
41 unsigned long flags;
42
43 if (pin < S3C2410_GPIO_BANKB) {
44 mask = 1 << S3C2410_GPIO_OFFSET(pin);
45 } else {
46 mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
47 }
48
49 switch (function) {
50 case S3C2410_GPIO_LEAVE:
51 mask = 0;
52 function = 0;
53 break;
54
55 case S3C2410_GPIO_INPUT:
56 case S3C2410_GPIO_OUTPUT:
57 case S3C2410_GPIO_SFN2:
58 case S3C2410_GPIO_SFN3:
59 if (pin < S3C2410_GPIO_BANKB) {
60 function -= 1;
61 function &= 1;
62 function <<= S3C2410_GPIO_OFFSET(pin);
63 } else {
64 function &= 3;
65 function <<= S3C2410_GPIO_OFFSET(pin)*2;
66 }
67 }
68
69 /* modify the specified register wwith IRQs off */
70
71 local_irq_save(flags);
72
73 con = __raw_readl(base + 0x00);
74 con &= ~mask;
75 con |= function;
76
77 __raw_writel(con, base + 0x00);
78
79 local_irq_restore(flags);
80}
81
82EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
83
84unsigned int s3c2410_gpio_getcfg(unsigned int pin)
85{
86 void __iomem *base = S3C24XX_GPIO_BASE(pin);
87 unsigned long val = __raw_readl(base);
88
89 if (pin < S3C2410_GPIO_BANKB) {
90 val >>= S3C2410_GPIO_OFFSET(pin);
91 val &= 1;
92 val += 1;
93 } else {
94 val >>= S3C2410_GPIO_OFFSET(pin)*2;
95 val &= 3;
96 }
97
98 return val | S3C2410_GPIO_INPUT;
99}
100
101EXPORT_SYMBOL(s3c2410_gpio_getcfg);
102
103void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
104{ 37{
105 void __iomem *base = S3C24XX_GPIO_BASE(pin); 38 void __iomem *reg = S3C24XX_EINFLT0;
106 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
107 unsigned long flags; 39 unsigned long flags;
108 unsigned long up; 40 unsigned long val;
109
110 if (pin < S3C2410_GPIO_BANKB)
111 return;
112
113 local_irq_save(flags);
114
115 up = __raw_readl(base + 0x08);
116 up &= ~(1L << offs);
117 up |= to << offs;
118 __raw_writel(up, base + 0x08);
119 41
120 local_irq_restore(flags); 42 if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
121} 43 return -1;
122 44
123EXPORT_SYMBOL(s3c2410_gpio_pullup); 45 config &= 0xff;
124 46
125void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) 47 pin -= S3C2410_GPG8;
126{ 48 reg += pin & ~3;
127 void __iomem *base = S3C24XX_GPIO_BASE(pin);
128 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
129 unsigned long flags;
130 unsigned long dat;
131 49
132 local_irq_save(flags); 50 local_irq_save(flags);
133 51
134 dat = __raw_readl(base + 0x04); 52 /* update filter width and clock source */
135 dat &= ~(1 << offs);
136 dat |= to << offs;
137 __raw_writel(dat, base + 0x04);
138
139 local_irq_restore(flags);
140}
141
142EXPORT_SYMBOL(s3c2410_gpio_setpin);
143
144unsigned int s3c2410_gpio_getpin(unsigned int pin)
145{
146 void __iomem *base = S3C24XX_GPIO_BASE(pin);
147 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
148 53
149 return __raw_readl(base + 0x04) & (1<< offs); 54 val = __raw_readl(reg);
150} 55 val &= ~(0xff << ((pin & 3) * 8));
56 val |= config << ((pin & 3) * 8);
57 __raw_writel(val, reg);
151 58
152EXPORT_SYMBOL(s3c2410_gpio_getpin); 59 /* update filter enable */
153 60
154unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) 61 val = __raw_readl(S3C24XX_EXTINT2);
155{ 62 val &= ~(1 << ((pin * 4) + 3));
156 unsigned long flags; 63 val |= on << ((pin * 4) + 3);
157 unsigned long misccr; 64 __raw_writel(val, S3C24XX_EXTINT2);
158 65
159 local_irq_save(flags);
160 misccr = __raw_readl(S3C24XX_MISCCR);
161 misccr &= ~clear;
162 misccr ^= change;
163 __raw_writel(misccr, S3C24XX_MISCCR);
164 local_irq_restore(flags); 66 local_irq_restore(flags);
165 67
166 return misccr; 68 return 0;
167}
168
169EXPORT_SYMBOL(s3c2410_modify_misccr);
170
171int s3c2410_gpio_getirq(unsigned int pin)
172{
173 if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15)
174 return -1; /* not valid interrupts */
175
176 if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
177 return -1; /* not valid pin */
178
179 if (pin < S3C2410_GPF4)
180 return (pin - S3C2410_GPF0) + IRQ_EINT0;
181
182 if (pin < S3C2410_GPG0)
183 return (pin - S3C2410_GPF4) + IRQ_EINT4;
184
185 return (pin - S3C2410_GPG0) + IRQ_EINT8;
186} 69}
187 70
188EXPORT_SYMBOL(s3c2410_gpio_getirq); 71EXPORT_SYMBOL(s3c2410_gpio_irqfilter);
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 3c0ed7871c55..53cbdaa43ac6 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s3c2410/irq.c 1/* linux/arch/arm/mach-s3c2410/irq.c
2 * 2 *
3 * Copyright (c) 2003,2004 Simtec Electronics 3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
@@ -17,37 +17,6 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 * 19 *
20 * Changelog:
21 *
22 * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
23 * Fixed compile warnings
24 *
25 * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
26 * Fixed s3c_extirq_type
27 *
28 * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
29 * Addition of ADC/TC demux
30 *
31 * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
32 * Fix for set_irq_type() on low EINT numbers
33 *
34 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
35 * Tidy up KF's patch and sort out new release
36 *
37 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
38 * Add support for power management controls
39 *
40 * 04-Nov-2004 Ben Dooks
41 * Fix standard IRQ wake for EINT0..4 and RTC
42 *
43 * 22-Feb-2005 Ben Dooks
44 * Fixed edge-triggering on ADC IRQ
45 *
46 * 28-Jun-2005 Ben Dooks
47 * Mark IRQ_LCD valid
48 *
49 * 25-Jul-2005 Ben Dooks
50 * Split the S3C2440 IRQ code to seperate file
51*/ 20*/
52 21
53#include <linux/init.h> 22#include <linux/init.h>
@@ -57,745 +26,23 @@
57#include <linux/ptrace.h> 26#include <linux/ptrace.h>
58#include <linux/sysdev.h> 27#include <linux/sysdev.h>
59 28
60#include <asm/hardware.h> 29#include <asm/plat-s3c24xx/cpu.h>
61#include <asm/irq.h> 30#include <asm/plat-s3c24xx/pm.h>
62#include <asm/io.h>
63
64#include <asm/mach/irq.h>
65
66#include <asm/arch/regs-irq.h>
67#include <asm/arch/regs-gpio.h>
68
69#include "cpu.h"
70#include "pm.h"
71#include "irq.h"
72
73/* wakeup irq control */
74
75#ifdef CONFIG_PM
76
77/* state for IRQs over sleep */
78
79/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
80 *
81 * set bit to 1 in allow bitfield to enable the wakeup settings on it
82*/
83
84unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
85unsigned long s3c_irqwake_intmask = 0xffffffffL;
86unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
87unsigned long s3c_irqwake_eintmask = 0xffffffffL;
88
89int
90s3c_irq_wake(unsigned int irqno, unsigned int state)
91{
92 unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
93
94 if (!(s3c_irqwake_intallow & irqbit))
95 return -ENOENT;
96
97 printk(KERN_INFO "wake %s for irq %d\n",
98 state ? "enabled" : "disabled", irqno);
99
100 if (!state)
101 s3c_irqwake_intmask |= irqbit;
102 else
103 s3c_irqwake_intmask &= ~irqbit;
104
105 return 0;
106}
107
108static int
109s3c_irqext_wake(unsigned int irqno, unsigned int state)
110{
111 unsigned long bit = 1L << (irqno - EXTINT_OFF);
112
113 if (!(s3c_irqwake_eintallow & bit))
114 return -ENOENT;
115
116 printk(KERN_INFO "wake %s for irq %d\n",
117 state ? "enabled" : "disabled", irqno);
118
119 if (!state)
120 s3c_irqwake_eintmask |= bit;
121 else
122 s3c_irqwake_eintmask &= ~bit;
123
124 return 0;
125}
126
127#else
128#define s3c_irqext_wake NULL
129#define s3c_irq_wake NULL
130#endif
131
132
133static void
134s3c_irq_mask(unsigned int irqno)
135{
136 unsigned long mask;
137
138 irqno -= IRQ_EINT0;
139
140 mask = __raw_readl(S3C2410_INTMSK);
141 mask |= 1UL << irqno;
142 __raw_writel(mask, S3C2410_INTMSK);
143}
144
145static inline void
146s3c_irq_ack(unsigned int irqno)
147{
148 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
149
150 __raw_writel(bitval, S3C2410_SRCPND);
151 __raw_writel(bitval, S3C2410_INTPND);
152}
153
154static inline void
155s3c_irq_maskack(unsigned int irqno)
156{
157 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
158 unsigned long mask;
159
160 mask = __raw_readl(S3C2410_INTMSK);
161 __raw_writel(mask|bitval, S3C2410_INTMSK);
162
163 __raw_writel(bitval, S3C2410_SRCPND);
164 __raw_writel(bitval, S3C2410_INTPND);
165}
166
167
168static void
169s3c_irq_unmask(unsigned int irqno)
170{
171 unsigned long mask;
172
173 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
174 irqdbf2("s3c_irq_unmask %d\n", irqno);
175
176 irqno -= IRQ_EINT0;
177
178 mask = __raw_readl(S3C2410_INTMSK);
179 mask &= ~(1UL << irqno);
180 __raw_writel(mask, S3C2410_INTMSK);
181}
182
183struct irq_chip s3c_irq_level_chip = {
184 .name = "s3c-level",
185 .ack = s3c_irq_maskack,
186 .mask = s3c_irq_mask,
187 .unmask = s3c_irq_unmask,
188 .set_wake = s3c_irq_wake
189};
190
191static struct irq_chip s3c_irq_chip = {
192 .name = "s3c",
193 .ack = s3c_irq_ack,
194 .mask = s3c_irq_mask,
195 .unmask = s3c_irq_unmask,
196 .set_wake = s3c_irq_wake
197};
198
199static void
200s3c_irqext_mask(unsigned int irqno)
201{
202 unsigned long mask;
203
204 irqno -= EXTINT_OFF;
205
206 mask = __raw_readl(S3C24XX_EINTMASK);
207 mask |= ( 1UL << irqno);
208 __raw_writel(mask, S3C24XX_EINTMASK);
209}
210
211static void
212s3c_irqext_ack(unsigned int irqno)
213{
214 unsigned long req;
215 unsigned long bit;
216 unsigned long mask;
217 31
218 bit = 1UL << (irqno - EXTINT_OFF); 32static int s3c2410_irq_add(struct sys_device *sysdev)
219
220 mask = __raw_readl(S3C24XX_EINTMASK);
221
222 __raw_writel(bit, S3C24XX_EINTPEND);
223
224 req = __raw_readl(S3C24XX_EINTPEND);
225 req &= ~mask;
226
227 /* not sure if we should be acking the parent irq... */
228
229 if (irqno <= IRQ_EINT7 ) {
230 if ((req & 0xf0) == 0)
231 s3c_irq_ack(IRQ_EINT4t7);
232 } else {
233 if ((req >> 8) == 0)
234 s3c_irq_ack(IRQ_EINT8t23);
235 }
236}
237
238static void
239s3c_irqext_unmask(unsigned int irqno)
240{ 33{
241 unsigned long mask;
242
243 irqno -= EXTINT_OFF;
244
245 mask = __raw_readl(S3C24XX_EINTMASK);
246 mask &= ~( 1UL << irqno);
247 __raw_writel(mask, S3C24XX_EINTMASK);
248}
249
250int
251s3c_irqext_type(unsigned int irq, unsigned int type)
252{
253 void __iomem *extint_reg;
254 void __iomem *gpcon_reg;
255 unsigned long gpcon_offset, extint_offset;
256 unsigned long newvalue = 0, value;
257
258 if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
259 {
260 gpcon_reg = S3C2410_GPFCON;
261 extint_reg = S3C24XX_EXTINT0;
262 gpcon_offset = (irq - IRQ_EINT0) * 2;
263 extint_offset = (irq - IRQ_EINT0) * 4;
264 }
265 else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
266 {
267 gpcon_reg = S3C2410_GPFCON;
268 extint_reg = S3C24XX_EXTINT0;
269 gpcon_offset = (irq - (EXTINT_OFF)) * 2;
270 extint_offset = (irq - (EXTINT_OFF)) * 4;
271 }
272 else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
273 {
274 gpcon_reg = S3C2410_GPGCON;
275 extint_reg = S3C24XX_EXTINT1;
276 gpcon_offset = (irq - IRQ_EINT8) * 2;
277 extint_offset = (irq - IRQ_EINT8) * 4;
278 }
279 else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
280 {
281 gpcon_reg = S3C2410_GPGCON;
282 extint_reg = S3C24XX_EXTINT2;
283 gpcon_offset = (irq - IRQ_EINT8) * 2;
284 extint_offset = (irq - IRQ_EINT16) * 4;
285 } else
286 return -1;
287
288 /* Set the GPIO to external interrupt mode */
289 value = __raw_readl(gpcon_reg);
290 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
291 __raw_writel(value, gpcon_reg);
292
293 /* Set the external interrupt to pointed trigger type */
294 switch (type)
295 {
296 case IRQT_NOEDGE:
297 printk(KERN_WARNING "No edge setting!\n");
298 break;
299
300 case IRQT_RISING:
301 newvalue = S3C2410_EXTINT_RISEEDGE;
302 break;
303
304 case IRQT_FALLING:
305 newvalue = S3C2410_EXTINT_FALLEDGE;
306 break;
307
308 case IRQT_BOTHEDGE:
309 newvalue = S3C2410_EXTINT_BOTHEDGE;
310 break;
311
312 case IRQT_LOW:
313 newvalue = S3C2410_EXTINT_LOWLEV;
314 break;
315
316 case IRQT_HIGH:
317 newvalue = S3C2410_EXTINT_HILEV;
318 break;
319
320 default:
321 printk(KERN_ERR "No such irq type %d", type);
322 return -1;
323 }
324
325 value = __raw_readl(extint_reg);
326 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
327 __raw_writel(value, extint_reg);
328
329 return 0; 34 return 0;
330} 35}
331 36
332static struct irq_chip s3c_irqext_chip = { 37static struct sysdev_driver s3c2410_irq_driver = {
333 .name = "s3c-ext", 38 .add = s3c2410_irq_add,
334 .mask = s3c_irqext_mask, 39 .suspend = s3c24xx_irq_suspend,
335 .unmask = s3c_irqext_unmask, 40 .resume = s3c24xx_irq_resume,
336 .ack = s3c_irqext_ack,
337 .set_type = s3c_irqext_type,
338 .set_wake = s3c_irqext_wake
339};
340
341static struct irq_chip s3c_irq_eint0t4 = {
342 .name = "s3c-ext0",
343 .ack = s3c_irq_ack,
344 .mask = s3c_irq_mask,
345 .unmask = s3c_irq_unmask,
346 .set_wake = s3c_irq_wake,
347 .set_type = s3c_irqext_type,
348};
349
350/* mask values for the parent registers for each of the interrupt types */
351
352#define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
353#define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
354#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
355#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
356
357
358/* UART0 */
359
360static void
361s3c_irq_uart0_mask(unsigned int irqno)
362{
363 s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
364}
365
366static void
367s3c_irq_uart0_unmask(unsigned int irqno)
368{
369 s3c_irqsub_unmask(irqno, INTMSK_UART0);
370}
371
372static void
373s3c_irq_uart0_ack(unsigned int irqno)
374{
375 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
376}
377
378static struct irq_chip s3c_irq_uart0 = {
379 .name = "s3c-uart0",
380 .mask = s3c_irq_uart0_mask,
381 .unmask = s3c_irq_uart0_unmask,
382 .ack = s3c_irq_uart0_ack,
383};
384
385/* UART1 */
386
387static void
388s3c_irq_uart1_mask(unsigned int irqno)
389{
390 s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
391}
392
393static void
394s3c_irq_uart1_unmask(unsigned int irqno)
395{
396 s3c_irqsub_unmask(irqno, INTMSK_UART1);
397}
398
399static void
400s3c_irq_uart1_ack(unsigned int irqno)
401{
402 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
403}
404
405static struct irq_chip s3c_irq_uart1 = {
406 .name = "s3c-uart1",
407 .mask = s3c_irq_uart1_mask,
408 .unmask = s3c_irq_uart1_unmask,
409 .ack = s3c_irq_uart1_ack,
410};
411
412/* UART2 */
413
414static void
415s3c_irq_uart2_mask(unsigned int irqno)
416{
417 s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
418}
419
420static void
421s3c_irq_uart2_unmask(unsigned int irqno)
422{
423 s3c_irqsub_unmask(irqno, INTMSK_UART2);
424}
425
426static void
427s3c_irq_uart2_ack(unsigned int irqno)
428{
429 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
430}
431
432static struct irq_chip s3c_irq_uart2 = {
433 .name = "s3c-uart2",
434 .mask = s3c_irq_uart2_mask,
435 .unmask = s3c_irq_uart2_unmask,
436 .ack = s3c_irq_uart2_ack,
437};
438
439/* ADC and Touchscreen */
440
441static void
442s3c_irq_adc_mask(unsigned int irqno)
443{
444 s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
445}
446
447static void
448s3c_irq_adc_unmask(unsigned int irqno)
449{
450 s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
451}
452
453static void
454s3c_irq_adc_ack(unsigned int irqno)
455{
456 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
457}
458
459static struct irq_chip s3c_irq_adc = {
460 .name = "s3c-adc",
461 .mask = s3c_irq_adc_mask,
462 .unmask = s3c_irq_adc_unmask,
463 .ack = s3c_irq_adc_ack,
464};
465
466/* irq demux for adc */
467static void s3c_irq_demux_adc(unsigned int irq,
468 struct irq_desc *desc)
469{
470 unsigned int subsrc, submsk;
471 unsigned int offset = 9;
472 struct irq_desc *mydesc;
473
474 /* read the current pending interrupts, and the mask
475 * for what it is available */
476
477 subsrc = __raw_readl(S3C2410_SUBSRCPND);
478 submsk = __raw_readl(S3C2410_INTSUBMSK);
479
480 subsrc &= ~submsk;
481 subsrc >>= offset;
482 subsrc &= 3;
483
484 if (subsrc != 0) {
485 if (subsrc & 1) {
486 mydesc = irq_desc + IRQ_TC;
487 desc_handle_irq(IRQ_TC, mydesc);
488 }
489 if (subsrc & 2) {
490 mydesc = irq_desc + IRQ_ADC;
491 desc_handle_irq(IRQ_ADC, mydesc);
492 }
493 }
494}
495
496static void s3c_irq_demux_uart(unsigned int start)
497{
498 unsigned int subsrc, submsk;
499 unsigned int offset = start - IRQ_S3CUART_RX0;
500 struct irq_desc *desc;
501
502 /* read the current pending interrupts, and the mask
503 * for what it is available */
504
505 subsrc = __raw_readl(S3C2410_SUBSRCPND);
506 submsk = __raw_readl(S3C2410_INTSUBMSK);
507
508 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
509 start, offset, subsrc, submsk);
510
511 subsrc &= ~submsk;
512 subsrc >>= offset;
513 subsrc &= 7;
514
515 if (subsrc != 0) {
516 desc = irq_desc + start;
517
518 if (subsrc & 1)
519 desc_handle_irq(start, desc);
520
521 desc++;
522
523 if (subsrc & 2)
524 desc_handle_irq(start+1, desc);
525
526 desc++;
527
528 if (subsrc & 4)
529 desc_handle_irq(start+2, desc);
530 }
531}
532
533/* uart demux entry points */
534
535static void
536s3c_irq_demux_uart0(unsigned int irq,
537 struct irq_desc *desc)
538{
539 irq = irq;
540 s3c_irq_demux_uart(IRQ_S3CUART_RX0);
541}
542
543static void
544s3c_irq_demux_uart1(unsigned int irq,
545 struct irq_desc *desc)
546{
547 irq = irq;
548 s3c_irq_demux_uart(IRQ_S3CUART_RX1);
549}
550
551static void
552s3c_irq_demux_uart2(unsigned int irq,
553 struct irq_desc *desc)
554{
555 irq = irq;
556 s3c_irq_demux_uart(IRQ_S3CUART_RX2);
557}
558
559static void
560s3c_irq_demux_extint8(unsigned int irq,
561 struct irq_desc *desc)
562{
563 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
564 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
565
566 eintpnd &= ~eintmsk;
567 eintpnd &= ~0xff; /* ignore lower irqs */
568
569 /* we may as well handle all the pending IRQs here */
570
571 while (eintpnd) {
572 irq = __ffs(eintpnd);
573 eintpnd &= ~(1<<irq);
574
575 irq += (IRQ_EINT4 - 4);
576 desc_handle_irq(irq, irq_desc + irq);
577 }
578
579}
580
581static void
582s3c_irq_demux_extint4t7(unsigned int irq,
583 struct irq_desc *desc)
584{
585 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
586 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
587
588 eintpnd &= ~eintmsk;
589 eintpnd &= 0xff; /* only lower irqs */
590
591 /* we may as well handle all the pending IRQs here */
592
593 while (eintpnd) {
594 irq = __ffs(eintpnd);
595 eintpnd &= ~(1<<irq);
596
597 irq += (IRQ_EINT4 - 4);
598
599 desc_handle_irq(irq, irq_desc + irq);
600 }
601}
602
603#ifdef CONFIG_PM
604
605static struct sleep_save irq_save[] = {
606 SAVE_ITEM(S3C2410_INTMSK),
607 SAVE_ITEM(S3C2410_INTSUBMSK),
608}; 41};
609 42
610/* the extint values move between the s3c2410/s3c2440 and the s3c2412 43static int s3c2410_irq_init(void)
611 * so we use an array to hold them, and to calculate the address of
612 * the register at run-time
613*/
614
615static unsigned long save_extint[3];
616static unsigned long save_eintflt[4];
617static unsigned long save_eintmask;
618
619int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
620{ 44{
621 unsigned int i; 45 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver);
622
623 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
624 save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
625
626 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
627 save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
628
629 s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
630 save_eintmask = __raw_readl(S3C24XX_EINTMASK);
631
632 return 0;
633} 46}
634 47
635int s3c24xx_irq_resume(struct sys_device *dev) 48arch_initcall(s3c2410_irq_init);
636{
637 unsigned int i;
638
639 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
640 __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
641
642 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
643 __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
644
645 s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
646 __raw_writel(save_eintmask, S3C24XX_EINTMASK);
647
648 return 0;
649}
650
651#else
652#define s3c24xx_irq_suspend NULL
653#define s3c24xx_irq_resume NULL
654#endif
655
656/* s3c24xx_init_irq
657 *
658 * Initialise S3C2410 IRQ system
659*/
660
661void __init s3c24xx_init_irq(void)
662{
663 unsigned long pend;
664 unsigned long last;
665 int irqno;
666 int i;
667
668 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
669
670 /* first, clear all interrupts pending... */
671
672 last = 0;
673 for (i = 0; i < 4; i++) {
674 pend = __raw_readl(S3C24XX_EINTPEND);
675
676 if (pend == 0 || pend == last)
677 break;
678
679 __raw_writel(pend, S3C24XX_EINTPEND);
680 printk("irq: clearing pending ext status %08x\n", (int)pend);
681 last = pend;
682 }
683
684 last = 0;
685 for (i = 0; i < 4; i++) {
686 pend = __raw_readl(S3C2410_INTPND);
687
688 if (pend == 0 || pend == last)
689 break;
690
691 __raw_writel(pend, S3C2410_SRCPND);
692 __raw_writel(pend, S3C2410_INTPND);
693 printk("irq: clearing pending status %08x\n", (int)pend);
694 last = pend;
695 }
696
697 last = 0;
698 for (i = 0; i < 4; i++) {
699 pend = __raw_readl(S3C2410_SUBSRCPND);
700
701 if (pend == 0 || pend == last)
702 break;
703
704 printk("irq: clearing subpending status %08x\n", (int)pend);
705 __raw_writel(pend, S3C2410_SUBSRCPND);
706 last = pend;
707 }
708
709 /* register the main interrupts */
710
711 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
712
713 for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
714 /* set all the s3c2410 internal irqs */
715
716 switch (irqno) {
717 /* deal with the special IRQs (cascaded) */
718
719 case IRQ_EINT4t7:
720 case IRQ_EINT8t23:
721 case IRQ_UART0:
722 case IRQ_UART1:
723 case IRQ_UART2:
724 case IRQ_ADCPARENT:
725 set_irq_chip(irqno, &s3c_irq_level_chip);
726 set_irq_handler(irqno, handle_level_irq);
727 break;
728
729 case IRQ_RESERVED6:
730 case IRQ_RESERVED24:
731 /* no IRQ here */
732 break;
733
734 default:
735 //irqdbf("registering irq %d (s3c irq)\n", irqno);
736 set_irq_chip(irqno, &s3c_irq_chip);
737 set_irq_handler(irqno, handle_edge_irq);
738 set_irq_flags(irqno, IRQF_VALID);
739 }
740 }
741
742 /* setup the cascade irq handlers */
743
744 set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
745 set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
746
747 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
748 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
749 set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
750 set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
751
752 /* external interrupts */
753
754 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
755 irqdbf("registering irq %d (ext int)\n", irqno);
756 set_irq_chip(irqno, &s3c_irq_eint0t4);
757 set_irq_handler(irqno, handle_edge_irq);
758 set_irq_flags(irqno, IRQF_VALID);
759 }
760
761 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
762 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
763 set_irq_chip(irqno, &s3c_irqext_chip);
764 set_irq_handler(irqno, handle_edge_irq);
765 set_irq_flags(irqno, IRQF_VALID);
766 }
767
768 /* register the uart interrupts */
769
770 irqdbf("s3c2410: registering external interrupts\n");
771
772 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
773 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
774 set_irq_chip(irqno, &s3c_irq_uart0);
775 set_irq_handler(irqno, handle_level_irq);
776 set_irq_flags(irqno, IRQF_VALID);
777 }
778
779 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
780 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
781 set_irq_chip(irqno, &s3c_irq_uart1);
782 set_irq_handler(irqno, handle_level_irq);
783 set_irq_flags(irqno, IRQF_VALID);
784 }
785
786 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
787 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
788 set_irq_chip(irqno, &s3c_irq_uart2);
789 set_irq_handler(irqno, handle_level_irq);
790 set_irq_flags(irqno, IRQF_VALID);
791 }
792
793 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
794 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
795 set_irq_chip(irqno, &s3c_irq_adc);
796 set_irq_handler(irqno, handle_edge_irq);
797 set_irq_flags(irqno, IRQF_VALID);
798 }
799
800 irqdbf("s3c2410: registered interrupt handlers\n");
801}
diff --git a/arch/arm/mach-s3c2410/irq.h b/arch/arm/mach-s3c2410/irq.h
deleted file mode 100644
index e5913da3b919..000000000000
--- a/arch/arm/mach-s3c2410/irq.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/* arch/arm/mach-s3c2410/irq.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#define irqdbf(x...)
14#define irqdbf2(x...)
15
16#define EXTINT_OFF (IRQ_EINT4 - 4)
17
18extern struct irq_chip s3c_irq_level_chip;
19
20static inline void
21s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
22 int subcheck)
23{
24 unsigned long mask;
25 unsigned long submask;
26
27 submask = __raw_readl(S3C2410_INTSUBMSK);
28 mask = __raw_readl(S3C2410_INTMSK);
29
30 submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
31
32 /* check to see if we need to mask the parent IRQ */
33
34 if ((submask & subcheck) == subcheck) {
35 __raw_writel(mask | parentbit, S3C2410_INTMSK);
36 }
37
38 /* write back masks */
39 __raw_writel(submask, S3C2410_INTSUBMSK);
40
41}
42
43static inline void
44s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
45{
46 unsigned long mask;
47 unsigned long submask;
48
49 submask = __raw_readl(S3C2410_INTSUBMSK);
50 mask = __raw_readl(S3C2410_INTMSK);
51
52 submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
53 mask &= ~parentbit;
54
55 /* write back masks */
56 __raw_writel(submask, S3C2410_INTSUBMSK);
57 __raw_writel(mask, S3C2410_INTMSK);
58}
59
60
61static inline void
62s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
63{
64 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
65
66 s3c_irqsub_mask(irqno, parentmask, group);
67
68 __raw_writel(bit, S3C2410_SUBSRCPND);
69
70 /* only ack parent if we've got all the irqs (seems we must
71 * ack, all and hope that the irq system retriggers ok when
72 * the interrupt goes off again)
73 */
74
75 if (1) {
76 __raw_writel(parentmask, S3C2410_SRCPND);
77 __raw_writel(parentmask, S3C2410_INTPND);
78 }
79}
80
81static inline void
82s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
83{
84 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
85
86 __raw_writel(bit, S3C2410_SUBSRCPND);
87
88 /* only ack parent if we've got all the irqs (seems we must
89 * ack, all and hope that the irq system retriggers ok when
90 * the interrupt goes off again)
91 */
92
93 if (1) {
94 __raw_writel(parentmask, S3C2410_SRCPND);
95 __raw_writel(parentmask, S3C2410_INTPND);
96 }
97}
98
99/* exported for use in arch/arm/mach-s3c2410 */
100
101#ifdef CONFIG_PM
102extern int s3c_irq_wake(unsigned int irqno, unsigned int state);
103#else
104#define s3c_irq_wake NULL
105#endif
106
107extern int s3c_irqext_type(unsigned int irq, unsigned int type);
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 817e2c684410..d54cda1b3006 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -1,4 +1,4 @@
1/*********************************************************************** 1/* linux/arch/arm/mach-s3c2410/mach-amlm5900.c
2 * 2 *
3 * linux/arch/arm/mach-s3c2410/mach-amlm5900.c 3 * linux/arch/arm/mach-s3c2410/mach-amlm5900.c
4 * 4 *
@@ -52,8 +52,8 @@
52#include <asm/arch/regs-lcd.h> 52#include <asm/arch/regs-lcd.h>
53#include <asm/arch/regs-gpio.h> 53#include <asm/arch/regs-gpio.h>
54 54
55#include "devs.h" 55#include <asm/plat-s3c24xx/devs.h>
56#include "cpu.h" 56#include <asm/plat-s3c24xx/cpu.h>
57 57
58#ifdef CONFIG_MTD_PARTITIONS 58#ifdef CONFIG_MTD_PARTITIONS
59 59
diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c
deleted file mode 100644
index 0fad0c2fe07b..000000000000
--- a/arch/arm/mach-s3c2410/mach-anubis.c
+++ /dev/null
@@ -1,325 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-anubis.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20
21#include <asm/mach/arch.h>
22#include <asm/mach/map.h>
23#include <asm/mach/irq.h>
24
25#include <asm/arch/anubis-map.h>
26#include <asm/arch/anubis-irq.h>
27#include <asm/arch/anubis-cpld.h>
28
29#include <asm/hardware.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/mach-types.h>
33
34#include <asm/arch/regs-serial.h>
35#include <asm/arch/regs-gpio.h>
36#include <asm/arch/regs-mem.h>
37#include <asm/arch/regs-lcd.h>
38#include <asm/arch/nand.h>
39
40#include <linux/mtd/mtd.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/nand_ecc.h>
43#include <linux/mtd/partitions.h>
44
45#include "clock.h"
46#include "devs.h"
47#include "cpu.h"
48
49#define COPYRIGHT ", (c) 2005 Simtec Electronics"
50
51static struct map_desc anubis_iodesc[] __initdata = {
52 /* ISA IO areas */
53
54 {
55 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
56 .pfn = __phys_to_pfn(0x0),
57 .length = SZ_4M,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = (u32)S3C24XX_VA_ISA_WORD,
61 .pfn = __phys_to_pfn(0x0),
62 .length = SZ_4M,
63 .type = MT_DEVICE,
64 },
65
66 /* we could possibly compress the next set down into a set of smaller tables
67 * pagetables, but that would mean using an L2 section, and it still means
68 * we cannot actually feed the same register to an LDR due to 16K spacing
69 */
70
71 /* CPLD control registers */
72
73 {
74 .virtual = (u32)ANUBIS_VA_CTRL1,
75 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
76 .length = SZ_4K,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = (u32)ANUBIS_VA_CTRL2,
80 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL2),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 },
84};
85
86#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
87#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
88#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
89
90static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
91 [0] = {
92 .name = "uclk",
93 .divisor = 1,
94 .min_baud = 0,
95 .max_baud = 0,
96 },
97 [1] = {
98 .name = "pclk",
99 .divisor = 1,
100 .min_baud = 0,
101 .max_baud = 0,
102 }
103};
104
105
106static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
107 [0] = {
108 .hwport = 0,
109 .flags = 0,
110 .ucon = UCON,
111 .ulcon = ULCON,
112 .ufcon = UFCON,
113 .clocks = anubis_serial_clocks,
114 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
115 },
116 [1] = {
117 .hwport = 2,
118 .flags = 0,
119 .ucon = UCON,
120 .ulcon = ULCON,
121 .ufcon = UFCON,
122 .clocks = anubis_serial_clocks,
123 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
124 },
125};
126
127/* NAND Flash on Anubis board */
128
129static int external_map[] = { 2 };
130static int chip0_map[] = { 0 };
131static int chip1_map[] = { 1 };
132
133static struct mtd_partition anubis_default_nand_part[] = {
134 [0] = {
135 .name = "Boot Agent",
136 .size = SZ_16K,
137 .offset = 0,
138 },
139 [1] = {
140 .name = "/boot",
141 .size = SZ_4M - SZ_16K,
142 .offset = SZ_16K,
143 },
144 [2] = {
145 .name = "user1",
146 .offset = SZ_4M,
147 .size = SZ_32M - SZ_4M,
148 },
149 [3] = {
150 .name = "user2",
151 .offset = SZ_32M,
152 .size = MTDPART_SIZ_FULL,
153 }
154};
155
156/* the Anubis has 3 selectable slots for nand-flash, the two
157 * on-board chip areas, as well as the external slot.
158 *
159 * Note, there is no current hot-plug support for the External
160 * socket.
161*/
162
163static struct s3c2410_nand_set anubis_nand_sets[] = {
164 [1] = {
165 .name = "External",
166 .nr_chips = 1,
167 .nr_map = external_map,
168 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
169 .partitions = anubis_default_nand_part,
170 },
171 [0] = {
172 .name = "chip0",
173 .nr_chips = 1,
174 .nr_map = chip0_map,
175 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
176 .partitions = anubis_default_nand_part,
177 },
178 [2] = {
179 .name = "chip1",
180 .nr_chips = 1,
181 .nr_map = chip1_map,
182 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
183 .partitions = anubis_default_nand_part,
184 },
185};
186
187static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
188{
189 unsigned int tmp;
190
191 slot = set->nr_map[slot] & 3;
192
193 pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
194 slot, set, set->nr_map);
195
196 tmp = __raw_readb(ANUBIS_VA_CTRL1);
197 tmp &= ~ANUBIS_CTRL1_NANDSEL;
198 tmp |= slot;
199
200 pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
201
202 __raw_writeb(tmp, ANUBIS_VA_CTRL1);
203}
204
205static struct s3c2410_platform_nand anubis_nand_info = {
206 .tacls = 25,
207 .twrph0 = 55,
208 .twrph1 = 40,
209 .nr_sets = ARRAY_SIZE(anubis_nand_sets),
210 .sets = anubis_nand_sets,
211 .select_chip = anubis_nand_select,
212};
213
214/* IDE channels */
215
216static struct resource anubis_ide0_resource[] = {
217 {
218 .start = S3C2410_CS3,
219 .end = S3C2410_CS3 + (8*32) - 1,
220 .flags = IORESOURCE_MEM,
221 }, {
222 .start = S3C2410_CS3 + (1<<26),
223 .end = S3C2410_CS3 + (1<<26) + (8*32) - 1,
224 .flags = IORESOURCE_MEM,
225 }, {
226 .start = IRQ_IDE0,
227 .end = IRQ_IDE0,
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device anubis_device_ide0 = {
233 .name = "simtec-ide",
234 .id = 0,
235 .num_resources = ARRAY_SIZE(anubis_ide0_resource),
236 .resource = anubis_ide0_resource,
237};
238
239static struct resource anubis_ide1_resource[] = {
240 {
241 .start = S3C2410_CS4,
242 .end = S3C2410_CS4 + (8*32) - 1,
243 .flags = IORESOURCE_MEM,
244 }, {
245 .start = S3C2410_CS4 + (1<<26),
246 .end = S3C2410_CS4 + (1<<26) + (8*32) - 1,
247 .flags = IORESOURCE_MEM,
248 }, {
249 .start = IRQ_IDE0,
250 .end = IRQ_IDE0,
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255
256static struct platform_device anubis_device_ide1 = {
257 .name = "simtec-ide",
258 .id = 1,
259 .num_resources = ARRAY_SIZE(anubis_ide1_resource),
260 .resource = anubis_ide1_resource,
261};
262
263/* Standard Anubis devices */
264
265static struct platform_device *anubis_devices[] __initdata = {
266 &s3c_device_usb,
267 &s3c_device_wdt,
268 &s3c_device_adc,
269 &s3c_device_i2c,
270 &s3c_device_rtc,
271 &s3c_device_nand,
272 &anubis_device_ide0,
273 &anubis_device_ide1,
274};
275
276static struct clk *anubis_clocks[] = {
277 &s3c24xx_dclk0,
278 &s3c24xx_dclk1,
279 &s3c24xx_clkout0,
280 &s3c24xx_clkout1,
281 &s3c24xx_uclk,
282};
283
284static struct s3c24xx_board anubis_board __initdata = {
285 .devices = anubis_devices,
286 .devices_count = ARRAY_SIZE(anubis_devices),
287 .clocks = anubis_clocks,
288 .clocks_count = ARRAY_SIZE(anubis_clocks),
289};
290
291static void __init anubis_map_io(void)
292{
293 /* initialise the clocks */
294
295 s3c24xx_dclk0.parent = NULL;
296 s3c24xx_dclk0.rate = 12*1000*1000;
297
298 s3c24xx_dclk1.parent = NULL;
299 s3c24xx_dclk1.rate = 24*1000*1000;
300
301 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
302 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
303
304 s3c24xx_uclk.parent = &s3c24xx_clkout1;
305
306 s3c_device_nand.dev.platform_data = &anubis_nand_info;
307
308 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
309 s3c24xx_init_clocks(0);
310 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
311 s3c24xx_set_board(&anubis_board);
312
313 /* ensure that the GPIO is setup */
314 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
315}
316
317MACHINE_START(ANUBIS, "Simtec-Anubis")
318 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
319 .phys_io = S3C2410_PA_UART,
320 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
321 .boot_params = S3C2410_SDRAM_PA + 0x100,
322 .map_io = anubis_map_io,
323 .init_irq = s3c24xx_init_irq,
324 .timer = &s3c24xx_timer,
325MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index b8b76757ec54..7b81296427eb 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -50,9 +50,9 @@
50 50
51#include <linux/serial_8250.h> 51#include <linux/serial_8250.h>
52 52
53#include "clock.h" 53#include <asm/plat-s3c24xx/clock.h>
54#include "devs.h" 54#include <asm/plat-s3c24xx/devs.h>
55#include "cpu.h" 55#include <asm/plat-s3c24xx/cpu.h>
56#include "usb-simtec.h" 56#include "usb-simtec.h"
57 57
58#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics" 58#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 15b625eae499..5af26e177966 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -38,10 +38,10 @@
38#include <asm/arch/h1940-latch.h> 38#include <asm/arch/h1940-latch.h>
39#include <asm/arch/fb.h> 39#include <asm/arch/fb.h>
40 40
41#include "clock.h" 41#include <asm/plat-s3c24xx/clock.h>
42#include "devs.h" 42#include <asm/plat-s3c24xx/devs.h>
43#include "cpu.h" 43#include <asm/plat-s3c24xx/cpu.h>
44#include "pm.h" 44#include <asm/plat-s3c24xx/pm.h>
45 45
46static struct map_desc h1940_iodesc[] __initdata = { 46static struct map_desc h1940_iodesc[] __initdata = {
47 [0] = { 47 [0] = {
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 0411e9adb54d..dbac7311f98f 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -38,10 +38,10 @@
38#include <asm/arch/regs-gpio.h> 38#include <asm/arch/regs-gpio.h>
39#include <asm/arch/iic.h> 39#include <asm/arch/iic.h>
40 40
41#include "s3c2410.h" 41#include <asm/plat-s3c24xx/s3c2410.h>
42#include "clock.h" 42#include <asm/plat-s3c24xx/clock.h>
43#include "devs.h" 43#include <asm/plat-s3c24xx/devs.h>
44#include "cpu.h" 44#include <asm/plat-s3c24xx/cpu.h>
45 45
46static struct map_desc n30_iodesc[] __initdata = { 46static struct map_desc n30_iodesc[] __initdata = {
47 /* nothing here yet */ 47 /* nothing here yet */
diff --git a/arch/arm/mach-s3c2410/mach-nexcoder.c b/arch/arm/mach-s3c2410/mach-nexcoder.c
deleted file mode 100644
index d6dfdad8c90b..000000000000
--- a/arch/arm/mach-s3c2410/mach-nexcoder.c
+++ /dev/null
@@ -1,158 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-nexcoder.c
2 *
3 * Copyright (c) 2004 Nex Vision
4 * Guillaume GOURAT <guillaume.gourat@nexvision.tv>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Modifications:
11 * 15-10-2004 GG Created initial version
12 * 12-03-2005 BJD Updated for release
13 */
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/string.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24
25#include <linux/mtd/map.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
31#include <asm/setup.h>
32#include <asm/hardware.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/mach-types.h>
36
37//#include <asm/debug-ll.h>
38#include <asm/arch/regs-gpio.h>
39#include <asm/arch/regs-serial.h>
40
41#include "s3c2410.h"
42#include "s3c2440.h"
43#include "clock.h"
44#include "devs.h"
45#include "cpu.h"
46
47static struct map_desc nexcoder_iodesc[] __initdata = {
48 /* nothing here yet */
49};
50
51#define UCON S3C2410_UCON_DEFAULT
52#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
53#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE
54
55static struct s3c2410_uartcfg nexcoder_uartcfgs[] __initdata = {
56 [0] = {
57 .hwport = 0,
58 .flags = 0,
59 .ucon = UCON,
60 .ulcon = ULCON,
61 .ufcon = UFCON,
62 },
63 [1] = {
64 .hwport = 1,
65 .flags = 0,
66 .ucon = UCON,
67 .ulcon = ULCON,
68 .ufcon = UFCON,
69 },
70 [2] = {
71 .hwport = 2,
72 .flags = 0,
73 .ucon = UCON,
74 .ulcon = ULCON,
75 .ufcon = UFCON,
76 }
77};
78
79/* NOR Flash on NexVision NexCoder 2440 board */
80
81static struct resource nexcoder_nor_resource[] = {
82 [0] = {
83 .start = S3C2410_CS0,
84 .end = S3C2410_CS0 + (8*1024*1024) - 1,
85 .flags = IORESOURCE_MEM,
86 }
87};
88
89static struct map_info nexcoder_nor_map = {
90 .bankwidth = 2,
91};
92
93static struct platform_device nexcoder_device_nor = {
94 .name = "mtd-flash",
95 .id = -1,
96 .num_resources = ARRAY_SIZE(nexcoder_nor_resource),
97 .resource = nexcoder_nor_resource,
98 .dev =
99 {
100 .platform_data = &nexcoder_nor_map,
101 }
102};
103
104/* Standard Nexcoder devices */
105
106static struct platform_device *nexcoder_devices[] __initdata = {
107 &s3c_device_usb,
108 &s3c_device_lcd,
109 &s3c_device_wdt,
110 &s3c_device_i2c,
111 &s3c_device_iis,
112 &s3c_device_rtc,
113 &s3c_device_camif,
114 &s3c_device_spi0,
115 &s3c_device_spi1,
116 &nexcoder_device_nor,
117};
118
119static struct s3c24xx_board nexcoder_board __initdata = {
120 .devices = nexcoder_devices,
121 .devices_count = ARRAY_SIZE(nexcoder_devices),
122};
123
124
125static void __init nexcoder_sensorboard_init(void)
126{
127 // Initialize SCCB bus
128 s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL
129 s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP);
130 s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA
131 s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP);
132
133 // Power up the sensor board
134 s3c2410_gpio_setpin(S3C2410_GPF1, 1);
135 s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN
136 s3c2410_gpio_setpin(S3C2410_GPF2, 0);
137 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN
138}
139
140static void __init nexcoder_map_io(void)
141{
142 s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
143 s3c24xx_init_clocks(0);
144 s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
145 s3c24xx_set_board(&nexcoder_board);
146 nexcoder_sensorboard_init();
147}
148
149
150MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
151 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
152 .phys_io = S3C2410_PA_UART,
153 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
154 .boot_params = S3C2410_SDRAM_PA + 0x100,
155 .map_io = nexcoder_map_io,
156 .init_irq = s3c24xx_init_irq,
157 .timer = &s3c24xx_timer,
158MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-osiris.c b/arch/arm/mach-s3c2410/mach-osiris.c
deleted file mode 100644
index 37b40850c9b9..000000000000
--- a/arch/arm/mach-s3c2410/mach-osiris.c
+++ /dev/null
@@ -1,303 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-osiris.c
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/device.h>
19#include <linux/serial_core.h>
20
21#include <asm/mach/arch.h>
22#include <asm/mach/map.h>
23#include <asm/mach/irq.h>
24
25#include <asm/arch/osiris-map.h>
26#include <asm/arch/osiris-cpld.h>
27
28#include <asm/hardware.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/mach-types.h>
32
33#include <asm/arch/regs-serial.h>
34#include <asm/arch/regs-gpio.h>
35#include <asm/arch/regs-mem.h>
36#include <asm/arch/regs-lcd.h>
37#include <asm/arch/nand.h>
38
39#include <linux/mtd/mtd.h>
40#include <linux/mtd/nand.h>
41#include <linux/mtd/nand_ecc.h>
42#include <linux/mtd/partitions.h>
43
44#include "clock.h"
45#include "devs.h"
46#include "cpu.h"
47
48/* onboard perihpheral map */
49
50static struct map_desc osiris_iodesc[] __initdata = {
51 /* ISA IO areas (may be over-written later) */
52
53 {
54 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
55 .pfn = __phys_to_pfn(S3C2410_CS5),
56 .length = SZ_16M,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (u32)S3C24XX_VA_ISA_WORD,
60 .pfn = __phys_to_pfn(S3C2410_CS5),
61 .length = SZ_16M,
62 .type = MT_DEVICE,
63 },
64
65 /* CPLD control registers */
66
67 {
68 .virtual = (u32)OSIRIS_VA_CTRL1,
69 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
70 .length = SZ_16K,
71 .type = MT_DEVICE,
72 }, {
73 .virtual = (u32)OSIRIS_VA_CTRL2,
74 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
75 .length = SZ_16K,
76 .type = MT_DEVICE,
77 },
78};
79
80#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
81#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
82#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
83
84static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
85 [0] = {
86 .name = "uclk",
87 .divisor = 1,
88 .min_baud = 0,
89 .max_baud = 0,
90 },
91 [1] = {
92 .name = "pclk",
93 .divisor = 1,
94 .min_baud = 0,
95 .max_baud = 0,
96 }
97};
98
99static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
100 [0] = {
101 .hwport = 0,
102 .flags = 0,
103 .ucon = UCON,
104 .ulcon = ULCON,
105 .ufcon = UFCON,
106 .clocks = osiris_serial_clocks,
107 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
108 },
109 [1] = {
110 .hwport = 1,
111 .flags = 0,
112 .ucon = UCON,
113 .ulcon = ULCON,
114 .ufcon = UFCON,
115 .clocks = osiris_serial_clocks,
116 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
117 },
118 [2] = {
119 .hwport = 2,
120 .flags = 0,
121 .ucon = UCON,
122 .ulcon = ULCON,
123 .ufcon = UFCON,
124 .clocks = osiris_serial_clocks,
125 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
126 }
127};
128
129/* NAND Flash on Osiris board */
130
131static int external_map[] = { 2 };
132static int chip0_map[] = { 0 };
133static int chip1_map[] = { 1 };
134
135static struct mtd_partition osiris_default_nand_part[] = {
136 [0] = {
137 .name = "Boot Agent",
138 .size = SZ_16K,
139 .offset = 0,
140 },
141 [1] = {
142 .name = "/boot",
143 .size = SZ_4M - SZ_16K,
144 .offset = SZ_16K,
145 },
146 [2] = {
147 .name = "user1",
148 .offset = SZ_4M,
149 .size = SZ_32M - SZ_4M,
150 },
151 [3] = {
152 .name = "user2",
153 .offset = SZ_32M,
154 .size = MTDPART_SIZ_FULL,
155 }
156};
157
158/* the Osiris has 3 selectable slots for nand-flash, the two
159 * on-board chip areas, as well as the external slot.
160 *
161 * Note, there is no current hot-plug support for the External
162 * socket.
163*/
164
165static struct s3c2410_nand_set osiris_nand_sets[] = {
166 [1] = {
167 .name = "External",
168 .nr_chips = 1,
169 .nr_map = external_map,
170 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
171 .partitions = osiris_default_nand_part,
172 },
173 [0] = {
174 .name = "chip0",
175 .nr_chips = 1,
176 .nr_map = chip0_map,
177 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
178 .partitions = osiris_default_nand_part,
179 },
180 [2] = {
181 .name = "chip1",
182 .nr_chips = 1,
183 .nr_map = chip1_map,
184 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
185 .partitions = osiris_default_nand_part,
186 },
187};
188
189static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
190{
191 unsigned int tmp;
192
193 slot = set->nr_map[slot] & 3;
194
195 pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
196 slot, set, set->nr_map);
197
198 tmp = __raw_readb(OSIRIS_VA_CTRL1);
199 tmp &= ~OSIRIS_CTRL1_NANDSEL;
200 tmp |= slot;
201
202 pr_debug("osiris_nand: ctrl1 now %02x\n", tmp);
203
204 __raw_writeb(tmp, OSIRIS_VA_CTRL1);
205}
206
207static struct s3c2410_platform_nand osiris_nand_info = {
208 .tacls = 25,
209 .twrph0 = 60,
210 .twrph1 = 60,
211 .nr_sets = ARRAY_SIZE(osiris_nand_sets),
212 .sets = osiris_nand_sets,
213 .select_chip = osiris_nand_select,
214};
215
216/* PCMCIA control and configuration */
217
218static struct resource osiris_pcmcia_resource[] = {
219 [0] = {
220 .start = 0x0f000000,
221 .end = 0x0f100000,
222 .flags = IORESOURCE_MEM,
223 },
224 [1] = {
225 .start = 0x0c000000,
226 .end = 0x0c100000,
227 .flags = IORESOURCE_MEM,
228 }
229};
230
231static struct platform_device osiris_pcmcia = {
232 .name = "osiris-pcmcia",
233 .id = -1,
234 .num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
235 .resource = osiris_pcmcia_resource,
236};
237
238/* Standard Osiris devices */
239
240static struct platform_device *osiris_devices[] __initdata = {
241 &s3c_device_i2c,
242 &s3c_device_nand,
243 &osiris_pcmcia,
244};
245
246static struct clk *osiris_clocks[] = {
247 &s3c24xx_dclk0,
248 &s3c24xx_dclk1,
249 &s3c24xx_clkout0,
250 &s3c24xx_clkout1,
251 &s3c24xx_uclk,
252};
253
254static struct s3c24xx_board osiris_board __initdata = {
255 .devices = osiris_devices,
256 .devices_count = ARRAY_SIZE(osiris_devices),
257 .clocks = osiris_clocks,
258 .clocks_count = ARRAY_SIZE(osiris_clocks),
259};
260
261static void __init osiris_map_io(void)
262{
263 unsigned long flags;
264
265 /* initialise the clocks */
266
267 s3c24xx_dclk0.parent = NULL;
268 s3c24xx_dclk0.rate = 12*1000*1000;
269
270 s3c24xx_dclk1.parent = NULL;
271 s3c24xx_dclk1.rate = 24*1000*1000;
272
273 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
274 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
275
276 s3c24xx_uclk.parent = &s3c24xx_clkout1;
277
278 s3c_device_nand.dev.platform_data = &osiris_nand_info;
279
280 s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
281 s3c24xx_init_clocks(0);
282 s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
283 s3c24xx_set_board(&osiris_board);
284
285 /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
286
287 local_irq_save(flags);
288 __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
289 local_irq_restore(flags);
290
291 /* write-protect line to the NAND */
292 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
293}
294
295MACHINE_START(OSIRIS, "Simtec-OSIRIS")
296 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
297 .phys_io = S3C2410_PA_UART,
298 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
299 .boot_params = S3C2410_SDRAM_PA + 0x100,
300 .map_io = osiris_map_io,
301 .init_irq = s3c24xx_init_irq,
302 .timer = &s3c24xx_timer,
303MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index 2c738b375e4d..c78ab75b44f3 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -32,10 +32,10 @@
32#include <asm/arch/regs-serial.h> 32#include <asm/arch/regs-serial.h>
33#include <asm/arch/regs-gpio.h> 33#include <asm/arch/regs-gpio.h>
34 34
35#include "s3c2410.h" 35#include <asm/plat-s3c24xx/s3c2410.h>
36#include "clock.h" 36#include <asm/plat-s3c24xx/clock.h>
37#include "devs.h" 37#include <asm/plat-s3c24xx/devs.h>
38#include "cpu.h" 38#include <asm/plat-s3c24xx/cpu.h>
39 39
40static struct map_desc otom11_iodesc[] __initdata = { 40static struct map_desc otom11_iodesc[] __initdata = {
41 /* Device area */ 41 /* Device area */
diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c
deleted file mode 100644
index ecbcdf79d739..000000000000
--- a/arch/arm/mach-s3c2410/mach-rx3715.c
+++ /dev/null
@@ -1,244 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-rx3715.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.handhelds.org/projects/rx3715.html
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/tty.h>
21#include <linux/console.h>
22#include <linux/platform_device.h>
23#include <linux/serial_core.h>
24#include <linux/serial.h>
25
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/nand_ecc.h>
29#include <linux/mtd/partitions.h>
30
31#include <asm/mach/arch.h>
32#include <asm/mach/map.h>
33#include <asm/mach/irq.h>
34
35#include <asm/hardware.h>
36#include <asm/hardware/iomd.h>
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/mach-types.h>
40
41#include <asm/arch/regs-serial.h>
42#include <asm/arch/regs-gpio.h>
43#include <asm/arch/regs-lcd.h>
44
45#include <asm/arch/h1940.h>
46#include <asm/arch/nand.h>
47#include <asm/arch/fb.h>
48
49#include "clock.h"
50#include "devs.h"
51#include "cpu.h"
52#include "pm.h"
53
54static struct map_desc rx3715_iodesc[] __initdata = {
55 /* dump ISA space somewhere unused */
56
57 {
58 .virtual = (u32)S3C24XX_VA_ISA_WORD,
59 .pfn = __phys_to_pfn(S3C2410_CS3),
60 .length = SZ_1M,
61 .type = MT_DEVICE,
62 }, {
63 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
64 .pfn = __phys_to_pfn(S3C2410_CS3),
65 .length = SZ_1M,
66 .type = MT_DEVICE,
67 },
68};
69
70
71static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
72 [0] = {
73 .name = "fclk",
74 .divisor = 0,
75 .min_baud = 0,
76 .max_baud = 0,
77 }
78};
79
80static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
81 [0] = {
82 .hwport = 0,
83 .flags = 0,
84 .ucon = 0x3c5,
85 .ulcon = 0x03,
86 .ufcon = 0x51,
87 .clocks = rx3715_serial_clocks,
88 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
89 },
90 [1] = {
91 .hwport = 1,
92 .flags = 0,
93 .ucon = 0x3c5,
94 .ulcon = 0x03,
95 .ufcon = 0x00,
96 .clocks = rx3715_serial_clocks,
97 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
98 },
99 /* IR port */
100 [2] = {
101 .hwport = 2,
102 .uart_flags = UPF_CONS_FLOW,
103 .ucon = 0x3c5,
104 .ulcon = 0x43,
105 .ufcon = 0x51,
106 .clocks = rx3715_serial_clocks,
107 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
108 }
109};
110
111/* framebuffer lcd controller information */
112
113static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = {
114 .regs = {
115 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \
116 S3C2410_LCDCON1_TFT | \
117 S3C2410_LCDCON1_CLKVAL(0x0C),
118
119 .lcdcon2 = S3C2410_LCDCON2_VBPD(5) | \
120 S3C2410_LCDCON2_LINEVAL(319) | \
121 S3C2410_LCDCON2_VFPD(6) | \
122 S3C2410_LCDCON2_VSPW(2),
123
124 .lcdcon3 = S3C2410_LCDCON3_HBPD(35) | \
125 S3C2410_LCDCON3_HOZVAL(239) | \
126 S3C2410_LCDCON3_HFPD(35),
127
128 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | \
129 S3C2410_LCDCON4_HSPW(7),
130
131 .lcdcon5 = S3C2410_LCDCON5_INVVLINE |
132 S3C2410_LCDCON5_FRM565 |
133 S3C2410_LCDCON5_HWSWP,
134 },
135
136 .lpcsel = 0xf82,
137
138 .gpccon = 0xaa955699,
139 .gpccon_mask = 0xffc003cc,
140 .gpcup = 0x0000ffff,
141 .gpcup_mask = 0xffffffff,
142
143 .gpdcon = 0xaa95aaa1,
144 .gpdcon_mask = 0xffc0fff0,
145 .gpdup = 0x0000faff,
146 .gpdup_mask = 0xffffffff,
147
148 .fixed_syncs = 1,
149 .width = 240,
150 .height = 320,
151
152 .xres = {
153 .min = 240,
154 .max = 240,
155 .defval = 240,
156 },
157
158 .yres = {
159 .max = 320,
160 .min = 320,
161 .defval = 320,
162 },
163
164 .bpp = {
165 .min = 16,
166 .max = 16,
167 .defval = 16,
168 },
169};
170
171static struct mtd_partition rx3715_nand_part[] = {
172 [0] = {
173 .name = "Whole Flash",
174 .offset = 0,
175 .size = MTDPART_SIZ_FULL,
176 .mask_flags = MTD_WRITEABLE,
177 }
178};
179
180static struct s3c2410_nand_set rx3715_nand_sets[] = {
181 [0] = {
182 .name = "Internal",
183 .nr_chips = 1,
184 .nr_partitions = ARRAY_SIZE(rx3715_nand_part),
185 .partitions = rx3715_nand_part,
186 },
187};
188
189static struct s3c2410_platform_nand rx3715_nand_info = {
190 .tacls = 25,
191 .twrph0 = 50,
192 .twrph1 = 15,
193 .nr_sets = ARRAY_SIZE(rx3715_nand_sets),
194 .sets = rx3715_nand_sets,
195};
196
197static struct platform_device *rx3715_devices[] __initdata = {
198 &s3c_device_usb,
199 &s3c_device_lcd,
200 &s3c_device_wdt,
201 &s3c_device_i2c,
202 &s3c_device_iis,
203 &s3c_device_nand,
204};
205
206static struct s3c24xx_board rx3715_board __initdata = {
207 .devices = rx3715_devices,
208 .devices_count = ARRAY_SIZE(rx3715_devices)
209};
210
211static void __init rx3715_map_io(void)
212{
213 s3c_device_nand.dev.platform_data = &rx3715_nand_info;
214
215 s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
216 s3c24xx_init_clocks(16934000);
217 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
218 s3c24xx_set_board(&rx3715_board);
219}
220
221static void __init rx3715_init_irq(void)
222{
223 s3c24xx_init_irq();
224}
225
226static void __init rx3715_init_machine(void)
227{
228 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
229 s3c2410_pm_init();
230
231 s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
232}
233
234
235MACHINE_START(RX3715, "IPAQ-RX3715")
236 /* Maintainer: Ben Dooks <ben@fluff.org> */
237 .phys_io = S3C2410_PA_UART,
238 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
239 .boot_params = S3C2410_SDRAM_PA + 0x100,
240 .map_io = rx3715_map_io,
241 .init_irq = rx3715_init_irq,
242 .init_machine = rx3715_init_machine,
243 .timer = &s3c24xx_timer,
244MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 01c0c986d827..57b8a80f33d0 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -1,4 +1,4 @@
1/*********************************************************************** 1/* linux/arch/arm/mach-s3c2410/mach-smdk2410.c
2 * 2 *
3 * linux/arch/arm/mach-s3c2410/mach-smdk2410.c 3 * linux/arch/arm/mach-s3c2410/mach-smdk2410.c
4 * 4 *
@@ -49,10 +49,10 @@
49 49
50#include <asm/arch/regs-serial.h> 50#include <asm/arch/regs-serial.h>
51 51
52#include "devs.h" 52#include <asm/plat-s3c24xx/devs.h>
53#include "cpu.h" 53#include <asm/plat-s3c24xx/cpu.h>
54 54
55#include "common-smdk.h" 55#include <asm/plat-s3c24xx/common-smdk.h>
56 56
57static struct map_desc smdk2410_iodesc[] __initdata = { 57static struct map_desc smdk2410_iodesc[] __initdata = {
58 /* nothing here yet */ 58 /* nothing here yet */
diff --git a/arch/arm/mach-s3c2410/mach-smdk2413.c b/arch/arm/mach-s3c2410/mach-smdk2413.c
deleted file mode 100644
index 4f89abd7a6df..000000000000
--- a/arch/arm/mach-s3c2410/mach-smdk2413.c
+++ /dev/null
@@ -1,140 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-smdk2413.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Thanks to Dimity Andric (TomTom) and Steven Ryu (Samsung) for the
7 * loans of SMDK2413 to work with.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <asm/hardware.h>
28#include <asm/hardware/iomd.h>
29#include <asm/setup.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/mach-types.h>
33
34//#include <asm/debug-ll.h>
35#include <asm/arch/regs-serial.h>
36#include <asm/arch/regs-gpio.h>
37#include <asm/arch/regs-lcd.h>
38
39#include <asm/arch/idle.h>
40#include <asm/arch/fb.h>
41
42#include "s3c2410.h"
43#include "s3c2412.h"
44#include "clock.h"
45#include "devs.h"
46#include "cpu.h"
47
48#include "common-smdk.h"
49
50static struct map_desc smdk2413_iodesc[] __initdata = {
51};
52
53static struct s3c2410_uartcfg smdk2413_uartcfgs[] __initdata = {
54 [0] = {
55 .hwport = 0,
56 .flags = 0,
57 .ucon = 0x3c5,
58 .ulcon = 0x03,
59 .ufcon = 0x51,
60 },
61 [1] = {
62 .hwport = 1,
63 .flags = 0,
64 .ucon = 0x3c5,
65 .ulcon = 0x03,
66 .ufcon = 0x51,
67 },
68 /* IR port */
69 [2] = {
70 .hwport = 2,
71 .flags = 0,
72 .ucon = 0x3c5,
73 .ulcon = 0x43,
74 .ufcon = 0x51,
75 }
76};
77
78static struct platform_device *smdk2413_devices[] __initdata = {
79 &s3c_device_usb,
80 //&s3c_device_lcd,
81 &s3c_device_wdt,
82 &s3c_device_i2c,
83 &s3c_device_iis,
84};
85
86static struct s3c24xx_board smdk2413_board __initdata = {
87 .devices = smdk2413_devices,
88 .devices_count = ARRAY_SIZE(smdk2413_devices)
89};
90
91static void __init smdk2413_fixup(struct machine_desc *desc,
92 struct tag *tags, char **cmdline,
93 struct meminfo *mi)
94{
95 if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
96 mi->nr_banks=1;
97 mi->bank[0].start = 0x30000000;
98 mi->bank[0].size = SZ_64M;
99 mi->bank[0].node = 0;
100 }
101}
102
103static void __init smdk2413_map_io(void)
104{
105 s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
106 s3c24xx_init_clocks(12000000);
107 s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
108 s3c24xx_set_board(&smdk2413_board);
109}
110
111static void __init smdk2413_machine_init(void)
112{
113 smdk_machine_init();
114}
115
116MACHINE_START(S3C2413, "S3C2413")
117 /* Maintainer: Ben Dooks <ben@fluff.org> */
118 .phys_io = S3C2410_PA_UART,
119 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
120 .boot_params = S3C2410_SDRAM_PA + 0x100,
121
122 .fixup = smdk2413_fixup,
123 .init_irq = s3c24xx_init_irq,
124 .map_io = smdk2413_map_io,
125 .init_machine = smdk2413_machine_init,
126 .timer = &s3c24xx_timer,
127MACHINE_END
128
129MACHINE_START(SMDK2413, "SMDK2413")
130 /* Maintainer: Ben Dooks <ben@fluff.org> */
131 .phys_io = S3C2410_PA_UART,
132 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
133 .boot_params = S3C2410_SDRAM_PA + 0x100,
134
135 .fixup = smdk2413_fixup,
136 .init_irq = s3c24xx_init_irq,
137 .map_io = smdk2413_map_io,
138 .init_machine = smdk2413_machine_init,
139 .timer = &s3c24xx_timer,
140MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-smdk2440.c b/arch/arm/mach-s3c2410/mach-smdk2440.c
deleted file mode 100644
index 2b61f4ed1da4..000000000000
--- a/arch/arm/mach-s3c2410/mach-smdk2440.c
+++ /dev/null
@@ -1,208 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-smdk2440.c
2 *
3 * Copyright (c) 2004,2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.fluff.org/ben/smdk2440/
7 *
8 * Thanks to Dimity Andric and TomTom for the loan of an SMDK2440.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <asm/hardware.h>
30#include <asm/hardware/iomd.h>
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <asm/mach-types.h>
34
35//#include <asm/debug-ll.h>
36#include <asm/arch/regs-serial.h>
37#include <asm/arch/regs-gpio.h>
38#include <asm/arch/regs-lcd.h>
39
40#include <asm/arch/idle.h>
41#include <asm/arch/fb.h>
42
43#include "s3c2410.h"
44#include "s3c2440.h"
45#include "clock.h"
46#include "devs.h"
47#include "cpu.h"
48
49#include "common-smdk.h"
50
51static struct map_desc smdk2440_iodesc[] __initdata = {
52 /* ISA IO Space map (memory space selected by A24) */
53
54 {
55 .virtual = (u32)S3C24XX_VA_ISA_WORD,
56 .pfn = __phys_to_pfn(S3C2410_CS2),
57 .length = 0x10000,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
61 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
62 .length = SZ_4M,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
66 .pfn = __phys_to_pfn(S3C2410_CS2),
67 .length = 0x10000,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
71 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
72 .length = SZ_4M,
73 .type = MT_DEVICE,
74 }
75};
76
77#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
78#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
79#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
80
81static struct s3c2410_uartcfg smdk2440_uartcfgs[] __initdata = {
82 [0] = {
83 .hwport = 0,
84 .flags = 0,
85 .ucon = 0x3c5,
86 .ulcon = 0x03,
87 .ufcon = 0x51,
88 },
89 [1] = {
90 .hwport = 1,
91 .flags = 0,
92 .ucon = 0x3c5,
93 .ulcon = 0x03,
94 .ufcon = 0x51,
95 },
96 /* IR port */
97 [2] = {
98 .hwport = 2,
99 .flags = 0,
100 .ucon = 0x3c5,
101 .ulcon = 0x43,
102 .ufcon = 0x51,
103 }
104};
105
106/* LCD driver info */
107
108static struct s3c2410fb_mach_info smdk2440_lcd_cfg __initdata = {
109 .regs = {
110
111 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
112 S3C2410_LCDCON1_TFT |
113 S3C2410_LCDCON1_CLKVAL(0x04),
114
115 .lcdcon2 = S3C2410_LCDCON2_VBPD(7) |
116 S3C2410_LCDCON2_LINEVAL(319) |
117 S3C2410_LCDCON2_VFPD(6) |
118 S3C2410_LCDCON2_VSPW(3),
119
120 .lcdcon3 = S3C2410_LCDCON3_HBPD(19) |
121 S3C2410_LCDCON3_HOZVAL(239) |
122 S3C2410_LCDCON3_HFPD(7),
123
124 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
125 S3C2410_LCDCON4_HSPW(3),
126
127 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
128 S3C2410_LCDCON5_INVVLINE |
129 S3C2410_LCDCON5_INVVFRAME |
130 S3C2410_LCDCON5_PWREN |
131 S3C2410_LCDCON5_HWSWP,
132 },
133
134#if 0
135 /* currently setup by downloader */
136 .gpccon = 0xaa940659,
137 .gpccon_mask = 0xffffffff,
138 .gpcup = 0x0000ffff,
139 .gpcup_mask = 0xffffffff,
140 .gpdcon = 0xaa84aaa0,
141 .gpdcon_mask = 0xffffffff,
142 .gpdup = 0x0000faff,
143 .gpdup_mask = 0xffffffff,
144#endif
145
146 .lpcsel = ((0xCE6) & ~7) | 1<<4,
147
148 .width = 240,
149 .height = 320,
150
151 .xres = {
152 .min = 240,
153 .max = 240,
154 .defval = 240,
155 },
156
157 .yres = {
158 .min = 320,
159 .max = 320,
160 .defval = 320,
161 },
162
163 .bpp = {
164 .min = 16,
165 .max = 16,
166 .defval = 16,
167 },
168};
169
170static struct platform_device *smdk2440_devices[] __initdata = {
171 &s3c_device_usb,
172 &s3c_device_lcd,
173 &s3c_device_wdt,
174 &s3c_device_i2c,
175 &s3c_device_iis,
176};
177
178static struct s3c24xx_board smdk2440_board __initdata = {
179 .devices = smdk2440_devices,
180 .devices_count = ARRAY_SIZE(smdk2440_devices)
181};
182
183static void __init smdk2440_map_io(void)
184{
185 s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
186 s3c24xx_init_clocks(16934400);
187 s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
188 s3c24xx_set_board(&smdk2440_board);
189}
190
191static void __init smdk2440_machine_init(void)
192{
193 s3c24xx_fb_set_platdata(&smdk2440_lcd_cfg);
194
195 smdk_machine_init();
196}
197
198MACHINE_START(S3C2440, "SMDK2440")
199 /* Maintainer: Ben Dooks <ben@fluff.org> */
200 .phys_io = S3C2410_PA_UART,
201 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
202 .boot_params = S3C2410_SDRAM_PA + 0x100,
203
204 .init_irq = s3c24xx_init_irq,
205 .map_io = smdk2440_map_io,
206 .init_machine = smdk2440_machine_init,
207 .timer = &s3c24xx_timer,
208MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index a382fc095110..c947c75bcbf0 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -43,9 +43,9 @@
43#include <asm/arch/regs-gpio.h> 43#include <asm/arch/regs-gpio.h>
44#include <asm/arch/leds-gpio.h> 44#include <asm/arch/leds-gpio.h>
45 45
46#include "clock.h" 46#include <asm/plat-s3c24xx/clock.h>
47#include "devs.h" 47#include <asm/plat-s3c24xx/devs.h>
48#include "cpu.h" 48#include <asm/plat-s3c24xx/cpu.h>
49#include "usb-simtec.h" 49#include "usb-simtec.h"
50 50
51/* macros for virtual address mods for the io space entries */ 51/* macros for virtual address mods for the io space entries */
diff --git a/arch/arm/mach-s3c2410/mach-vstms.c b/arch/arm/mach-s3c2410/mach-vstms.c
deleted file mode 100644
index 0360e1055bcd..000000000000
--- a/arch/arm/mach-s3c2410/mach-vstms.c
+++ /dev/null
@@ -1,169 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-vstms.c
2 *
3 * (C) 2006 Thomas Gleixner <tglx@linutronix.de>
4 *
5 * Derived from mach-smdk2413.c - (C) 2006 Simtec Electronics
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/nand.h>
23#include <linux/mtd/nand_ecc.h>
24#include <linux/mtd/partitions.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <asm/hardware.h>
31#include <asm/hardware/iomd.h>
32#include <asm/setup.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/mach-types.h>
36
37#include <asm/arch/regs-serial.h>
38#include <asm/arch/regs-gpio.h>
39#include <asm/arch/regs-lcd.h>
40
41#include <asm/arch/idle.h>
42#include <asm/arch/fb.h>
43
44#include <asm/arch/nand.h>
45
46#include "s3c2410.h"
47#include "s3c2412.h"
48#include "clock.h"
49#include "devs.h"
50#include "cpu.h"
51
52
53static struct map_desc vstms_iodesc[] __initdata = {
54};
55
56static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = {
57 [0] = {
58 .hwport = 0,
59 .flags = 0,
60 .ucon = 0x3c5,
61 .ulcon = 0x03,
62 .ufcon = 0x51,
63 },
64 [1] = {
65 .hwport = 1,
66 .flags = 0,
67 .ucon = 0x3c5,
68 .ulcon = 0x03,
69 .ufcon = 0x51,
70 },
71 [2] = {
72 .hwport = 2,
73 .flags = 0,
74 .ucon = 0x3c5,
75 .ulcon = 0x03,
76 .ufcon = 0x51,
77 }
78};
79
80static struct mtd_partition vstms_nand_part[] = {
81 [0] = {
82 .name = "Boot Agent",
83 .size = 0x7C000,
84 .offset = 0,
85 },
86 [1] = {
87 .name = "UBoot Config",
88 .offset = 0x7C000,
89 .size = 0x4000,
90 },
91 [2] = {
92 .name = "Kernel",
93 .offset = 0x80000,
94 .size = 0x200000,
95 },
96 [3] = {
97 .name = "RFS",
98 .offset = 0x280000,
99 .size = 0x3d80000,
100 },
101};
102
103static struct s3c2410_nand_set vstms_nand_sets[] = {
104 [0] = {
105 .name = "NAND",
106 .nr_chips = 1,
107 .nr_partitions = ARRAY_SIZE(vstms_nand_part),
108 .partitions = vstms_nand_part,
109 },
110};
111
112/* choose a set of timings which should suit most 512Mbit
113 * chips and beyond.
114*/
115
116static struct s3c2410_platform_nand vstms_nand_info = {
117 .tacls = 20,
118 .twrph0 = 60,
119 .twrph1 = 20,
120 .nr_sets = ARRAY_SIZE(vstms_nand_sets),
121 .sets = vstms_nand_sets,
122};
123
124static struct platform_device *vstms_devices[] __initdata = {
125 &s3c_device_usb,
126 &s3c_device_wdt,
127 &s3c_device_i2c,
128 &s3c_device_iis,
129 &s3c_device_rtc,
130 &s3c_device_nand,
131};
132
133static struct s3c24xx_board vstms_board __initdata = {
134 .devices = vstms_devices,
135 .devices_count = ARRAY_SIZE(vstms_devices)
136};
137
138static void __init vstms_fixup(struct machine_desc *desc,
139 struct tag *tags, char **cmdline,
140 struct meminfo *mi)
141{
142 if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
143 mi->nr_banks=1;
144 mi->bank[0].start = 0x30000000;
145 mi->bank[0].size = SZ_64M;
146 mi->bank[0].node = 0;
147 }
148}
149
150static void __init vstms_map_io(void)
151{
152 s3c_device_nand.dev.platform_data = &vstms_nand_info;
153
154 s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
155 s3c24xx_init_clocks(12000000);
156 s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
157 s3c24xx_set_board(&vstms_board);
158}
159
160MACHINE_START(VSTMS, "VSTMS")
161 .phys_io = S3C2410_PA_UART,
162 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
163 .boot_params = S3C2410_SDRAM_PA + 0x100,
164
165 .fixup = vstms_fixup,
166 .init_irq = s3c24xx_init_irq,
167 .map_io = vstms_map_io,
168 .timer = &s3c24xx_timer,
169MACHINE_END
diff --git a/arch/arm/mach-s3c2410/pm-simtec.c b/arch/arm/mach-s3c2410/pm-simtec.c
deleted file mode 100644
index 619133eb7168..000000000000
--- a/arch/arm/mach-s3c2410/pm-simtec.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/pm-simtec.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/
7 *
8 * Power Management helpers for Simtec S3C24XX implementations
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25
26#include <asm/hardware.h>
27#include <asm/io.h>
28
29#include <asm/arch/map.h>
30#include <asm/arch/regs-gpio.h>
31#include <asm/arch/regs-mem.h>
32
33#include <asm/mach-types.h>
34
35#include "pm.h"
36
37#define COPYRIGHT ", (c) 2005 Simtec Electronics"
38
39/* pm_simtec_init
40 *
41 * enable the power management functions
42*/
43
44static __init int pm_simtec_init(void)
45{
46 unsigned long gstatus4;
47
48 /* check which machine we are running on */
49
50 if (!machine_is_bast() && !machine_is_vr1000() &&
51 !machine_is_anubis() && !machine_is_osiris() &&
52 !machine_is_aml_m5900())
53 return 0;
54
55 printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n");
56
57 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30;
58 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28;
59 gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK);
60
61 __raw_writel(gstatus4, S3C2410_GSTATUS4);
62
63 return s3c2410_pm_init();
64}
65
66arch_initcall(pm_simtec_init);
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index ebf294dd31da..3b3a7db4e0dd 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -1,11 +1,9 @@
1/* linux/arch/arm/mach-s3c2410/pm.c 1/* linux/arch/arm/mach-s3c2410/pm.c
2 * 2 *
3 * Copyright (c) 2004,2006 Simtec Electronics 3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * S3C24XX Power Manager (Suspend-To-RAM) support 6 * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
7 *
8 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
9 * 7 *
10 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -20,640 +18,139 @@
20 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * Parts based on arch/arm/mach-pxa/pm.c
25 *
26 * Thanks to Dimitry Andric for debugging
27*/ 21*/
28 22
29#include <linux/init.h> 23#include <linux/init.h>
30#include <linux/suspend.h> 24#include <linux/suspend.h>
31#include <linux/errno.h> 25#include <linux/errno.h>
32#include <linux/time.h> 26#include <linux/time.h>
33#include <linux/interrupt.h> 27#include <linux/sysdev.h>
34#include <linux/crc32.h>
35#include <linux/ioport.h>
36#include <linux/delay.h>
37#include <linux/serial_core.h>
38 28
39#include <asm/cacheflush.h>
40#include <asm/hardware.h> 29#include <asm/hardware.h>
41#include <asm/io.h> 30#include <asm/io.h>
42 31
43#include <asm/arch/regs-serial.h> 32#include <asm/mach-types.h>
44#include <asm/arch/regs-clock.h>
45#include <asm/arch/regs-gpio.h>
46#include <asm/arch/regs-mem.h>
47#include <asm/arch/regs-irq.h>
48
49#include <asm/mach/time.h>
50
51#include "pm.h"
52
53/* for external use */
54
55unsigned long s3c_pm_flags;
56
57#define PFX "s3c24xx-pm: "
58
59static struct sleep_save core_save[] = {
60 SAVE_ITEM(S3C2410_LOCKTIME),
61 SAVE_ITEM(S3C2410_CLKCON),
62
63 /* we restore the timings here, with the proviso that the board
64 * brings the system up in an slower, or equal frequency setting
65 * to the original system.
66 *
67 * if we cannot guarantee this, then things are going to go very
68 * wrong here, as we modify the refresh and both pll settings.
69 */
70
71 SAVE_ITEM(S3C2410_BWSCON),
72 SAVE_ITEM(S3C2410_BANKCON0),
73 SAVE_ITEM(S3C2410_BANKCON1),
74 SAVE_ITEM(S3C2410_BANKCON2),
75 SAVE_ITEM(S3C2410_BANKCON3),
76 SAVE_ITEM(S3C2410_BANKCON4),
77 SAVE_ITEM(S3C2410_BANKCON5),
78
79 SAVE_ITEM(S3C2410_CLKDIVN),
80 SAVE_ITEM(S3C2410_MPLLCON),
81 SAVE_ITEM(S3C2410_UPLLCON),
82 SAVE_ITEM(S3C2410_CLKSLOW),
83 SAVE_ITEM(S3C2410_REFRESH),
84};
85
86static struct sleep_save gpio_save[] = {
87 SAVE_ITEM(S3C2410_GPACON),
88 SAVE_ITEM(S3C2410_GPADAT),
89
90 SAVE_ITEM(S3C2410_GPBCON),
91 SAVE_ITEM(S3C2410_GPBDAT),
92 SAVE_ITEM(S3C2410_GPBUP),
93
94 SAVE_ITEM(S3C2410_GPCCON),
95 SAVE_ITEM(S3C2410_GPCDAT),
96 SAVE_ITEM(S3C2410_GPCUP),
97
98 SAVE_ITEM(S3C2410_GPDCON),
99 SAVE_ITEM(S3C2410_GPDDAT),
100 SAVE_ITEM(S3C2410_GPDUP),
101
102 SAVE_ITEM(S3C2410_GPECON),
103 SAVE_ITEM(S3C2410_GPEDAT),
104 SAVE_ITEM(S3C2410_GPEUP),
105
106 SAVE_ITEM(S3C2410_GPFCON),
107 SAVE_ITEM(S3C2410_GPFDAT),
108 SAVE_ITEM(S3C2410_GPFUP),
109 33
110 SAVE_ITEM(S3C2410_GPGCON), 34#include <asm/arch/regs-gpio.h>
111 SAVE_ITEM(S3C2410_GPGDAT), 35#include <asm/arch/h1940.h>
112 SAVE_ITEM(S3C2410_GPGUP),
113
114 SAVE_ITEM(S3C2410_GPHCON),
115 SAVE_ITEM(S3C2410_GPHDAT),
116 SAVE_ITEM(S3C2410_GPHUP),
117 36
118 SAVE_ITEM(S3C2410_DCLKCON), 37#include <asm/plat-s3c24xx/cpu.h>
119}; 38#include <asm/plat-s3c24xx/pm.h>
120 39
121#ifdef CONFIG_S3C2410_PM_DEBUG 40#ifdef CONFIG_S3C2410_PM_DEBUG
122 41extern void pm_dbg(const char *fmt, ...);
123#define SAVE_UART(va) \
124 SAVE_ITEM((va) + S3C2410_ULCON), \
125 SAVE_ITEM((va) + S3C2410_UCON), \
126 SAVE_ITEM((va) + S3C2410_UFCON), \
127 SAVE_ITEM((va) + S3C2410_UMCON), \
128 SAVE_ITEM((va) + S3C2410_UBRDIV)
129
130static struct sleep_save uart_save[] = {
131 SAVE_UART(S3C24XX_VA_UART0),
132 SAVE_UART(S3C24XX_VA_UART1),
133#ifndef CONFIG_CPU_S3C2400
134 SAVE_UART(S3C24XX_VA_UART2),
135#endif
136};
137
138/* debug
139 *
140 * we send the debug to printascii() to allow it to be seen if the
141 * system never wakes up from the sleep
142*/
143
144extern void printascii(const char *);
145
146void pm_dbg(const char *fmt, ...)
147{
148 va_list va;
149 char buff[256];
150
151 va_start(va, fmt);
152 vsprintf(buff, fmt, va);
153 va_end(va);
154
155 printascii(buff);
156}
157
158static void s3c2410_pm_debug_init(void)
159{
160 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
161
162 /* re-start uart clocks */
163 tmp |= S3C2410_CLKCON_UART0;
164 tmp |= S3C2410_CLKCON_UART1;
165 tmp |= S3C2410_CLKCON_UART2;
166
167 __raw_writel(tmp, S3C2410_CLKCON);
168 udelay(10);
169}
170
171#define DBG(fmt...) pm_dbg(fmt) 42#define DBG(fmt...) pm_dbg(fmt)
172#else 43#else
173#define DBG(fmt...) printk(KERN_DEBUG fmt) 44#define DBG(fmt...) printk(KERN_DEBUG fmt)
174
175#define s3c2410_pm_debug_init() do { } while(0)
176
177static struct sleep_save uart_save[] = {};
178#endif 45#endif
179 46
180#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0 47static void s3c2410_pm_prepare(void)
181
182/* suspend checking code...
183 *
184 * this next area does a set of crc checks over all the installed
185 * memory, so the system can verify if the resume was ok.
186 *
187 * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
188 * increasing it will mean that the area corrupted will be less easy to spot,
189 * and reducing the size will cause the CRC save area to grow
190*/
191
192#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
193
194static u32 crc_size; /* size needed for the crc block */
195static u32 *crcs; /* allocated over suspend/resume */
196
197typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
198
199/* s3c2410_pm_run_res
200 *
201 * go thorugh the given resource list, and look for system ram
202*/
203
204static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
205{
206 while (ptr != NULL) {
207 if (ptr->child != NULL)
208 s3c2410_pm_run_res(ptr->child, fn, arg);
209
210 if ((ptr->flags & IORESOURCE_MEM) &&
211 strcmp(ptr->name, "System RAM") == 0) {
212 DBG("Found system RAM at %08lx..%08lx\n",
213 ptr->start, ptr->end);
214 arg = (fn)(ptr, arg);
215 }
216
217 ptr = ptr->sibling;
218 }
219}
220
221static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
222{
223 s3c2410_pm_run_res(&iomem_resource, fn, arg);
224}
225
226static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
227{
228 u32 size = (u32)(res->end - res->start)+1;
229
230 size += CHECK_CHUNKSIZE-1;
231 size /= CHECK_CHUNKSIZE;
232
233 DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
234
235 *val += size * sizeof(u32);
236 return val;
237}
238
239/* s3c2410_pm_prepare_check
240 *
241 * prepare the necessary information for creating the CRCs. This
242 * must be done before the final save, as it will require memory
243 * allocating, and thus touching bits of the kernel we do not
244 * know about.
245*/
246
247static void s3c2410_pm_check_prepare(void)
248{ 48{
249 crc_size = 0; 49 /* ensure at least GSTATUS3 has the resume address */
250 50
251 s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size); 51 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
252 52
253 DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size); 53 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
54 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
254 55
255 crcs = kmalloc(crc_size+4, GFP_KERNEL); 56 if (machine_is_h1940()) {
256 if (crcs == NULL) 57 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
257 printk(KERN_ERR "Cannot allocated CRC save area\n"); 58 unsigned long ptr;
258} 59 unsigned long calc = 0;
259 60
260static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val) 61 /* generate check for the bootloader to check on resume */
261{
262 unsigned long addr, left;
263 62
264 for (addr = res->start; addr < res->end; 63 for (ptr = 0; ptr < 0x40000; ptr += 0x400)
265 addr += CHECK_CHUNKSIZE) { 64 calc += __raw_readl(base+ptr);
266 left = res->end - addr;
267 65
268 if (left > CHECK_CHUNKSIZE) 66 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
269 left = CHECK_CHUNKSIZE;
270
271 *val = crc32_le(~0, phys_to_virt(addr), left);
272 val++;
273 } 67 }
274 68
275 return val; 69 /* the RX3715 uses similar code and the same H1940 and the
276} 70 * same offsets for resume and checksum pointers */
277
278/* s3c2410_pm_check_store
279 *
280 * compute the CRC values for the memory blocks before the final
281 * sleep.
282*/
283
284static void s3c2410_pm_check_store(void)
285{
286 if (crcs != NULL)
287 s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
288}
289
290/* in_region
291 *
292 * return TRUE if the area defined by ptr..ptr+size contatins the
293 * what..what+whatsz
294*/
295
296static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
297{
298 if ((what+whatsz) < ptr)
299 return 0;
300
301 if (what > (ptr+size))
302 return 0;
303
304 return 1;
305}
306
307static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
308{
309 void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
310 unsigned long addr;
311 unsigned long left;
312 void *ptr;
313 u32 calc;
314
315 for (addr = res->start; addr < res->end;
316 addr += CHECK_CHUNKSIZE) {
317 left = res->end - addr;
318 71
319 if (left > CHECK_CHUNKSIZE) 72 if (machine_is_rx3715()) {
320 left = CHECK_CHUNKSIZE; 73 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
74 unsigned long ptr;
75 unsigned long calc = 0;
321 76
322 ptr = phys_to_virt(addr); 77 /* generate check for the bootloader to check on resume */
323 78
324 if (in_region(ptr, left, crcs, crc_size)) { 79 for (ptr = 0; ptr < 0x40000; ptr += 0x4)
325 DBG("skipping %08lx, has crc block in\n", addr); 80 calc += __raw_readl(base+ptr);
326 goto skip_check;
327 }
328 81
329 if (in_region(ptr, left, save_at, 32*4 )) { 82 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
330 DBG("skipping %08lx, has save block in\n", addr);
331 goto skip_check;
332 }
333
334 /* calculate and check the checksum */
335
336 calc = crc32_le(~0, ptr, left);
337 if (calc != *val) {
338 printk(KERN_ERR PFX "Restore CRC error at "
339 "%08lx (%08x vs %08x)\n", addr, calc, *val);
340
341 DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
342 addr, calc, *val);
343 }
344
345 skip_check:
346 val++;
347 } 83 }
348 84
349 return val; 85 if ( machine_is_aml_m5900() )
350} 86 s3c2410_gpio_setpin(S3C2410_GPF2, 1);
351 87
352/* s3c2410_pm_check_restore
353 *
354 * check the CRCs after the restore event and free the memory used
355 * to hold them
356*/
357
358static void s3c2410_pm_check_restore(void)
359{
360 if (crcs != NULL) {
361 s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
362 kfree(crcs);
363 crcs = NULL;
364 }
365} 88}
366 89
367#else 90static int s3c2410_pm_resume(struct sys_device *dev)
368
369#define s3c2410_pm_check_prepare() do { } while(0)
370#define s3c2410_pm_check_restore() do { } while(0)
371#define s3c2410_pm_check_store() do { } while(0)
372#endif
373
374/* helper functions to save and restore register state */
375
376void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
377{ 91{
378 for (; count > 0; count--, ptr++) { 92 unsigned long tmp;
379 ptr->val = __raw_readl(ptr->reg);
380 DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
381 }
382}
383 93
384/* s3c2410_pm_do_restore 94 /* unset the return-from-sleep flag, to ensure reset */
385 *
386 * restore the system from the given list of saved registers
387 *
388 * Note, we do not use DBG() in here, as the system may not have
389 * restore the UARTs state yet
390*/
391 95
392void s3c2410_pm_do_restore(struct sleep_save *ptr, int count) 96 tmp = __raw_readl(S3C2410_GSTATUS2);
393{ 97 tmp &= S3C2410_GSTATUS2_OFFRESET;
394 for (; count > 0; count--, ptr++) { 98 __raw_writel(tmp, S3C2410_GSTATUS2);
395 printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
396 ptr->reg, ptr->val, __raw_readl(ptr->reg));
397
398 __raw_writel(ptr->val, ptr->reg);
399 }
400}
401 99
402/* s3c2410_pm_do_restore_core 100 if ( machine_is_aml_m5900() )
403 * 101 s3c2410_gpio_setpin(S3C2410_GPF2, 0);
404 * similar to s3c2410_pm_do_restore_core
405 *
406 * WARNING: Do not put any debug in here that may effect memory or use
407 * peripherals, as things may be changing!
408*/
409 102
410static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count) 103 return 0;
411{
412 for (; count > 0; count--, ptr++) {
413 __raw_writel(ptr->val, ptr->reg);
414 }
415} 104}
416 105
417/* s3c2410_pm_show_resume_irqs 106static int s3c2410_pm_add(struct sys_device *dev)
418 *
419 * print any IRQs asserted at resume time (ie, we woke from)
420*/
421
422static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
423 unsigned long mask)
424{ 107{
425 int i; 108 pm_cpu_prep = s3c2410_pm_prepare;
109 pm_cpu_sleep = s3c2410_cpu_suspend;
426 110
427 which &= ~mask; 111 return 0;
428
429 for (i = 0; i <= 31; i++) {
430 if ((which) & (1L<<i)) {
431 DBG("IRQ %d asserted at resume\n", start+i);
432 }
433 }
434} 112}
435 113
436/* s3c2410_pm_check_resume_pin 114#if defined(CONFIG_CPU_S3C2410)
437 * 115static struct sysdev_driver s3c2410_pm_driver = {
438 * check to see if the pin is configured correctly for sleep mode, and 116 .add = s3c2410_pm_add,
439 * make any necessary adjustments if it is not 117 .resume = s3c2410_pm_resume,
440*/ 118};
441
442static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
443{
444 unsigned long irqstate;
445 unsigned long pinstate;
446 int irq = s3c2410_gpio_getirq(pin);
447
448 if (irqoffs < 4)
449 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
450 else
451 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
452
453 pinstate = s3c2410_gpio_getcfg(pin);
454
455 if (!irqstate) {
456 if (pinstate == S3C2410_GPIO_IRQ)
457 DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
458 } else {
459 if (pinstate == S3C2410_GPIO_IRQ) {
460 DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
461 s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
462 }
463 }
464}
465 119
466/* s3c2410_pm_configure_extint 120/* register ourselves */
467 *
468 * configure all external interrupt pins
469*/
470 121
471static void s3c2410_pm_configure_extint(void) 122static int __init s3c2410_pm_drvinit(void)
472{ 123{
473 int pin; 124 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_pm_driver);
474
475 /* for each of the external interrupts (EINT0..EINT15) we
476 * need to check wether it is an external interrupt source,
477 * and then configure it as an input if it is not
478 */
479
480 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
481 s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
482 }
483
484 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
485 s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
486 }
487} 125}
488 126
489void (*pm_cpu_prep)(void); 127arch_initcall(s3c2410_pm_drvinit);
490void (*pm_cpu_sleep)(void); 128#endif
491
492#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
493
494/* s3c2410_pm_enter
495 *
496 * central control for sleep/resume process
497*/
498
499static int s3c2410_pm_enter(suspend_state_t state)
500{
501 unsigned long regs_save[16];
502
503 /* ensure the debug is initialised (if enabled) */
504
505 s3c2410_pm_debug_init();
506
507 DBG("s3c2410_pm_enter(%d)\n", state);
508
509 if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
510 printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
511 return -EINVAL;
512 }
513
514 if (state != PM_SUSPEND_MEM) {
515 printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
516 return -EINVAL;
517 }
518
519 /* check if we have anything to wake-up with... bad things seem
520 * to happen if you suspend with no wakeup (system will often
521 * require a full power-cycle)
522 */
523
524 if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
525 !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
526 printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
527 printk(KERN_ERR PFX "Aborting sleep\n");
528 return -EINVAL;
529 }
530
531 /* prepare check area if configured */
532
533 s3c2410_pm_check_prepare();
534
535 /* store the physical address of the register recovery block */
536
537 s3c2410_sleep_save_phys = virt_to_phys(regs_save);
538
539 DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
540
541 /* save all necessary core registers not covered by the drivers */
542
543 s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
544 s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
545 s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
546
547 /* set the irq configuration for wake */
548
549 s3c2410_pm_configure_extint();
550
551 DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
552 s3c_irqwake_intmask, s3c_irqwake_eintmask);
553
554 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
555 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
556
557 /* ack any outstanding external interrupts before we go to sleep */
558
559 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
560 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
561 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
562
563 /* call cpu specific preperation */
564
565 pm_cpu_prep();
566
567 /* flush cache back to ram */
568
569 flush_cache_all();
570
571 s3c2410_pm_check_store();
572
573 /* send the cpu to sleep... */
574
575 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
576
577 /* s3c2410_cpu_save will also act as our return point from when
578 * we resume as it saves its own register state, so use the return
579 * code to differentiate return from save and return from sleep */
580
581 if (s3c2410_cpu_save(regs_save) == 0) {
582 flush_cache_all();
583 pm_cpu_sleep();
584 }
585
586 /* restore the cpu state */
587
588 cpu_init();
589
590 /* restore the system state */
591
592 s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
593 s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
594 s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
595
596 s3c2410_pm_debug_init();
597
598 /* check what irq (if any) restored the system */
599
600 DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
601 __raw_readl(S3C2410_SRCPND),
602 __raw_readl(S3C2410_EINTPEND));
603
604 s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
605 s3c_irqwake_intmask);
606
607 s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
608 s3c_irqwake_eintmask);
609
610 DBG("post sleep, preparing to return\n");
611
612 s3c2410_pm_check_restore();
613
614 /* ok, let's return from sleep */
615 129
616 DBG("S3C2410 PM Resume (post-restore)\n"); 130#if defined(CONFIG_CPU_S3C2440)
617 return 0; 131static struct sysdev_driver s3c2440_pm_driver = {
618} 132 .add = s3c2410_pm_add,
133 .resume = s3c2410_pm_resume,
134};
619 135
620/* 136static int __init s3c2440_pm_drvinit(void)
621 * Called after processes are frozen, but before we shut down devices.
622 */
623static int s3c2410_pm_prepare(suspend_state_t state)
624{ 137{
625 return 0; 138 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_pm_driver);
626} 139}
627 140
628/* 141arch_initcall(s3c2440_pm_drvinit);
629 * Called after devices are re-setup, but before processes are thawed. 142#endif
630 */
631static int s3c2410_pm_finish(suspend_state_t state)
632{
633 return 0;
634}
635 143
636/* 144#if defined(CONFIG_CPU_S3C2442)
637 * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk. 145static struct sysdev_driver s3c2442_pm_driver = {
638 */ 146 .add = s3c2410_pm_add,
639static struct pm_ops s3c2410_pm_ops = { 147 .resume = s3c2410_pm_resume,
640 .pm_disk_mode = PM_DISK_FIRMWARE,
641 .prepare = s3c2410_pm_prepare,
642 .enter = s3c2410_pm_enter,
643 .finish = s3c2410_pm_finish,
644}; 148};
645 149
646/* s3c2410_pm_init 150static int __init s3c2442_pm_drvinit(void)
647 *
648 * Attach the power management functions. This should be called
649 * from the board specific initialisation if the board supports
650 * it.
651*/
652
653int __init s3c2410_pm_init(void)
654{ 151{
655 printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n"); 152 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_pm_driver);
656
657 pm_set_ops(&s3c2410_pm_ops);
658 return 0;
659} 153}
154
155arch_initcall(s3c2442_pm_drvinit);
156#endif
diff --git a/arch/arm/mach-s3c2410/pm.h b/arch/arm/mach-s3c2410/pm.h
deleted file mode 100644
index ffe197a119fb..000000000000
--- a/arch/arm/mach-s3c2410/pm.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/pm.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Written by Ben Dooks, <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* s3c2410_pm_init
12 *
13 * called from board at initialisation time to setup the power
14 * management
15*/
16
17#ifdef CONFIG_PM
18
19extern __init int s3c2410_pm_init(void);
20
21#else
22
23static inline int s3c2410_pm_init(void)
24{
25 return 0;
26}
27#endif
28
29/* configuration for the IRQ mask over sleep */
30extern unsigned long s3c_irqwake_intmask;
31extern unsigned long s3c_irqwake_eintmask;
32
33/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
34extern unsigned long s3c_irqwake_intallow;
35extern unsigned long s3c_irqwake_eintallow;
36
37/* per-cpu sleep functions */
38
39extern void (*pm_cpu_prep)(void);
40extern void (*pm_cpu_sleep)(void);
41
42/* Flags for PM Control */
43
44extern unsigned long s3c_pm_flags;
45
46/* from sleep.S */
47
48extern int s3c2410_cpu_save(unsigned long *saveblk);
49extern void s3c2410_cpu_suspend(void);
50extern void s3c2410_cpu_resume(void);
51
52extern unsigned long s3c2410_sleep_save_phys;
53
54/* sleep save info */
55
56struct sleep_save {
57 void __iomem *reg;
58 unsigned long val;
59};
60
61#define SAVE_ITEM(x) \
62 { .reg = (x) }
63
64extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
65extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
66
67#ifdef CONFIG_PM
68extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
69extern int s3c24xx_irq_resume(struct sys_device *dev);
70#else
71#define s3c24xx_irq_suspend NULL
72#define s3c24xx_irq_resume NULL
73#endif
diff --git a/arch/arm/mach-s3c2410/s3c2400-gpio.c b/arch/arm/mach-s3c2410/s3c2400-gpio.c
deleted file mode 100644
index 1576d01d5f82..000000000000
--- a/arch/arm/mach-s3c2410/s3c2400-gpio.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2400-gpio.c
2 *
3 * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
4 *
5 * S3C2400 GPIO support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20*/
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/interrupt.h>
26#include <linux/ioport.h>
27
28#include <asm/hardware.h>
29#include <asm/irq.h>
30#include <asm/io.h>
31
32#include <asm/arch/regs-gpio.h>
33
34int s3c2400_gpio_getirq(unsigned int pin)
35{
36 if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7)
37 return -1; /* not valid interrupts */
38
39 return (pin - S3C2410_GPE0) + IRQ_EINT0;
40}
41
42EXPORT_SYMBOL(s3c2400_gpio_getirq);
diff --git a/arch/arm/mach-s3c2410/s3c2400.h b/arch/arm/mach-s3c2410/s3c2400.h
deleted file mode 100644
index 8b2394e1ed40..000000000000
--- a/arch/arm/mach-s3c2410/s3c2400.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/* arch/arm/mach-s3c2410/s3c2400.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C2400 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13 * 09-Fev-2006 LCVR First version, based on s3c2410.h
14*/
15
16#ifdef CONFIG_CPU_S3C2400
17
18extern int s3c2400_init(void);
19
20extern void s3c2400_map_io(struct map_desc *mach_desc, int size);
21
22extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
23
24extern void s3c2400_init_clocks(int xtal);
25
26#else
27#define s3c2400_init_clocks NULL
28#define s3c2400_init_uarts NULL
29#define s3c2400_map_io NULL
30#define s3c2400_init NULL
31#endif
diff --git a/arch/arm/mach-s3c2410/s3c2410-clock.c b/arch/arm/mach-s3c2410/s3c2410-clock.c
deleted file mode 100644
index 992cc6af230e..000000000000
--- a/arch/arm/mach-s3c2410/s3c2410-clock.c
+++ /dev/null
@@ -1,276 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410-clock.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410,S3C2440,S3C2442 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/list.h>
27#include <linux/errno.h>
28#include <linux/err.h>
29#include <linux/sysdev.h>
30#include <linux/clk.h>
31#include <linux/mutex.h>
32#include <linux/delay.h>
33#include <linux/serial_core.h>
34
35#include <asm/mach/map.h>
36
37#include <asm/hardware.h>
38#include <asm/io.h>
39
40#include <asm/arch/regs-serial.h>
41#include <asm/arch/regs-clock.h>
42#include <asm/arch/regs-gpio.h>
43
44#include "s3c2410.h"
45#include "clock.h"
46#include "cpu.h"
47
48int s3c2410_clkcon_enable(struct clk *clk, int enable)
49{
50 unsigned int clocks = clk->ctrlbit;
51 unsigned long clkcon;
52
53 clkcon = __raw_readl(S3C2410_CLKCON);
54
55 if (enable)
56 clkcon |= clocks;
57 else
58 clkcon &= ~clocks;
59
60 /* ensure none of the special function bits set */
61 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
62
63 __raw_writel(clkcon, S3C2410_CLKCON);
64
65 return 0;
66}
67
68static int s3c2410_upll_enable(struct clk *clk, int enable)
69{
70 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
71 unsigned long orig = clkslow;
72
73 if (enable)
74 clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
75 else
76 clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
77
78 __raw_writel(clkslow, S3C2410_CLKSLOW);
79
80 /* if we started the UPLL, then allow to settle */
81
82 if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
83 udelay(200);
84
85 return 0;
86}
87
88/* standard clock definitions */
89
90static struct clk init_clocks_disable[] = {
91 {
92 .name = "nand",
93 .id = -1,
94 .parent = &clk_h,
95 .enable = s3c2410_clkcon_enable,
96 .ctrlbit = S3C2410_CLKCON_NAND,
97 }, {
98 .name = "sdi",
99 .id = -1,
100 .parent = &clk_p,
101 .enable = s3c2410_clkcon_enable,
102 .ctrlbit = S3C2410_CLKCON_SDI,
103 }, {
104 .name = "adc",
105 .id = -1,
106 .parent = &clk_p,
107 .enable = s3c2410_clkcon_enable,
108 .ctrlbit = S3C2410_CLKCON_ADC,
109 }, {
110 .name = "i2c",
111 .id = -1,
112 .parent = &clk_p,
113 .enable = s3c2410_clkcon_enable,
114 .ctrlbit = S3C2410_CLKCON_IIC,
115 }, {
116 .name = "iis",
117 .id = -1,
118 .parent = &clk_p,
119 .enable = s3c2410_clkcon_enable,
120 .ctrlbit = S3C2410_CLKCON_IIS,
121 }, {
122 .name = "spi",
123 .id = -1,
124 .parent = &clk_p,
125 .enable = s3c2410_clkcon_enable,
126 .ctrlbit = S3C2410_CLKCON_SPI,
127 }
128};
129
130static struct clk init_clocks[] = {
131 {
132 .name = "lcd",
133 .id = -1,
134 .parent = &clk_h,
135 .enable = s3c2410_clkcon_enable,
136 .ctrlbit = S3C2410_CLKCON_LCDC,
137 }, {
138 .name = "gpio",
139 .id = -1,
140 .parent = &clk_p,
141 .enable = s3c2410_clkcon_enable,
142 .ctrlbit = S3C2410_CLKCON_GPIO,
143 }, {
144 .name = "usb-host",
145 .id = -1,
146 .parent = &clk_h,
147 .enable = s3c2410_clkcon_enable,
148 .ctrlbit = S3C2410_CLKCON_USBH,
149 }, {
150 .name = "usb-device",
151 .id = -1,
152 .parent = &clk_h,
153 .enable = s3c2410_clkcon_enable,
154 .ctrlbit = S3C2410_CLKCON_USBD,
155 }, {
156 .name = "timers",
157 .id = -1,
158 .parent = &clk_p,
159 .enable = s3c2410_clkcon_enable,
160 .ctrlbit = S3C2410_CLKCON_PWMT,
161 }, {
162 .name = "uart",
163 .id = 0,
164 .parent = &clk_p,
165 .enable = s3c2410_clkcon_enable,
166 .ctrlbit = S3C2410_CLKCON_UART0,
167 }, {
168 .name = "uart",
169 .id = 1,
170 .parent = &clk_p,
171 .enable = s3c2410_clkcon_enable,
172 .ctrlbit = S3C2410_CLKCON_UART1,
173 }, {
174 .name = "uart",
175 .id = 2,
176 .parent = &clk_p,
177 .enable = s3c2410_clkcon_enable,
178 .ctrlbit = S3C2410_CLKCON_UART2,
179 }, {
180 .name = "rtc",
181 .id = -1,
182 .parent = &clk_p,
183 .enable = s3c2410_clkcon_enable,
184 .ctrlbit = S3C2410_CLKCON_RTC,
185 }, {
186 .name = "watchdog",
187 .id = -1,
188 .parent = &clk_p,
189 .ctrlbit = 0,
190 }, {
191 .name = "usb-bus-host",
192 .id = -1,
193 .parent = &clk_usb_bus,
194 }, {
195 .name = "usb-bus-gadget",
196 .id = -1,
197 .parent = &clk_usb_bus,
198 },
199};
200
201/* s3c2410_baseclk_add()
202 *
203 * Add all the clocks used by the s3c2410 or compatible CPUs
204 * such as the S3C2440 and S3C2442.
205 *
206 * We cannot use a system device as we are needed before any
207 * of the init-calls that initialise the devices are actually
208 * done.
209*/
210
211int __init s3c2410_baseclk_add(void)
212{
213 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
214 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
215 struct clk *clkp;
216 struct clk *xtal;
217 int ret;
218 int ptr;
219
220 clk_upll.enable = s3c2410_upll_enable;
221
222 if (s3c24xx_register_clock(&clk_usb_bus) < 0)
223 printk(KERN_ERR "failed to register usb bus clock\n");
224
225 /* register clocks from clock array */
226
227 clkp = init_clocks;
228 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
229 /* ensure that we note the clock state */
230
231 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
232
233 ret = s3c24xx_register_clock(clkp);
234 if (ret < 0) {
235 printk(KERN_ERR "Failed to register clock %s (%d)\n",
236 clkp->name, ret);
237 }
238 }
239
240 /* We must be careful disabling the clocks we are not intending to
241 * be using at boot time, as subsytems such as the LCD which do
242 * their own DMA requests to the bus can cause the system to lockup
243 * if they where in the middle of requesting bus access.
244 *
245 * Disabling the LCD clock if the LCD is active is very dangerous,
246 * and therefore the bootloader should be careful to not enable
247 * the LCD clock if it is not needed.
248 */
249
250 /* install (and disable) the clocks we do not need immediately */
251
252 clkp = init_clocks_disable;
253 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
254
255 ret = s3c24xx_register_clock(clkp);
256 if (ret < 0) {
257 printk(KERN_ERR "Failed to register clock %s (%d)\n",
258 clkp->name, ret);
259 }
260
261 s3c2410_clkcon_enable(clkp, 0);
262 }
263
264 /* show the clock-slow value */
265
266 xtal = clk_get(NULL, "xtal");
267
268 printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
269 print_mhz(clk_get_rate(xtal) /
270 ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
271 (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
272 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
273 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
274
275 return 0;
276}
diff --git a/arch/arm/mach-s3c2410/s3c2410-dma.c b/arch/arm/mach-s3c2410/s3c2410-dma.c
deleted file mode 100644
index e67ba3911f11..000000000000
--- a/arch/arm/mach-s3c2410/s3c2410-dma.c
+++ /dev/null
@@ -1,161 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410-dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18#include <linux/serial_core.h>
19
20#include <asm/dma.h>
21#include <asm/arch/dma.h>
22#include "dma.h"
23
24#include "cpu.h"
25
26#include <asm/arch/regs-serial.h>
27#include <asm/arch/regs-gpio.h>
28#include <asm/arch/regs-ac97.h>
29#include <asm/arch/regs-mem.h>
30#include <asm/arch/regs-lcd.h>
31#include <asm/arch/regs-sdi.h>
32#include <asm/arch/regs-iis.h>
33#include <asm/arch/regs-spi.h>
34
35static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
36 [DMACH_XD0] = {
37 .name = "xdreq0",
38 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
39 },
40 [DMACH_XD1] = {
41 .name = "xdreq1",
42 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
43 },
44 [DMACH_SDI] = {
45 .name = "sdi",
46 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
47 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
48 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
49 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
50 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
51 },
52 [DMACH_SPI0] = {
53 .name = "spi0",
54 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
55 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
56 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
57 },
58 [DMACH_SPI1] = {
59 .name = "spi1",
60 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
61 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
62 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
63 },
64 [DMACH_UART0] = {
65 .name = "uart0",
66 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
67 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
68 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
69 },
70 [DMACH_UART1] = {
71 .name = "uart1",
72 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
73 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
74 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
75 },
76 [DMACH_UART2] = {
77 .name = "uart2",
78 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
79 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
80 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
81 },
82 [DMACH_TIMER] = {
83 .name = "timer",
84 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
85 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
86 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
87 },
88 [DMACH_I2S_IN] = {
89 .name = "i2s-sdi",
90 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
91 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
92 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
93 },
94 [DMACH_I2S_OUT] = {
95 .name = "i2s-sdo",
96 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
97 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
98 },
99 [DMACH_USB_EP1] = {
100 .name = "usb-ep1",
101 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
102 },
103 [DMACH_USB_EP2] = {
104 .name = "usb-ep2",
105 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
106 },
107 [DMACH_USB_EP3] = {
108 .name = "usb-ep3",
109 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
110 },
111 [DMACH_USB_EP4] = {
112 .name = "usb-ep4",
113 .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
114 },
115};
116
117static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
118 struct s3c24xx_dma_map *map)
119{
120 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
121}
122
123static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
124 .select = s3c2410_dma_select,
125 .dcon_mask = 7 << 24,
126 .map = s3c2410_dma_mappings,
127 .map_size = ARRAY_SIZE(s3c2410_dma_mappings),
128};
129
130static int s3c2410_dma_add(struct sys_device *sysdev)
131{
132 return s3c24xx_dma_init_map(&s3c2410_dma_sel);
133}
134
135#if defined(CONFIG_CPU_S3C2410)
136static struct sysdev_driver s3c2410_dma_driver = {
137 .add = s3c2410_dma_add,
138};
139
140static int __init s3c2410_dma_init(void)
141{
142 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
143}
144
145arch_initcall(s3c2410_dma_init);
146#endif
147
148#if defined(CONFIG_CPU_S3C2442)
149/* S3C2442 DMA contains the same selection table as the S3C2410 */
150static struct sysdev_driver s3c2442_dma_driver = {
151 .add = s3c2410_dma_add,
152};
153
154static int __init s3c2442_dma_init(void)
155{
156 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
157}
158
159arch_initcall(s3c2442_dma_init);
160#endif
161
diff --git a/arch/arm/mach-s3c2410/s3c2410-gpio.c b/arch/arm/mach-s3c2410/s3c2410-gpio.c
deleted file mode 100644
index ec3a276cc3cf..000000000000
--- a/arch/arm/mach-s3c2410/s3c2410-gpio.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410-gpio.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 GPIO support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/interrupt.h>
27#include <linux/ioport.h>
28
29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/io.h>
32
33#include <asm/arch/regs-gpio.h>
34
35int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
36 unsigned int config)
37{
38 void __iomem *reg = S3C24XX_EINFLT0;
39 unsigned long flags;
40 unsigned long val;
41
42 if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
43 return -1;
44
45 config &= 0xff;
46
47 pin -= S3C2410_GPG8;
48 reg += pin & ~3;
49
50 local_irq_save(flags);
51
52 /* update filter width and clock source */
53
54 val = __raw_readl(reg);
55 val &= ~(0xff << ((pin & 3) * 8));
56 val |= config << ((pin & 3) * 8);
57 __raw_writel(val, reg);
58
59 /* update filter enable */
60
61 val = __raw_readl(S3C24XX_EXTINT2);
62 val &= ~(1 << ((pin * 4) + 3));
63 val |= on << ((pin * 4) + 3);
64 __raw_writel(val, S3C24XX_EXTINT2);
65
66 local_irq_restore(flags);
67
68 return 0;
69}
70
71EXPORT_SYMBOL(s3c2410_gpio_irqfilter);
diff --git a/arch/arm/mach-s3c2410/s3c2410-irq.c b/arch/arm/mach-s3c2410/s3c2410-irq.c
deleted file mode 100644
index c796c9c76e78..000000000000
--- a/arch/arm/mach-s3c2410/s3c2410-irq.c
+++ /dev/null
@@ -1,48 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410-irq.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/ptrace.h>
27#include <linux/sysdev.h>
28
29#include "cpu.h"
30#include "pm.h"
31
32static int s3c2410_irq_add(struct sys_device *sysdev)
33{
34 return 0;
35}
36
37static struct sysdev_driver s3c2410_irq_driver = {
38 .add = s3c2410_irq_add,
39 .suspend = s3c24xx_irq_suspend,
40 .resume = s3c24xx_irq_resume,
41};
42
43static int s3c2410_irq_init(void)
44{
45 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver);
46}
47
48arch_initcall(s3c2410_irq_init);
diff --git a/arch/arm/mach-s3c2410/s3c2410-pm.c b/arch/arm/mach-s3c2410/s3c2410-pm.c
deleted file mode 100644
index 8bb6e5e21f59..000000000000
--- a/arch/arm/mach-s3c2410/s3c2410-pm.c
+++ /dev/null
@@ -1,156 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410-pm.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24#include <linux/suspend.h>
25#include <linux/errno.h>
26#include <linux/time.h>
27#include <linux/sysdev.h>
28
29#include <asm/hardware.h>
30#include <asm/io.h>
31
32#include <asm/mach-types.h>
33
34#include <asm/arch/regs-gpio.h>
35#include <asm/arch/h1940.h>
36
37#include "cpu.h"
38#include "pm.h"
39
40#ifdef CONFIG_S3C2410_PM_DEBUG
41extern void pm_dbg(const char *fmt, ...);
42#define DBG(fmt...) pm_dbg(fmt)
43#else
44#define DBG(fmt...) printk(KERN_DEBUG fmt)
45#endif
46
47static void s3c2410_pm_prepare(void)
48{
49 /* ensure at least GSTATUS3 has the resume address */
50
51 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
52
53 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
54 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
55
56 if (machine_is_h1940()) {
57 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
58 unsigned long ptr;
59 unsigned long calc = 0;
60
61 /* generate check for the bootloader to check on resume */
62
63 for (ptr = 0; ptr < 0x40000; ptr += 0x400)
64 calc += __raw_readl(base+ptr);
65
66 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
67 }
68
69 /* the RX3715 uses similar code and the same H1940 and the
70 * same offsets for resume and checksum pointers */
71
72 if (machine_is_rx3715()) {
73 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
74 unsigned long ptr;
75 unsigned long calc = 0;
76
77 /* generate check for the bootloader to check on resume */
78
79 for (ptr = 0; ptr < 0x40000; ptr += 0x4)
80 calc += __raw_readl(base+ptr);
81
82 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
83 }
84
85 if ( machine_is_aml_m5900() )
86 s3c2410_gpio_setpin(S3C2410_GPF2, 1);
87
88}
89
90static int s3c2410_pm_resume(struct sys_device *dev)
91{
92 unsigned long tmp;
93
94 /* unset the return-from-sleep flag, to ensure reset */
95
96 tmp = __raw_readl(S3C2410_GSTATUS2);
97 tmp &= S3C2410_GSTATUS2_OFFRESET;
98 __raw_writel(tmp, S3C2410_GSTATUS2);
99
100 if ( machine_is_aml_m5900() )
101 s3c2410_gpio_setpin(S3C2410_GPF2, 0);
102
103 return 0;
104}
105
106static int s3c2410_pm_add(struct sys_device *dev)
107{
108 pm_cpu_prep = s3c2410_pm_prepare;
109 pm_cpu_sleep = s3c2410_cpu_suspend;
110
111 return 0;
112}
113
114#if defined(CONFIG_CPU_S3C2410)
115static struct sysdev_driver s3c2410_pm_driver = {
116 .add = s3c2410_pm_add,
117 .resume = s3c2410_pm_resume,
118};
119
120/* register ourselves */
121
122static int __init s3c2410_pm_drvinit(void)
123{
124 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_pm_driver);
125}
126
127arch_initcall(s3c2410_pm_drvinit);
128#endif
129
130#if defined(CONFIG_CPU_S3C2440)
131static struct sysdev_driver s3c2440_pm_driver = {
132 .add = s3c2410_pm_add,
133 .resume = s3c2410_pm_resume,
134};
135
136static int __init s3c2440_pm_drvinit(void)
137{
138 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_pm_driver);
139}
140
141arch_initcall(s3c2440_pm_drvinit);
142#endif
143
144#if defined(CONFIG_CPU_S3C2442)
145static struct sysdev_driver s3c2442_pm_driver = {
146 .add = s3c2410_pm_add,
147 .resume = s3c2410_pm_resume,
148};
149
150static int __init s3c2442_pm_drvinit(void)
151{
152 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_pm_driver);
153}
154
155arch_initcall(s3c2442_pm_drvinit);
156#endif
diff --git a/arch/arm/mach-s3c2410/s3c2410-sleep.S b/arch/arm/mach-s3c2410/s3c2410-sleep.S
deleted file mode 100644
index 9179a1024588..000000000000
--- a/arch/arm/mach-s3c2410/s3c2410-sleep.S
+++ /dev/null
@@ -1,68 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410-sleep.S
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Power Manager (Suspend-To-RAM) support
7 *
8 * Based on PXA/SA1100 sleep code by:
9 * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
10 * Cliff Brake, (c) 2001
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25*/
26
27#include <linux/linkage.h>
28#include <asm/assembler.h>
29#include <asm/hardware.h>
30#include <asm/arch/map.h>
31
32#include <asm/arch/regs-gpio.h>
33#include <asm/arch/regs-clock.h>
34#include <asm/arch/regs-mem.h>
35#include <asm/arch/regs-serial.h>
36
37 /* s3c2410_cpu_suspend
38 *
39 * put the cpu into sleep mode
40 */
41
42ENTRY(s3c2410_cpu_suspend)
43 @@ prepare cpu to sleep
44
45 ldr r4, =S3C2410_REFRESH
46 ldr r5, =S3C24XX_MISCCR
47 ldr r6, =S3C2410_CLKCON
48 ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB)
49 ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB)
50 ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB)
51
52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
54 orr r9, r9, #S3C2410_CLKCON_POWER @ power down command
55
56 teq pc, #0 @ first as a trial-run to load cache
57 bl s3c2410_do_sleep
58 teq r0, r0 @ now do it for real
59 b s3c2410_do_sleep @
60
61 @@ align next bit of code to cache line
62 .align 8
63s3c2410_do_sleep:
64 streq r7, [ r4 ] @ SDRAM sleep command
65 streq r8, [ r5 ] @ SDRAM power-down config
66 streq r9, [ r6 ] @ CPU sleep
671: beq 1b
68 mov pc, r14
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 4cdc0d70c19f..d96fdcf2d2e3 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -31,10 +31,10 @@
31#include <asm/arch/regs-clock.h> 31#include <asm/arch/regs-clock.h>
32#include <asm/arch/regs-serial.h> 32#include <asm/arch/regs-serial.h>
33 33
34#include "s3c2410.h" 34#include <asm/plat-s3c24xx/s3c2410.h>
35#include "cpu.h" 35#include <asm/plat-s3c24xx/cpu.h>
36#include "devs.h" 36#include <asm/plat-s3c24xx/devs.h>
37#include "clock.h" 37#include <asm/plat-s3c24xx/clock.h>
38 38
39/* Initial IO mappings */ 39/* Initial IO mappings */
40 40
diff --git a/arch/arm/mach-s3c2410/s3c2410.h b/arch/arm/mach-s3c2410/s3c2410.h
deleted file mode 100644
index fbed084f26d0..000000000000
--- a/arch/arm/mach-s3c2410/s3c2410.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/* arch/arm/mach-s3c2410/s3c2410.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2410 machine directory
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#ifdef CONFIG_CPU_S3C2410
15
16extern int s3c2410_init(void);
17
18extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
19
20extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
21
22extern void s3c2410_init_clocks(int xtal);
23
24extern int s3c2410_baseclk_add(void);
25
26#else
27#define s3c2410_init_clocks NULL
28#define s3c2410_init_uarts NULL
29#define s3c2410_map_io NULL
30#define s3c2410_init NULL
31#endif
diff --git a/arch/arm/mach-s3c2410/s3c2412-clock.c b/arch/arm/mach-s3c2410/s3c2412-clock.c
deleted file mode 100644
index 8f94ad83901d..000000000000
--- a/arch/arm/mach-s3c2410/s3c2412-clock.c
+++ /dev/null
@@ -1,716 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2412-clock.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412,S3C2413 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/list.h>
27#include <linux/errno.h>
28#include <linux/err.h>
29#include <linux/sysdev.h>
30#include <linux/clk.h>
31#include <linux/mutex.h>
32#include <linux/delay.h>
33#include <linux/serial_core.h>
34
35#include <asm/mach/map.h>
36
37#include <asm/hardware.h>
38#include <asm/io.h>
39
40#include <asm/arch/regs-serial.h>
41#include <asm/arch/regs-clock.h>
42#include <asm/arch/regs-gpio.h>
43
44#include "s3c2412.h"
45#include "clock.h"
46#include "cpu.h"
47
48/* We currently have to assume that the system is running
49 * from the XTPll input, and that all ***REFCLKs are being
50 * fed from it, as we cannot read the state of OM[4] from
51 * software.
52 *
53 * It would be possible for each board initialisation to
54 * set the correct muxing at initialisation
55*/
56
57static int s3c2412_clkcon_enable(struct clk *clk, int enable)
58{
59 unsigned int clocks = clk->ctrlbit;
60 unsigned long clkcon;
61
62 clkcon = __raw_readl(S3C2410_CLKCON);
63
64 if (enable)
65 clkcon |= clocks;
66 else
67 clkcon &= ~clocks;
68
69 __raw_writel(clkcon, S3C2410_CLKCON);
70
71 return 0;
72}
73
74static int s3c2412_upll_enable(struct clk *clk, int enable)
75{
76 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
77 unsigned long orig = upllcon;
78
79 if (!enable)
80 upllcon |= S3C2412_PLLCON_OFF;
81 else
82 upllcon &= ~S3C2412_PLLCON_OFF;
83
84 __raw_writel(upllcon, S3C2410_UPLLCON);
85
86 /* allow ~150uS for the PLL to settle and lock */
87
88 if (enable && (orig & S3C2412_PLLCON_OFF))
89 udelay(150);
90
91 return 0;
92}
93
94/* clock selections */
95
96/* CPU EXTCLK input */
97static struct clk clk_ext = {
98 .name = "extclk",
99 .id = -1,
100};
101
102static struct clk clk_erefclk = {
103 .name = "erefclk",
104 .id = -1,
105};
106
107static struct clk clk_urefclk = {
108 .name = "urefclk",
109 .id = -1,
110};
111
112static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
113{
114 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
115
116 if (parent == &clk_urefclk)
117 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
118 else if (parent == &clk_upll)
119 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
120 else
121 return -EINVAL;
122
123 clk->parent = parent;
124
125 __raw_writel(clksrc, S3C2412_CLKSRC);
126 return 0;
127}
128
129static struct clk clk_usysclk = {
130 .name = "usysclk",
131 .id = -1,
132 .parent = &clk_xtal,
133 .set_parent = s3c2412_setparent_usysclk,
134};
135
136static struct clk clk_mrefclk = {
137 .name = "mrefclk",
138 .parent = &clk_xtal,
139 .id = -1,
140};
141
142static struct clk clk_mdivclk = {
143 .name = "mdivclk",
144 .parent = &clk_xtal,
145 .id = -1,
146};
147
148static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
149{
150 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
151
152 if (parent == &clk_usysclk)
153 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
154 else if (parent == &clk_h)
155 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
156 else
157 return -EINVAL;
158
159 clk->parent = parent;
160
161 __raw_writel(clksrc, S3C2412_CLKSRC);
162 return 0;
163}
164
165static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
166 unsigned long rate)
167{
168 unsigned long parent_rate = clk_get_rate(clk->parent);
169 int div;
170
171 if (rate > parent_rate)
172 return parent_rate;
173
174 div = parent_rate / rate;
175 if (div > 2)
176 div = 2;
177
178 return parent_rate / div;
179}
180
181static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
182{
183 unsigned long parent_rate = clk_get_rate(clk->parent);
184 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
185
186 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
187}
188
189static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
190{
191 unsigned long parent_rate = clk_get_rate(clk->parent);
192 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
193
194 rate = s3c2412_roundrate_usbsrc(clk, rate);
195
196 if ((parent_rate / rate) == 2)
197 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
198 else
199 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
200
201 __raw_writel(clkdivn, S3C2410_CLKDIVN);
202 return 0;
203}
204
205static struct clk clk_usbsrc = {
206 .name = "usbsrc",
207 .id = -1,
208 .get_rate = s3c2412_getrate_usbsrc,
209 .set_rate = s3c2412_setrate_usbsrc,
210 .round_rate = s3c2412_roundrate_usbsrc,
211 .set_parent = s3c2412_setparent_usbsrc,
212};
213
214static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
215{
216 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
217
218 if (parent == &clk_mdivclk)
219 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
220 else if (parent == &clk_upll)
221 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
222 else
223 return -EINVAL;
224
225 clk->parent = parent;
226
227 __raw_writel(clksrc, S3C2412_CLKSRC);
228 return 0;
229}
230
231static struct clk clk_msysclk = {
232 .name = "msysclk",
233 .id = -1,
234 .set_parent = s3c2412_setparent_msysclk,
235};
236
237/* these next clocks have an divider immediately after them,
238 * so we can register them with their divider and leave out the
239 * intermediate clock stage
240*/
241static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
242 unsigned long rate)
243{
244 unsigned long parent_rate = clk_get_rate(clk->parent);
245 int div;
246
247 if (rate > parent_rate)
248 return parent_rate;
249
250 /* note, we remove the +/- 1 calculations as they cancel out */
251
252 div = (rate / parent_rate);
253
254 if (div < 1)
255 div = 1;
256 else if (div > 16)
257 div = 16;
258
259 return parent_rate / div;
260}
261
262static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
263{
264 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
265
266 if (parent == &clk_erefclk)
267 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
268 else if (parent == &clk_mpll)
269 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
270 else
271 return -EINVAL;
272
273 clk->parent = parent;
274
275 __raw_writel(clksrc, S3C2412_CLKSRC);
276 return 0;
277}
278
279static unsigned long s3c2412_getrate_uart(struct clk *clk)
280{
281 unsigned long parent_rate = clk_get_rate(clk->parent);
282 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
283
284 div &= S3C2412_CLKDIVN_UARTDIV_MASK;
285 div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
286
287 return parent_rate / (div + 1);
288}
289
290static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
291{
292 unsigned long parent_rate = clk_get_rate(clk->parent);
293 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
294
295 rate = s3c2412_roundrate_clksrc(clk, rate);
296
297 clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
298 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
299
300 __raw_writel(clkdivn, S3C2410_CLKDIVN);
301 return 0;
302}
303
304static struct clk clk_uart = {
305 .name = "uartclk",
306 .id = -1,
307 .get_rate = s3c2412_getrate_uart,
308 .set_rate = s3c2412_setrate_uart,
309 .set_parent = s3c2412_setparent_uart,
310 .round_rate = s3c2412_roundrate_clksrc,
311};
312
313static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
314{
315 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
316
317 if (parent == &clk_erefclk)
318 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
319 else if (parent == &clk_mpll)
320 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
321 else
322 return -EINVAL;
323
324 clk->parent = parent;
325
326 __raw_writel(clksrc, S3C2412_CLKSRC);
327 return 0;
328}
329
330static unsigned long s3c2412_getrate_i2s(struct clk *clk)
331{
332 unsigned long parent_rate = clk_get_rate(clk->parent);
333 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
334
335 div &= S3C2412_CLKDIVN_I2SDIV_MASK;
336 div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
337
338 return parent_rate / (div + 1);
339}
340
341static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
342{
343 unsigned long parent_rate = clk_get_rate(clk->parent);
344 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
345
346 rate = s3c2412_roundrate_clksrc(clk, rate);
347
348 clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
349 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
350
351 __raw_writel(clkdivn, S3C2410_CLKDIVN);
352 return 0;
353}
354
355static struct clk clk_i2s = {
356 .name = "i2sclk",
357 .id = -1,
358 .get_rate = s3c2412_getrate_i2s,
359 .set_rate = s3c2412_setrate_i2s,
360 .set_parent = s3c2412_setparent_i2s,
361 .round_rate = s3c2412_roundrate_clksrc,
362};
363
364static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
365{
366 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
367
368 if (parent == &clk_usysclk)
369 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
370 else if (parent == &clk_h)
371 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
372 else
373 return -EINVAL;
374
375 clk->parent = parent;
376
377 __raw_writel(clksrc, S3C2412_CLKSRC);
378 return 0;
379}
380static unsigned long s3c2412_getrate_cam(struct clk *clk)
381{
382 unsigned long parent_rate = clk_get_rate(clk->parent);
383 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
384
385 div &= S3C2412_CLKDIVN_CAMDIV_MASK;
386 div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
387
388 return parent_rate / (div + 1);
389}
390
391static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
392{
393 unsigned long parent_rate = clk_get_rate(clk->parent);
394 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
395
396 rate = s3c2412_roundrate_clksrc(clk, rate);
397
398 clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
399 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
400
401 __raw_writel(clkdivn, S3C2410_CLKDIVN);
402 return 0;
403}
404
405static struct clk clk_cam = {
406 .name = "camif-upll", /* same as 2440 name */
407 .id = -1,
408 .get_rate = s3c2412_getrate_cam,
409 .set_rate = s3c2412_setrate_cam,
410 .set_parent = s3c2412_setparent_cam,
411 .round_rate = s3c2412_roundrate_clksrc,
412};
413
414/* standard clock definitions */
415
416static struct clk init_clocks_disable[] = {
417 {
418 .name = "nand",
419 .id = -1,
420 .parent = &clk_h,
421 .enable = s3c2412_clkcon_enable,
422 .ctrlbit = S3C2412_CLKCON_NAND,
423 }, {
424 .name = "sdi",
425 .id = -1,
426 .parent = &clk_p,
427 .enable = s3c2412_clkcon_enable,
428 .ctrlbit = S3C2412_CLKCON_SDI,
429 }, {
430 .name = "adc",
431 .id = -1,
432 .parent = &clk_p,
433 .enable = s3c2412_clkcon_enable,
434 .ctrlbit = S3C2412_CLKCON_ADC,
435 }, {
436 .name = "i2c",
437 .id = -1,
438 .parent = &clk_p,
439 .enable = s3c2412_clkcon_enable,
440 .ctrlbit = S3C2412_CLKCON_IIC,
441 }, {
442 .name = "iis",
443 .id = -1,
444 .parent = &clk_p,
445 .enable = s3c2412_clkcon_enable,
446 .ctrlbit = S3C2412_CLKCON_IIS,
447 }, {
448 .name = "spi",
449 .id = -1,
450 .parent = &clk_p,
451 .enable = s3c2412_clkcon_enable,
452 .ctrlbit = S3C2412_CLKCON_SPI,
453 }
454};
455
456static struct clk init_clocks[] = {
457 {
458 .name = "dma",
459 .id = 0,
460 .parent = &clk_h,
461 .enable = s3c2412_clkcon_enable,
462 .ctrlbit = S3C2412_CLKCON_DMA0,
463 }, {
464 .name = "dma",
465 .id = 1,
466 .parent = &clk_h,
467 .enable = s3c2412_clkcon_enable,
468 .ctrlbit = S3C2412_CLKCON_DMA1,
469 }, {
470 .name = "dma",
471 .id = 2,
472 .parent = &clk_h,
473 .enable = s3c2412_clkcon_enable,
474 .ctrlbit = S3C2412_CLKCON_DMA2,
475 }, {
476 .name = "dma",
477 .id = 3,
478 .parent = &clk_h,
479 .enable = s3c2412_clkcon_enable,
480 .ctrlbit = S3C2412_CLKCON_DMA3,
481 }, {
482 .name = "lcd",
483 .id = -1,
484 .parent = &clk_h,
485 .enable = s3c2412_clkcon_enable,
486 .ctrlbit = S3C2412_CLKCON_LCDC,
487 }, {
488 .name = "gpio",
489 .id = -1,
490 .parent = &clk_p,
491 .enable = s3c2412_clkcon_enable,
492 .ctrlbit = S3C2412_CLKCON_GPIO,
493 }, {
494 .name = "usb-host",
495 .id = -1,
496 .parent = &clk_h,
497 .enable = s3c2412_clkcon_enable,
498 .ctrlbit = S3C2412_CLKCON_USBH,
499 }, {
500 .name = "usb-device",
501 .id = -1,
502 .parent = &clk_h,
503 .enable = s3c2412_clkcon_enable,
504 .ctrlbit = S3C2412_CLKCON_USBD,
505 }, {
506 .name = "timers",
507 .id = -1,
508 .parent = &clk_p,
509 .enable = s3c2412_clkcon_enable,
510 .ctrlbit = S3C2412_CLKCON_PWMT,
511 }, {
512 .name = "uart",
513 .id = 0,
514 .parent = &clk_p,
515 .enable = s3c2412_clkcon_enable,
516 .ctrlbit = S3C2412_CLKCON_UART0,
517 }, {
518 .name = "uart",
519 .id = 1,
520 .parent = &clk_p,
521 .enable = s3c2412_clkcon_enable,
522 .ctrlbit = S3C2412_CLKCON_UART1,
523 }, {
524 .name = "uart",
525 .id = 2,
526 .parent = &clk_p,
527 .enable = s3c2412_clkcon_enable,
528 .ctrlbit = S3C2412_CLKCON_UART2,
529 }, {
530 .name = "rtc",
531 .id = -1,
532 .parent = &clk_p,
533 .enable = s3c2412_clkcon_enable,
534 .ctrlbit = S3C2412_CLKCON_RTC,
535 }, {
536 .name = "watchdog",
537 .id = -1,
538 .parent = &clk_p,
539 .ctrlbit = 0,
540 }, {
541 .name = "usb-bus-gadget",
542 .id = -1,
543 .parent = &clk_usb_bus,
544 .enable = s3c2412_clkcon_enable,
545 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
546 }, {
547 .name = "usb-bus-host",
548 .id = -1,
549 .parent = &clk_usb_bus,
550 .enable = s3c2412_clkcon_enable,
551 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
552 }
553};
554
555/* clocks to add where we need to check their parentage */
556
557struct clk_init {
558 struct clk *clk;
559 unsigned int bit;
560 struct clk *src_0;
561 struct clk *src_1;
562};
563
564static struct clk_init clks_src[] __initdata = {
565 {
566 .clk = &clk_usysclk,
567 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
568 .src_0 = &clk_urefclk,
569 .src_1 = &clk_upll,
570 }, {
571 .clk = &clk_i2s,
572 .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
573 .src_0 = &clk_erefclk,
574 .src_1 = &clk_mpll,
575 }, {
576 .clk = &clk_cam,
577 .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
578 .src_0 = &clk_usysclk,
579 .src_1 = &clk_h,
580 }, {
581 .clk = &clk_msysclk,
582 .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
583 .src_0 = &clk_mdivclk,
584 .src_1 = &clk_mpll,
585 }, {
586 .clk = &clk_uart,
587 .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
588 .src_0 = &clk_erefclk,
589 .src_1 = &clk_mpll,
590 }, {
591 .clk = &clk_usbsrc,
592 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
593 .src_0 = &clk_usysclk,
594 .src_1 = &clk_h,
595 },
596};
597
598/* s3c2412_clk_initparents
599 *
600 * Initialise the parents for the clocks that we get at start-time
601*/
602
603static void __init s3c2412_clk_initparents(void)
604{
605 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
606 struct clk_init *cip = clks_src;
607 struct clk *src;
608 int ptr;
609 int ret;
610
611 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
612 ret = s3c24xx_register_clock(cip->clk);
613 if (ret < 0) {
614 printk(KERN_ERR "Failed to register clock %s (%d)\n",
615 cip->clk->name, ret);
616 }
617
618 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
619
620 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
621 clk_set_parent(cip->clk, src);
622 }
623}
624
625/* clocks to add straight away */
626
627static struct clk *clks[] __initdata = {
628 &clk_ext,
629 &clk_usb_bus,
630 &clk_erefclk,
631 &clk_urefclk,
632 &clk_mrefclk,
633};
634
635int __init s3c2412_baseclk_add(void)
636{
637 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
638 struct clk *clkp;
639 int ret;
640 int ptr;
641
642 clk_upll.enable = s3c2412_upll_enable;
643 clk_usb_bus.parent = &clk_usbsrc;
644 clk_usb_bus.rate = 0x0;
645
646 s3c2412_clk_initparents();
647
648 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
649 clkp = clks[ptr];
650
651 ret = s3c24xx_register_clock(clkp);
652 if (ret < 0) {
653 printk(KERN_ERR "Failed to register clock %s (%d)\n",
654 clkp->name, ret);
655 }
656 }
657
658 /* ensure usb bus clock is within correct rate of 48MHz */
659
660 if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
661 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
662
663 /* for the moment, let's use the UPLL, and see if we can
664 * get 48MHz */
665
666 clk_set_parent(&clk_usysclk, &clk_upll);
667 clk_set_parent(&clk_usbsrc, &clk_usysclk);
668 clk_set_rate(&clk_usbsrc, 48*1000*1000);
669 }
670
671 printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
672 (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
673 print_mhz(clk_get_rate(&clk_upll)),
674 print_mhz(clk_get_rate(&clk_usb_bus)));
675
676 /* register clocks from clock array */
677
678 clkp = init_clocks;
679 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
680 /* ensure that we note the clock state */
681
682 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
683
684 ret = s3c24xx_register_clock(clkp);
685 if (ret < 0) {
686 printk(KERN_ERR "Failed to register clock %s (%d)\n",
687 clkp->name, ret);
688 }
689 }
690
691 /* We must be careful disabling the clocks we are not intending to
692 * be using at boot time, as subsytems such as the LCD which do
693 * their own DMA requests to the bus can cause the system to lockup
694 * if they where in the middle of requesting bus access.
695 *
696 * Disabling the LCD clock if the LCD is active is very dangerous,
697 * and therefore the bootloader should be careful to not enable
698 * the LCD clock if it is not needed.
699 */
700
701 /* install (and disable) the clocks we do not need immediately */
702
703 clkp = init_clocks_disable;
704 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
705
706 ret = s3c24xx_register_clock(clkp);
707 if (ret < 0) {
708 printk(KERN_ERR "Failed to register clock %s (%d)\n",
709 clkp->name, ret);
710 }
711
712 s3c2412_clkcon_enable(clkp, 0);
713 }
714
715 return 0;
716}
diff --git a/arch/arm/mach-s3c2410/s3c2412-dma.c b/arch/arm/mach-s3c2410/s3c2412-dma.c
deleted file mode 100644
index 138f726ac6bf..000000000000
--- a/arch/arm/mach-s3c2410/s3c2412-dma.c
+++ /dev/null
@@ -1,161 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2412-dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18#include <linux/serial_core.h>
19
20#include <asm/dma.h>
21#include <asm/arch/dma.h>
22#include <asm/io.h>
23
24#include "dma.h"
25#include "cpu.h"
26
27#include <asm/arch/regs-serial.h>
28#include <asm/arch/regs-gpio.h>
29#include <asm/arch/regs-ac97.h>
30#include <asm/arch/regs-mem.h>
31#include <asm/arch/regs-lcd.h>
32#include <asm/arch/regs-sdi.h>
33#include <asm/arch/regs-iis.h>
34#include <asm/arch/regs-spi.h>
35
36#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
37
38static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
39 [DMACH_XD0] = {
40 .name = "xdreq0",
41 .channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
42 },
43 [DMACH_XD1] = {
44 .name = "xdreq1",
45 .channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
46 },
47 [DMACH_SDI] = {
48 .name = "sdi",
49 .channels = MAP(S3C2412_DMAREQSEL_SDI),
50 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
51 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
52 },
53 [DMACH_SPI0] = {
54 .name = "spi0",
55 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
56 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
57 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
58 },
59 [DMACH_SPI1] = {
60 .name = "spi1",
61 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
62 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
63 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
64 },
65 [DMACH_UART0] = {
66 .name = "uart0",
67 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
68 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
69 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
70 },
71 [DMACH_UART1] = {
72 .name = "uart1",
73 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
74 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
75 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
76 },
77 [DMACH_UART2] = {
78 .name = "uart2",
79 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
80 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
81 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
82 },
83 [DMACH_UART0_SRC2] = {
84 .name = "uart0",
85 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
86 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
87 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
88 },
89 [DMACH_UART1_SRC2] = {
90 .name = "uart1",
91 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
92 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
93 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
94 },
95 [DMACH_UART2_SRC2] = {
96 .name = "uart2",
97 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
98 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
99 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
100 },
101 [DMACH_TIMER] = {
102 .name = "timer",
103 .channels = MAP(S3C2412_DMAREQSEL_TIMER),
104 },
105 [DMACH_I2S_IN] = {
106 .name = "i2s-sdi",
107 .channels = MAP(S3C2412_DMAREQSEL_I2SRX),
108 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
109 },
110 [DMACH_I2S_OUT] = {
111 .name = "i2s-sdo",
112 .channels = MAP(S3C2412_DMAREQSEL_I2STX),
113 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
114 },
115 [DMACH_USB_EP1] = {
116 .name = "usb-ep1",
117 .channels = MAP(S3C2412_DMAREQSEL_USBEP1),
118 },
119 [DMACH_USB_EP2] = {
120 .name = "usb-ep2",
121 .channels = MAP(S3C2412_DMAREQSEL_USBEP2),
122 },
123 [DMACH_USB_EP3] = {
124 .name = "usb-ep3",
125 .channels = MAP(S3C2412_DMAREQSEL_USBEP3),
126 },
127 [DMACH_USB_EP4] = {
128 .name = "usb-ep4",
129 .channels = MAP(S3C2412_DMAREQSEL_USBEP4),
130 },
131};
132
133static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
134 struct s3c24xx_dma_map *map)
135{
136 writel(map->channels[0] | S3C2412_DMAREQSEL_HW,
137 chan->regs + S3C2412_DMA_DMAREQSEL);
138}
139
140static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
141 .select = s3c2412_dma_select,
142 .dcon_mask = 0,
143 .map = s3c2412_dma_mappings,
144 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
145};
146
147static int s3c2412_dma_add(struct sys_device *sysdev)
148{
149 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
150}
151
152static struct sysdev_driver s3c2412_dma_driver = {
153 .add = s3c2412_dma_add,
154};
155
156static int __init s3c2412_dma_init(void)
157{
158 return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
159}
160
161arch_initcall(s3c2412_dma_init);
diff --git a/arch/arm/mach-s3c2410/s3c2412-irq.c b/arch/arm/mach-s3c2410/s3c2412-irq.c
deleted file mode 100644
index ffcc30b23a80..000000000000
--- a/arch/arm/mach-s3c2410/s3c2412-irq.c
+++ /dev/null
@@ -1,133 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/s3c2412-irq.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/ptrace.h>
27#include <linux/sysdev.h>
28
29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/io.h>
32
33#include <asm/mach/irq.h>
34
35#include <asm/arch/regs-irq.h>
36#include <asm/arch/regs-gpio.h>
37
38#include "cpu.h"
39#include "irq.h"
40#include "pm.h"
41
42/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
43 * having them turn up in both the INT* and the EINT* registers. Whilst
44 * both show the status, they both now need to be acked when the IRQs
45 * go off.
46*/
47
48static void
49s3c2412_irq_mask(unsigned int irqno)
50{
51 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
52 unsigned long mask;
53
54 mask = __raw_readl(S3C2410_INTMSK);
55 __raw_writel(mask | bitval, S3C2410_INTMSK);
56
57 mask = __raw_readl(S3C2412_EINTMASK);
58 __raw_writel(mask | bitval, S3C2412_EINTMASK);
59}
60
61static inline void
62s3c2412_irq_ack(unsigned int irqno)
63{
64 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
65
66 __raw_writel(bitval, S3C2412_EINTPEND);
67 __raw_writel(bitval, S3C2410_SRCPND);
68 __raw_writel(bitval, S3C2410_INTPND);
69}
70
71static inline void
72s3c2412_irq_maskack(unsigned int irqno)
73{
74 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
75 unsigned long mask;
76
77 mask = __raw_readl(S3C2410_INTMSK);
78 __raw_writel(mask|bitval, S3C2410_INTMSK);
79
80 mask = __raw_readl(S3C2412_EINTMASK);
81 __raw_writel(mask | bitval, S3C2412_EINTMASK);
82
83 __raw_writel(bitval, S3C2412_EINTPEND);
84 __raw_writel(bitval, S3C2410_SRCPND);
85 __raw_writel(bitval, S3C2410_INTPND);
86}
87
88static void
89s3c2412_irq_unmask(unsigned int irqno)
90{
91 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
92 unsigned long mask;
93
94 mask = __raw_readl(S3C2412_EINTMASK);
95 __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
96
97 mask = __raw_readl(S3C2410_INTMSK);
98 __raw_writel(mask & ~bitval, S3C2410_INTMSK);
99}
100
101static struct irq_chip s3c2412_irq_eint0t4 = {
102 .ack = s3c2412_irq_ack,
103 .mask = s3c2412_irq_mask,
104 .unmask = s3c2412_irq_unmask,
105 .set_wake = s3c_irq_wake,
106 .set_type = s3c_irqext_type,
107};
108
109static int s3c2412_irq_add(struct sys_device *sysdev)
110{
111 unsigned int irqno;
112
113 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
114 set_irq_chip(irqno, &s3c2412_irq_eint0t4);
115 set_irq_handler(irqno, handle_edge_irq);
116 set_irq_flags(irqno, IRQF_VALID);
117 }
118
119 return 0;
120}
121
122static struct sysdev_driver s3c2412_irq_driver = {
123 .add = s3c2412_irq_add,
124 .suspend = s3c24xx_irq_suspend,
125 .resume = s3c24xx_irq_resume,
126};
127
128static int s3c2412_irq_init(void)
129{
130 return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver);
131}
132
133arch_initcall(s3c2412_irq_init);
diff --git a/arch/arm/mach-s3c2410/s3c2412-pm.c b/arch/arm/mach-s3c2410/s3c2412-pm.c
deleted file mode 100644
index 19b63322d259..000000000000
--- a/arch/arm/mach-s3c2410/s3c2412-pm.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2412-pm.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/sysdev.h>
20#include <linux/platform_device.h>
21
22#include <asm/hardware.h>
23#include <asm/io.h>
24#include <asm/irq.h>
25
26#include <asm/arch/regs-power.h>
27#include <asm/arch/regs-gpioj.h>
28#include <asm/arch/regs-gpio.h>
29#include <asm/arch/regs-dsc.h>
30
31#include "cpu.h"
32#include "pm.h"
33
34#include "s3c2412.h"
35
36static void s3c2412_cpu_suspend(void)
37{
38 unsigned long tmp;
39
40 /* set our standby method to sleep */
41
42 tmp = __raw_readl(S3C2412_PWRCFG);
43 tmp |= S3C2412_PWRCFG_STANDBYWFI_SLEEP;
44 __raw_writel(tmp, S3C2412_PWRCFG);
45
46 /* issue the standby signal into the pm unit. Note, we
47 * issue a write-buffer drain just in case */
48
49 tmp = 0;
50
51 asm("b 1f\n\t"
52 ".align 5\n\t"
53 "1:\n\t"
54 "mcr p15, 0, %0, c7, c10, 4\n\t"
55 "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
56
57 /* we should never get past here */
58
59 panic("sleep resumed to originator?");
60}
61
62static void s3c2412_pm_prepare(void)
63{
64}
65
66static int s3c2412_pm_add(struct sys_device *sysdev)
67{
68 pm_cpu_prep = s3c2412_pm_prepare;
69 pm_cpu_sleep = s3c2412_cpu_suspend;
70
71 return 0;
72}
73
74static struct sleep_save s3c2412_sleep[] = {
75 SAVE_ITEM(S3C2412_DSC0),
76 SAVE_ITEM(S3C2412_DSC1),
77 SAVE_ITEM(S3C2413_GPJDAT),
78 SAVE_ITEM(S3C2413_GPJCON),
79 SAVE_ITEM(S3C2413_GPJUP),
80
81 /* save the PWRCFG to get back to original sleep method */
82
83 SAVE_ITEM(S3C2412_PWRCFG),
84
85 /* save the sleep configuration anyway, just in case these
86 * get damaged during wakeup */
87
88 SAVE_ITEM(S3C2412_GPBSLPCON),
89 SAVE_ITEM(S3C2412_GPCSLPCON),
90 SAVE_ITEM(S3C2412_GPDSLPCON),
91 SAVE_ITEM(S3C2412_GPESLPCON),
92 SAVE_ITEM(S3C2412_GPFSLPCON),
93 SAVE_ITEM(S3C2412_GPGSLPCON),
94 SAVE_ITEM(S3C2412_GPHSLPCON),
95 SAVE_ITEM(S3C2413_GPJSLPCON),
96};
97
98static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state)
99{
100 s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
101 return 0;
102}
103
104static int s3c2412_pm_resume(struct sys_device *dev)
105{
106 unsigned long tmp;
107
108 tmp = __raw_readl(S3C2412_PWRCFG);
109 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
110 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
111 __raw_writel(tmp, S3C2412_PWRCFG);
112
113 s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
114 return 0;
115}
116
117static struct sysdev_driver s3c2412_pm_driver = {
118 .add = s3c2412_pm_add,
119 .suspend = s3c2412_pm_suspend,
120 .resume = s3c2412_pm_resume,
121};
122
123static __init int s3c2412_pm_init(void)
124{
125 return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver);
126}
127
128arch_initcall(s3c2412_pm_init);
diff --git a/arch/arm/mach-s3c2410/s3c2412.c b/arch/arm/mach-s3c2410/s3c2412.c
deleted file mode 100644
index 2f651a811ecd..000000000000
--- a/arch/arm/mach-s3c2410/s3c2412.c
+++ /dev/null
@@ -1,181 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2412.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <asm/hardware.h>
28#include <asm/proc-fns.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31
32#include <asm/arch/idle.h>
33
34#include <asm/arch/regs-clock.h>
35#include <asm/arch/regs-serial.h>
36#include <asm/arch/regs-power.h>
37#include <asm/arch/regs-gpio.h>
38#include <asm/arch/regs-gpioj.h>
39#include <asm/arch/regs-dsc.h>
40
41#include "s3c2412.h"
42#include "cpu.h"
43#include "devs.h"
44#include "clock.h"
45#include "pm.h"
46
47#ifndef CONFIG_CPU_S3C2412_ONLY
48void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
49
50static inline void s3c2412_init_gpio2(void)
51{
52 s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
53}
54#else
55#define s3c2412_init_gpio2() do { } while(0)
56#endif
57
58/* Initial IO mappings */
59
60static struct map_desc s3c2412_iodesc[] __initdata = {
61 IODESC_ENT(CLKPWR),
62 IODESC_ENT(LCD),
63 IODESC_ENT(TIMER),
64 IODESC_ENT(WATCHDOG),
65};
66
67/* uart registration process */
68
69void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
70{
71 s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
72
73 /* rename devices that are s3c2412/s3c2413 specific */
74 s3c_device_sdi.name = "s3c2412-sdi";
75 s3c_device_lcd.name = "s3c2412-lcd";
76 s3c_device_nand.name = "s3c2412-nand";
77}
78
79/* s3c2412_idle
80 *
81 * use the standard idle call by ensuring the idle mode
82 * in power config, then issuing the idle co-processor
83 * instruction
84*/
85
86static void s3c2412_idle(void)
87{
88 unsigned long tmp;
89
90 /* ensure our idle mode is to go to idle */
91
92 tmp = __raw_readl(S3C2412_PWRCFG);
93 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
94 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
95 __raw_writel(tmp, S3C2412_PWRCFG);
96
97 cpu_do_idle();
98}
99
100/* s3c2412_map_io
101 *
102 * register the standard cpu IO areas, and any passed in from the
103 * machine specific initialisation.
104*/
105
106void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
107{
108 /* move base of IO */
109
110 s3c2412_init_gpio2();
111
112 /* set our idle function */
113
114 s3c24xx_idle = s3c2412_idle;
115
116 /* register our io-tables */
117
118 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
119 iotable_init(mach_desc, mach_size);
120}
121
122void __init s3c2412_init_clocks(int xtal)
123{
124 unsigned long tmp;
125 unsigned long fclk;
126 unsigned long hclk;
127 unsigned long pclk;
128
129 /* now we've got our machine bits initialised, work out what
130 * clocks we've got */
131
132 fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
133
134 tmp = __raw_readl(S3C2410_CLKDIVN);
135
136 /* work out clock scalings */
137
138 hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
139 hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1);
140 pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
141
142 /* print brieft summary of clocks, etc */
143
144 printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
145 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
146
147 /* initialise the clocks here, to allow other things like the
148 * console to use them
149 */
150
151 s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
152 s3c2412_baseclk_add();
153}
154
155/* need to register class before we actually register the device, and
156 * we also need to ensure that it has been initialised before any of the
157 * drivers even try to use it (even if not on an s3c2412 based system)
158 * as a driver which may support both 2410 and 2440 may try and use it.
159*/
160
161struct sysdev_class s3c2412_sysclass = {
162 set_kset_name("s3c2412-core"),
163};
164
165static int __init s3c2412_core_init(void)
166{
167 return sysdev_class_register(&s3c2412_sysclass);
168}
169
170core_initcall(s3c2412_core_init);
171
172static struct sys_device s3c2412_sysdev = {
173 .cls = &s3c2412_sysclass,
174};
175
176int __init s3c2412_init(void)
177{
178 printk("S3C2412: Initialising architecture\n");
179
180 return sysdev_register(&s3c2412_sysdev);
181}
diff --git a/arch/arm/mach-s3c2410/s3c2412.h b/arch/arm/mach-s3c2410/s3c2412.h
deleted file mode 100644
index c6e56032a6e7..000000000000
--- a/arch/arm/mach-s3c2410/s3c2412.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/* arch/arm/mach-s3c2410/s3c2412.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2412 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2412
14
15extern int s3c2412_init(void);
16
17extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
18
19extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
20
21extern void s3c2412_init_clocks(int xtal);
22
23extern int s3c2412_baseclk_add(void);
24#else
25#define s3c2412_init_clocks NULL
26#define s3c2412_init_uarts NULL
27#define s3c2412_map_io NULL
28#define s3c2412_init NULL
29#endif
diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c b/arch/arm/mach-s3c2410/s3c2440-clock.c
deleted file mode 100644
index ba13c1d079d1..000000000000
--- a/arch/arm/mach-s3c2410/s3c2440-clock.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440-clock.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440 Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/mutex.h>
35#include <linux/clk.h>
36
37#include <asm/hardware.h>
38#include <asm/atomic.h>
39#include <asm/irq.h>
40#include <asm/io.h>
41
42#include <asm/arch/regs-clock.h>
43
44#include "clock.h"
45#include "cpu.h"
46
47/* S3C2440 extended clock support */
48
49static unsigned long s3c2440_camif_upll_round(struct clk *clk,
50 unsigned long rate)
51{
52 unsigned long parent_rate = clk_get_rate(clk->parent);
53 int div;
54
55 if (rate > parent_rate)
56 return parent_rate;
57
58 /* note, we remove the +/- 1 calculations for the divisor */
59
60 div = (parent_rate / rate) / 2;
61
62 if (div < 1)
63 div = 1;
64 else if (div > 16)
65 div = 16;
66
67 return parent_rate / (div * 2);
68}
69
70static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
71{
72 unsigned long parent_rate = clk_get_rate(clk->parent);
73 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
74
75 rate = s3c2440_camif_upll_round(clk, rate);
76
77 camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
78
79 if (rate != parent_rate) {
80 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
81 camdivn |= (((parent_rate / rate) / 2) - 1);
82 }
83
84 __raw_writel(camdivn, S3C2440_CAMDIVN);
85
86 return 0;
87}
88
89/* Extra S3C2440 clocks */
90
91static struct clk s3c2440_clk_cam = {
92 .name = "camif",
93 .id = -1,
94 .enable = s3c2410_clkcon_enable,
95 .ctrlbit = S3C2440_CLKCON_CAMERA,
96};
97
98static struct clk s3c2440_clk_cam_upll = {
99 .name = "camif-upll",
100 .id = -1,
101 .set_rate = s3c2440_camif_upll_setrate,
102 .round_rate = s3c2440_camif_upll_round,
103};
104
105static struct clk s3c2440_clk_ac97 = {
106 .name = "ac97",
107 .id = -1,
108 .enable = s3c2410_clkcon_enable,
109 .ctrlbit = S3C2440_CLKCON_CAMERA,
110};
111
112static int s3c2440_clk_add(struct sys_device *sysdev)
113{
114 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
115 unsigned long clkdivn;
116 struct clk *clock_h;
117 struct clk *clock_p;
118 struct clk *clock_upll;
119
120 printk("S3C2440: Clock Support, DVS %s\n",
121 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
122
123 clock_p = clk_get(NULL, "pclk");
124 clock_h = clk_get(NULL, "hclk");
125 clock_upll = clk_get(NULL, "upll");
126
127 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
128 printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
129 return -EINVAL;
130 }
131
132 /* check rate of UPLL, and if it is near 96MHz, then change
133 * to using half the UPLL rate for the system */
134
135 if (clk_get_rate(clock_upll) > (94 * MHZ)) {
136 clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
137
138 mutex_lock(&clocks_mutex);
139
140 clkdivn = __raw_readl(S3C2410_CLKDIVN);
141 clkdivn |= S3C2440_CLKDIVN_UCLK;
142 __raw_writel(clkdivn, S3C2410_CLKDIVN);
143
144 mutex_unlock(&clocks_mutex);
145 }
146
147 s3c2440_clk_cam.parent = clock_h;
148 s3c2440_clk_ac97.parent = clock_p;
149 s3c2440_clk_cam_upll.parent = clock_upll;
150
151 s3c24xx_register_clock(&s3c2440_clk_ac97);
152 s3c24xx_register_clock(&s3c2440_clk_cam);
153 s3c24xx_register_clock(&s3c2440_clk_cam_upll);
154
155 clk_disable(&s3c2440_clk_ac97);
156 clk_disable(&s3c2440_clk_cam);
157
158 return 0;
159}
160
161static struct sysdev_driver s3c2440_clk_driver = {
162 .add = s3c2440_clk_add,
163};
164
165static __init int s3c24xx_clk_driver(void)
166{
167 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
168}
169
170arch_initcall(s3c24xx_clk_driver);
diff --git a/arch/arm/mach-s3c2410/s3c2440-dma.c b/arch/arm/mach-s3c2410/s3c2440-dma.c
deleted file mode 100644
index 47b861b9443d..000000000000
--- a/arch/arm/mach-s3c2410/s3c2440-dma.c
+++ /dev/null
@@ -1,165 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440-dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2440 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18#include <linux/serial_core.h>
19
20#include <asm/dma.h>
21#include <asm/arch/dma.h>
22#include "dma.h"
23
24#include "cpu.h"
25
26#include <asm/arch/regs-serial.h>
27#include <asm/arch/regs-gpio.h>
28#include <asm/arch/regs-ac97.h>
29#include <asm/arch/regs-mem.h>
30#include <asm/arch/regs-lcd.h>
31#include <asm/arch/regs-sdi.h>
32#include <asm/arch/regs-iis.h>
33#include <asm/arch/regs-spi.h>
34
35static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
36 [DMACH_XD0] = {
37 .name = "xdreq0",
38 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
39 },
40 [DMACH_XD1] = {
41 .name = "xdreq1",
42 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
43 },
44 [DMACH_SDI] = {
45 .name = "sdi",
46 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
47 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
48 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
49 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
50 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
51 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
52 },
53 [DMACH_SPI0] = {
54 .name = "spi0",
55 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
56 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
57 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
58 },
59 [DMACH_SPI1] = {
60 .name = "spi1",
61 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
62 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
63 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
64 },
65 [DMACH_UART0] = {
66 .name = "uart0",
67 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
68 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
69 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
70 },
71 [DMACH_UART1] = {
72 .name = "uart1",
73 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
74 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
75 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
76 },
77 [DMACH_UART2] = {
78 .name = "uart2",
79 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
80 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
81 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
82 },
83 [DMACH_TIMER] = {
84 .name = "timer",
85 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
86 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
87 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
88 },
89 [DMACH_I2S_IN] = {
90 .name = "i2s-sdi",
91 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
92 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
93 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
94 },
95 [DMACH_I2S_OUT] = {
96 .name = "i2s-sdo",
97 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
98 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
99 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
100 },
101 [DMACH_PCM_IN] = {
102 .name = "pcm-in",
103 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
104 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
105 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
106 },
107 [DMACH_PCM_OUT] = {
108 .name = "pcm-out",
109 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
110 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
111 .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
112 },
113 [DMACH_MIC_IN] = {
114 .name = "mic-in",
115 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
116 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
117 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
118 },
119 [DMACH_USB_EP1] = {
120 .name = "usb-ep1",
121 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
122 },
123 [DMACH_USB_EP2] = {
124 .name = "usb-ep2",
125 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
126 },
127 [DMACH_USB_EP3] = {
128 .name = "usb-ep3",
129 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
130 },
131 [DMACH_USB_EP4] = {
132 .name = "usb-ep4",
133 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
134 },
135};
136
137static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
138 struct s3c24xx_dma_map *map)
139{
140 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
141}
142
143static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
144 .select = s3c2440_dma_select,
145 .dcon_mask = 7 << 24,
146 .map = s3c2440_dma_mappings,
147 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
148};
149
150static int s3c2440_dma_add(struct sys_device *sysdev)
151{
152 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
153}
154
155static struct sysdev_driver s3c2440_dma_driver = {
156 .add = s3c2440_dma_add,
157};
158
159static int __init s3c2440_dma_init(void)
160{
161 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver);
162}
163
164arch_initcall(s3c2440_dma_init);
165
diff --git a/arch/arm/mach-s3c2410/s3c2440-dsc.c b/arch/arm/mach-s3c2410/s3c2440-dsc.c
deleted file mode 100644
index c92ea66ba45e..000000000000
--- a/arch/arm/mach-s3c2410/s3c2440-dsc.c
+++ /dev/null
@@ -1,54 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440-dsc.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 Drive Strength Control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/init.h>
17#include <linux/module.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/mach/irq.h>
22
23#include <asm/hardware.h>
24#include <asm/io.h>
25#include <asm/irq.h>
26
27#include <asm/arch/regs-gpio.h>
28#include <asm/arch/regs-dsc.h>
29
30#include "cpu.h"
31#include "s3c2440.h"
32
33int s3c2440_set_dsc(unsigned int pin, unsigned int value)
34{
35 void __iomem *base;
36 unsigned long val;
37 unsigned long flags;
38 unsigned long mask;
39
40 base = (pin & S3C2440_SELECT_DSC1) ? S3C2440_DSC1 : S3C2440_DSC0;
41 mask = 3 << S3C2440_DSC_GETSHIFT(pin);
42
43 local_irq_save(flags);
44
45 val = __raw_readl(base);
46 val &= ~mask;
47 val |= value & mask;
48 __raw_writel(val, base);
49
50 local_irq_restore(flags);
51 return 0;
52}
53
54EXPORT_SYMBOL(s3c2440_set_dsc);
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
deleted file mode 100644
index 1ba19b27ab05..000000000000
--- a/arch/arm/mach-s3c2410/s3c2440-irq.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440-irq.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/ptrace.h>
27#include <linux/sysdev.h>
28
29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/io.h>
32
33#include <asm/mach/irq.h>
34
35#include <asm/arch/regs-irq.h>
36#include <asm/arch/regs-gpio.h>
37
38#include "cpu.h"
39#include "pm.h"
40#include "irq.h"
41
42/* WDT/AC97 */
43
44static void s3c_irq_demux_wdtac97(unsigned int irq,
45 struct irq_desc *desc)
46{
47 unsigned int subsrc, submsk;
48 struct irq_desc *mydesc;
49
50 /* read the current pending interrupts, and the mask
51 * for what it is available */
52
53 subsrc = __raw_readl(S3C2410_SUBSRCPND);
54 submsk = __raw_readl(S3C2410_INTSUBMSK);
55
56 subsrc &= ~submsk;
57 subsrc >>= 13;
58 subsrc &= 3;
59
60 if (subsrc != 0) {
61 if (subsrc & 1) {
62 mydesc = irq_desc + IRQ_S3C2440_WDT;
63 desc_handle_irq(IRQ_S3C2440_WDT, mydesc);
64 }
65 if (subsrc & 2) {
66 mydesc = irq_desc + IRQ_S3C2440_AC97;
67 desc_handle_irq(IRQ_S3C2440_AC97, mydesc);
68 }
69 }
70}
71
72
73#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
74
75static void
76s3c_irq_wdtac97_mask(unsigned int irqno)
77{
78 s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13);
79}
80
81static void
82s3c_irq_wdtac97_unmask(unsigned int irqno)
83{
84 s3c_irqsub_unmask(irqno, INTMSK_WDT);
85}
86
87static void
88s3c_irq_wdtac97_ack(unsigned int irqno)
89{
90 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
91}
92
93static struct irq_chip s3c_irq_wdtac97 = {
94 .mask = s3c_irq_wdtac97_mask,
95 .unmask = s3c_irq_wdtac97_unmask,
96 .ack = s3c_irq_wdtac97_ack,
97};
98
99static int s3c2440_irq_add(struct sys_device *sysdev)
100{
101 unsigned int irqno;
102
103 printk("S3C2440: IRQ Support\n");
104
105 /* add new chained handler for wdt, ac7 */
106
107 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
108 set_irq_handler(IRQ_WDT, handle_level_irq);
109 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
110
111 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
112 set_irq_chip(irqno, &s3c_irq_wdtac97);
113 set_irq_handler(irqno, handle_level_irq);
114 set_irq_flags(irqno, IRQF_VALID);
115 }
116
117 return 0;
118}
119
120static struct sysdev_driver s3c2440_irq_driver = {
121 .add = s3c2440_irq_add,
122};
123
124static int s3c2440_irq_init(void)
125{
126 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
127}
128
129arch_initcall(s3c2440_irq_init);
130
diff --git a/arch/arm/mach-s3c2410/s3c2440.c b/arch/arm/mach-s3c2410/s3c2440.c
deleted file mode 100644
index 344eb27cca48..000000000000
--- a/arch/arm/mach-s3c2410/s3c2440.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 Mobile CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/serial_core.h>
21#include <linux/sysdev.h>
22#include <linux/clk.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <asm/hardware.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31
32#include "s3c2440.h"
33#include "devs.h"
34#include "cpu.h"
35
36static struct sys_device s3c2440_sysdev = {
37 .cls = &s3c2440_sysclass,
38};
39
40int __init s3c2440_init(void)
41{
42 printk("S3C2440: Initialising architecture\n");
43
44 /* change irq for watchdog */
45
46 s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
47 s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT;
48
49 /* register our system device for everything else */
50
51 return sysdev_register(&s3c2440_sysdev);
52}
diff --git a/arch/arm/mach-s3c2410/s3c2440.h b/arch/arm/mach-s3c2410/s3c2440.h
deleted file mode 100644
index dcd316076c59..000000000000
--- a/arch/arm/mach-s3c2410/s3c2440.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* arch/arm/mach-s3c2410/s3c2440.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2440 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2440
14extern int s3c2440_init(void);
15#else
16#define s3c2440_init NULL
17#endif
diff --git a/arch/arm/mach-s3c2410/s3c2442-clock.c b/arch/arm/mach-s3c2410/s3c2442-clock.c
deleted file mode 100644
index 4e292ca7c9be..000000000000
--- a/arch/arm/mach-s3c2410/s3c2442-clock.c
+++ /dev/null
@@ -1,171 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2442-clock.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2442 Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/mutex.h>
35#include <linux/clk.h>
36
37#include <asm/hardware.h>
38#include <asm/atomic.h>
39#include <asm/irq.h>
40#include <asm/io.h>
41
42#include <asm/arch/regs-clock.h>
43
44#include "clock.h"
45#include "cpu.h"
46
47/* S3C2442 extended clock support */
48
49static unsigned long s3c2442_camif_upll_round(struct clk *clk,
50 unsigned long rate)
51{
52 unsigned long parent_rate = clk_get_rate(clk->parent);
53 int div;
54
55 if (rate > parent_rate)
56 return parent_rate;
57
58 div = parent_rate / rate;
59
60 if (div == 3)
61 return parent_rate / 3;
62
63 /* note, we remove the +/- 1 calculations for the divisor */
64
65 div /= 2;
66
67 if (div < 1)
68 div = 1;
69 else if (div > 16)
70 div = 16;
71
72 return parent_rate / (div * 2);
73}
74
75static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
76{
77 unsigned long parent_rate = clk_get_rate(clk->parent);
78 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
79
80 rate = s3c2442_camif_upll_round(clk, rate);
81
82 camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
83
84 if (rate == parent_rate) {
85 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
86 } else if ((parent_rate / rate) == 3) {
87 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
88 camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
89 } else {
90 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
91 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
92 camdivn |= (((parent_rate / rate) / 2) - 1);
93 }
94
95 __raw_writel(camdivn, S3C2440_CAMDIVN);
96
97 return 0;
98}
99
100/* Extra S3C2442 clocks */
101
102static struct clk s3c2442_clk_cam = {
103 .name = "camif",
104 .id = -1,
105 .enable = s3c2410_clkcon_enable,
106 .ctrlbit = S3C2440_CLKCON_CAMERA,
107};
108
109static struct clk s3c2442_clk_cam_upll = {
110 .name = "camif-upll",
111 .id = -1,
112 .set_rate = s3c2442_camif_upll_setrate,
113 .round_rate = s3c2442_camif_upll_round,
114};
115
116static int s3c2442_clk_add(struct sys_device *sysdev)
117{
118 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
119 unsigned long clkdivn;
120 struct clk *clock_h;
121 struct clk *clock_p;
122 struct clk *clock_upll;
123
124 printk("S3C2442: Clock Support, DVS %s\n",
125 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
126
127 clock_p = clk_get(NULL, "pclk");
128 clock_h = clk_get(NULL, "hclk");
129 clock_upll = clk_get(NULL, "upll");
130
131 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
132 printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
133 return -EINVAL;
134 }
135
136 /* check rate of UPLL, and if it is near 96MHz, then change
137 * to using half the UPLL rate for the system */
138
139 if (clk_get_rate(clock_upll) > (94 * MHZ)) {
140 clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
141
142 mutex_lock(&clocks_mutex);
143
144 clkdivn = __raw_readl(S3C2410_CLKDIVN);
145 clkdivn |= S3C2440_CLKDIVN_UCLK;
146 __raw_writel(clkdivn, S3C2410_CLKDIVN);
147
148 mutex_unlock(&clocks_mutex);
149 }
150
151 s3c2442_clk_cam.parent = clock_h;
152 s3c2442_clk_cam_upll.parent = clock_upll;
153
154 s3c24xx_register_clock(&s3c2442_clk_cam);
155 s3c24xx_register_clock(&s3c2442_clk_cam_upll);
156
157 clk_disable(&s3c2442_clk_cam);
158
159 return 0;
160}
161
162static struct sysdev_driver s3c2442_clk_driver = {
163 .add = s3c2442_clk_add,
164};
165
166static __init int s3c2442_clk_init(void)
167{
168 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
169}
170
171arch_initcall(s3c2442_clk_init);
diff --git a/arch/arm/mach-s3c2410/s3c2442.c b/arch/arm/mach-s3c2410/s3c2442.c
deleted file mode 100644
index 428732ee68c4..000000000000
--- a/arch/arm/mach-s3c2410/s3c2442.c
+++ /dev/null
@@ -1,34 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2442.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2442 Mobile CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/serial_core.h>
20#include <linux/sysdev.h>
21
22#include "s3c2442.h"
23#include "cpu.h"
24
25static struct sys_device s3c2442_sysdev = {
26 .cls = &s3c2442_sysclass,
27};
28
29int __init s3c2442_init(void)
30{
31 printk("S3C2442: Initialising architecture\n");
32
33 return sysdev_register(&s3c2442_sysdev);
34}
diff --git a/arch/arm/mach-s3c2410/s3c2442.h b/arch/arm/mach-s3c2410/s3c2442.h
deleted file mode 100644
index 0ae37d24866c..000000000000
--- a/arch/arm/mach-s3c2410/s3c2442.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* arch/arm/mach-s3c2410/s3c2442.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2442 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2442
14extern int s3c2442_init(void);
15#else
16#define s3c2442_init NULL
17#endif
diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c
deleted file mode 100644
index ede94636a72a..000000000000
--- a/arch/arm/mach-s3c2410/s3c244x-irq.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c244x-irq.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/ptrace.h>
27#include <linux/sysdev.h>
28
29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/io.h>
32
33#include <asm/mach/irq.h>
34
35#include <asm/arch/regs-irq.h>
36#include <asm/arch/regs-gpio.h>
37
38#include "cpu.h"
39#include "pm.h"
40#include "irq.h"
41
42/* camera irq */
43
44static void s3c_irq_demux_cam(unsigned int irq,
45 struct irq_desc *desc)
46{
47 unsigned int subsrc, submsk;
48 struct irq_desc *mydesc;
49
50 /* read the current pending interrupts, and the mask
51 * for what it is available */
52
53 subsrc = __raw_readl(S3C2410_SUBSRCPND);
54 submsk = __raw_readl(S3C2410_INTSUBMSK);
55
56 subsrc &= ~submsk;
57 subsrc >>= 11;
58 subsrc &= 3;
59
60 if (subsrc != 0) {
61 if (subsrc & 1) {
62 mydesc = irq_desc + IRQ_S3C2440_CAM_C;
63 desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc);
64 }
65 if (subsrc & 2) {
66 mydesc = irq_desc + IRQ_S3C2440_CAM_P;
67 desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc);
68 }
69 }
70}
71
72#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
73
74static void
75s3c_irq_cam_mask(unsigned int irqno)
76{
77 s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
78}
79
80static void
81s3c_irq_cam_unmask(unsigned int irqno)
82{
83 s3c_irqsub_unmask(irqno, INTMSK_CAM);
84}
85
86static void
87s3c_irq_cam_ack(unsigned int irqno)
88{
89 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
90}
91
92static struct irq_chip s3c_irq_cam = {
93 .mask = s3c_irq_cam_mask,
94 .unmask = s3c_irq_cam_unmask,
95 .ack = s3c_irq_cam_ack,
96};
97
98static int s3c244x_irq_add(struct sys_device *sysdev)
99{
100 unsigned int irqno;
101
102 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
103 set_irq_handler(IRQ_NFCON, handle_level_irq);
104 set_irq_flags(IRQ_NFCON, IRQF_VALID);
105
106 /* add chained handler for camera */
107
108 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
109 set_irq_handler(IRQ_CAM, handle_level_irq);
110 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
111
112 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
113 set_irq_chip(irqno, &s3c_irq_cam);
114 set_irq_handler(irqno, handle_level_irq);
115 set_irq_flags(irqno, IRQF_VALID);
116 }
117
118 return 0;
119}
120
121static struct sysdev_driver s3c2440_irq_driver = {
122 .add = s3c244x_irq_add,
123 .suspend = s3c24xx_irq_suspend,
124 .resume = s3c24xx_irq_resume,
125};
126
127static int s3c2440_irq_init(void)
128{
129 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
130}
131
132arch_initcall(s3c2440_irq_init);
133
134static struct sysdev_driver s3c2442_irq_driver = {
135 .add = s3c244x_irq_add,
136 .suspend = s3c24xx_irq_suspend,
137 .resume = s3c24xx_irq_resume,
138};
139
140
141static int s3c2442_irq_init(void)
142{
143 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver);
144}
145
146arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/mach-s3c2410/s3c244x.c b/arch/arm/mach-s3c2410/s3c244x.c
deleted file mode 100644
index 23c7494ad10d..000000000000
--- a/arch/arm/mach-s3c2410/s3c244x.c
+++ /dev/null
@@ -1,184 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c244x.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 and S3C2442 Mobile CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/sysdev.h>
22#include <linux/clk.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <asm/hardware.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31
32#include <asm/arch/regs-clock.h>
33#include <asm/arch/regs-serial.h>
34#include <asm/arch/regs-gpio.h>
35#include <asm/arch/regs-gpioj.h>
36#include <asm/arch/regs-dsc.h>
37
38#include "s3c2410.h"
39#include "s3c2440.h"
40#include "s3c244x.h"
41#include "clock.h"
42#include "devs.h"
43#include "cpu.h"
44#include "pm.h"
45
46static struct map_desc s3c244x_iodesc[] __initdata = {
47 IODESC_ENT(CLKPWR),
48 IODESC_ENT(TIMER),
49 IODESC_ENT(WATCHDOG),
50 IODESC_ENT(LCD),
51};
52
53/* uart initialisation */
54
55void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
56{
57 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
58}
59
60void __init s3c244x_map_io(struct map_desc *mach_desc, int size)
61{
62 /* register our io-tables */
63
64 iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
65 iotable_init(mach_desc, size);
66
67 /* rename any peripherals used differing from the s3c2410 */
68
69 s3c_device_i2c.name = "s3c2440-i2c";
70 s3c_device_nand.name = "s3c2440-nand";
71 s3c_device_usbgadget.name = "s3c2440-usbgadget";
72}
73
74void __init s3c244x_init_clocks(int xtal)
75{
76 unsigned long clkdiv;
77 unsigned long camdiv;
78 unsigned long hclk, fclk, pclk;
79 int hdiv = 1;
80
81 /* now we've got our machine bits initialised, work out what
82 * clocks we've got */
83
84 fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
85
86 clkdiv = __raw_readl(S3C2410_CLKDIVN);
87 camdiv = __raw_readl(S3C2440_CAMDIVN);
88
89 /* work out clock scalings */
90
91 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
92 case S3C2440_CLKDIVN_HDIVN_1:
93 hdiv = 1;
94 break;
95
96 case S3C2440_CLKDIVN_HDIVN_2:
97 hdiv = 2;
98 break;
99
100 case S3C2440_CLKDIVN_HDIVN_4_8:
101 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
102 break;
103
104 case S3C2440_CLKDIVN_HDIVN_3_6:
105 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
106 break;
107 }
108
109 hclk = fclk / hdiv;
110 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
111
112 /* print brief summary of clocks, etc */
113
114 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
115 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
116
117 /* initialise the clocks here, to allow other things like the
118 * console to use them, and to add new ones after the initialisation
119 */
120
121 s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
122 s3c2410_baseclk_add();
123}
124
125#ifdef CONFIG_PM
126
127static struct sleep_save s3c244x_sleep[] = {
128 SAVE_ITEM(S3C2440_DSC0),
129 SAVE_ITEM(S3C2440_DSC1),
130 SAVE_ITEM(S3C2440_GPJDAT),
131 SAVE_ITEM(S3C2440_GPJCON),
132 SAVE_ITEM(S3C2440_GPJUP)
133};
134
135static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
136{
137 s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
138 return 0;
139}
140
141static int s3c244x_resume(struct sys_device *dev)
142{
143 s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
144 return 0;
145}
146
147#else
148#define s3c244x_suspend NULL
149#define s3c244x_resume NULL
150#endif
151
152/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
153
154struct sysdev_class s3c2440_sysclass = {
155 set_kset_name("s3c2440-core"),
156 .suspend = s3c244x_suspend,
157 .resume = s3c244x_resume
158};
159
160struct sysdev_class s3c2442_sysclass = {
161 set_kset_name("s3c2442-core"),
162 .suspend = s3c244x_suspend,
163 .resume = s3c244x_resume
164};
165
166/* need to register class before we actually register the device, and
167 * we also need to ensure that it has been initialised before any of the
168 * drivers even try to use it (even if not on an s3c2440 based system)
169 * as a driver which may support both 2410 and 2440 may try and use it.
170*/
171
172static int __init s3c2440_core_init(void)
173{
174 return sysdev_class_register(&s3c2440_sysclass);
175}
176
177core_initcall(s3c2440_core_init);
178
179static int __init s3c2442_core_init(void)
180{
181 return sysdev_class_register(&s3c2442_sysclass);
182}
183
184core_initcall(s3c2442_core_init);
diff --git a/arch/arm/mach-s3c2410/s3c244x.h b/arch/arm/mach-s3c2410/s3c244x.h
deleted file mode 100644
index 1488c1eb37e6..000000000000
--- a/arch/arm/mach-s3c2410/s3c244x.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/* arch/arm/mach-s3c2410/s3c244x.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C2440 and S3C2442 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
14
15extern void s3c244x_map_io(struct map_desc *mach_desc, int size);
16
17extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18
19extern void s3c244x_init_clocks(int xtal);
20
21#else
22#define s3c244x_init_clocks NULL
23#define s3c244x_init_uarts NULL
24#define s3c244x_map_io NULL
25#endif
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 2018c2e1dcc5..9179a1024588 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s3c2410/sleep.S 1/* linux/arch/arm/mach-s3c2410/s3c2410-sleep.S
2 * 2 *
3 * Copyright (c) 2004 Simtec Electronics 3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
@@ -34,126 +34,35 @@
34#include <asm/arch/regs-mem.h> 34#include <asm/arch/regs-mem.h>
35#include <asm/arch/regs-serial.h> 35#include <asm/arch/regs-serial.h>
36 36
37/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not 37 /* s3c2410_cpu_suspend
38 * reset the UART configuration, only enable if you really need this!
39*/
40//#define CONFIG_DEBUG_RESUME
41
42 .text
43
44 /* s3c2410_cpu_save
45 *
46 * save enough of the CPU state to allow us to re-start
47 * pm.c code. as we store items like the sp/lr, we will
48 * end up returning from this function when the cpu resumes
49 * so the return value is set to mark this.
50 *
51 * This arangement means we avoid having to flush the cache
52 * from this code.
53 *
54 * entry:
55 * r0 = pointer to save block
56 *
57 * exit:
58 * r0 = 0 => we stored everything
59 * 1 => resumed from sleep
60 */
61
62ENTRY(s3c2410_cpu_save)
63 stmfd sp!, { r4 - r12, lr }
64
65 @@ store co-processor registers
66
67 mrc p15, 0, r4, c15, c1, 0 @ CP access register
68 mrc p15, 0, r5, c13, c0, 0 @ PID
69 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
70 mrc p15, 0, r7, c2, c0, 0 @ translation table base address
71 mrc p15, 0, r8, c1, c0, 0 @ control register
72
73 stmia r0, { r4 - r13 }
74
75 mov r0, #0
76 ldmfd sp, { r4 - r12, pc }
77
78 @@ return to the caller, after having the MMU
79 @@ turned on, this restores the last bits from the
80 @@ stack
81resume_with_mmu:
82 mov r0, #1
83 ldmfd sp!, { r4 - r12, pc }
84
85 .ltorg
86
87 @@ the next bits sit in the .data segment, even though they
88 @@ happen to be code... the s3c2410_sleep_save_phys needs to be
89 @@ accessed by the resume code before it can restore the MMU.
90 @@ This means that the variable has to be close enough for the
91 @@ code to read it... since the .text segment needs to be RO,
92 @@ the data segment can be the only place to put this code.
93
94 .data
95
96 .global s3c2410_sleep_save_phys
97s3c2410_sleep_save_phys:
98 .word 0
99
100 /* s3c2410_cpu_resume
101 * 38 *
102 * resume code entry for bootloader to call 39 * put the cpu into sleep mode
103 *
104 * we must put this code here in the data segment as we have no
105 * other way of restoring the stack pointer after sleep, and we
106 * must not write to the code segment (code is read-only)
107 */ 40 */
108 41
109ENTRY(s3c2410_cpu_resume) 42ENTRY(s3c2410_cpu_suspend)
110 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE 43 @@ prepare cpu to sleep
111 msr cpsr_c, r0 44
112 45 ldr r4, =S3C2410_REFRESH
113 @@ load UART to allow us to print the two characters for 46 ldr r5, =S3C24XX_MISCCR
114 @@ resume debug 47 ldr r6, =S3C2410_CLKCON
115 48 ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB)
116 mov r2, #S3C24XX_PA_UART & 0xff000000 49 ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB)
117 orr r2, r2, #S3C24XX_PA_UART & 0xff000 50 ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB)
118 51
119#if 0 52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
120 /* SMDK2440 LED set */ 53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
121 mov r14, #S3C24XX_PA_GPIO 54 orr r9, r9, #S3C2410_CLKCON_POWER @ power down command
122 ldr r12, [ r14, #0x54 ] 55
123 bic r12, r12, #3<<4 56 teq pc, #0 @ first as a trial-run to load cache
124 orr r12, r12, #1<<7 57 bl s3c2410_do_sleep
125 str r12, [ r14, #0x54 ] 58 teq r0, r0 @ now do it for real
126#endif 59 b s3c2410_do_sleep @
127 60
128#ifdef CONFIG_DEBUG_RESUME 61 @@ align next bit of code to cache line
129 mov r3, #'L' 62 .align 8
130 strb r3, [ r2, #S3C2410_UTXH ] 63s3c2410_do_sleep:
1311001: 64 streq r7, [ r4 ] @ SDRAM sleep command
132 ldrb r14, [ r3, #S3C2410_UTRSTAT ] 65 streq r8, [ r5 ] @ SDRAM power-down config
133 tst r14, #S3C2410_UTRSTAT_TXE 66 streq r9, [ r6 ] @ CPU sleep
134 beq 1001b 671: beq 1b
135#endif /* CONFIG_DEBUG_RESUME */ 68 mov pc, r14
136
137 mov r1, #0
138 mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
139 mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
140
141 ldr r0, s3c2410_sleep_save_phys @ address of restore block
142 ldmia r0, { r4 - r13 }
143
144 mcr p15, 0, r4, c15, c1, 0 @ CP access register
145 mcr p15, 0, r5, c13, c0, 0 @ PID
146 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
147 mcr p15, 0, r7, c2, c0, 0 @ translation table base
148
149#ifdef CONFIG_DEBUG_RESUME
150 mov r3, #'R'
151 strb r3, [ r2, #S3C2410_UTXH ]
152#endif
153
154 ldr r2, =resume_with_mmu
155 mcr p15, 0, r8, c1, c0, 0 @ turn on MMU, etc
156 nop @ second-to-last before mmu
157 mov pc, r2 @ go back to virtual address
158
159 .ltorg
diff --git a/arch/arm/mach-s3c2410/time.c b/arch/arm/mach-s3c2410/time.c
deleted file mode 100644
index 9910bf0f2cea..000000000000
--- a/arch/arm/mach-s3c2410/time.c
+++ /dev/null
@@ -1,262 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/time.c
2 *
3 * Copyright (C) 2003-2005 Simtec Electronics
4 * Ben Dooks, <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/sched.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/err.h>
27#include <linux/clk.h>
28
29#include <asm/system.h>
30#include <asm/leds.h>
31#include <asm/mach-types.h>
32
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/arch/map.h>
36#include <asm/arch/regs-timer.h>
37#include <asm/arch/regs-irq.h>
38#include <asm/mach/time.h>
39
40#include "clock.h"
41#include "cpu.h"
42
43static unsigned long timer_startval;
44static unsigned long timer_usec_ticks;
45
46#define TIMER_USEC_SHIFT 16
47
48/* we use the shifted arithmetic to work out the ratio of timer ticks
49 * to usecs, as often the peripheral clock is not a nice even multiple
50 * of 1MHz.
51 *
52 * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
53 * for the current HZ value of 200 without producing overflows.
54 *
55 * Original patch by Dimitry Andric, updated by Ben Dooks
56*/
57
58
59/* timer_mask_usec_ticks
60 *
61 * given a clock and divisor, make the value to pass into timer_ticks_to_usec
62 * to scale the ticks into usecs
63*/
64
65static inline unsigned long
66timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
67{
68 unsigned long den = pclk / 1000;
69
70 return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
71}
72
73/* timer_ticks_to_usec
74 *
75 * convert timer ticks to usec.
76*/
77
78static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
79{
80 unsigned long res;
81
82 res = ticks * timer_usec_ticks;
83 res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */
84
85 return res >> TIMER_USEC_SHIFT;
86}
87
88/***
89 * Returns microsecond since last clock interrupt. Note that interrupts
90 * will have been disabled by do_gettimeoffset()
91 * IRQs are disabled before entering here from do_gettimeofday()
92 */
93
94#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
95
96static unsigned long s3c2410_gettimeoffset (void)
97{
98 unsigned long tdone;
99 unsigned long irqpend;
100 unsigned long tval;
101
102 /* work out how many ticks have gone since last timer interrupt */
103
104 tval = __raw_readl(S3C2410_TCNTO(4));
105 tdone = timer_startval - tval;
106
107 /* check to see if there is an interrupt pending */
108
109 irqpend = __raw_readl(S3C2410_SRCPND);
110 if (irqpend & SRCPND_TIMER4) {
111 /* re-read the timer, and try and fix up for the missed
112 * interrupt. Note, the interrupt may go off before the
113 * timer has re-loaded from wrapping.
114 */
115
116 tval = __raw_readl(S3C2410_TCNTO(4));
117 tdone = timer_startval - tval;
118
119 if (tval != 0)
120 tdone += timer_startval;
121 }
122
123 return timer_ticks_to_usec(tdone);
124}
125
126
127/*
128 * IRQ handler for the timer
129 */
130static irqreturn_t
131s3c2410_timer_interrupt(int irq, void *dev_id)
132{
133 write_seqlock(&xtime_lock);
134 timer_tick();
135 write_sequnlock(&xtime_lock);
136 return IRQ_HANDLED;
137}
138
139static struct irqaction s3c2410_timer_irq = {
140 .name = "S3C2410 Timer Tick",
141 .flags = IRQF_DISABLED | IRQF_TIMER,
142 .handler = s3c2410_timer_interrupt,
143};
144
145#define use_tclk1_12() ( \
146 machine_is_bast() || \
147 machine_is_vr1000() || \
148 machine_is_anubis() || \
149 machine_is_osiris() )
150
151/*
152 * Set up timer interrupt, and return the current time in seconds.
153 *
154 * Currently we only use timer4, as it is the only timer which has no
155 * other function that can be exploited externally
156 */
157static void s3c2410_timer_setup (void)
158{
159 unsigned long tcon;
160 unsigned long tcnt;
161 unsigned long tcfg1;
162 unsigned long tcfg0;
163
164 tcnt = 0xffff; /* default value for tcnt */
165
166 /* read the current timer configuration bits */
167
168 tcon = __raw_readl(S3C2410_TCON);
169 tcfg1 = __raw_readl(S3C2410_TCFG1);
170 tcfg0 = __raw_readl(S3C2410_TCFG0);
171
172 /* configure the system for whichever machine is in use */
173
174 if (use_tclk1_12()) {
175 /* timer is at 12MHz, scaler is 1 */
176 timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
177 tcnt = 12000000 / HZ;
178
179 tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
180 tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
181 } else {
182 unsigned long pclk;
183 struct clk *clk;
184
185 /* for the h1940 (and others), we use the pclk from the core
186 * to generate the timer values. since values around 50 to
187 * 70MHz are not values we can directly generate the timer
188 * value from, we need to pre-scale and divide before using it.
189 *
190 * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
191 * (8.45 ticks per usec)
192 */
193
194 /* this is used as default if no other timer can be found */
195
196 clk = clk_get(NULL, "timers");
197 if (IS_ERR(clk))
198 panic("failed to get clock for system timer");
199
200 clk_enable(clk);
201
202 pclk = clk_get_rate(clk);
203
204 /* configure clock tick */
205
206 timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
207
208 tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
209 tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
210
211 tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
212 tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
213
214 tcnt = (pclk / 6) / HZ;
215 }
216
217 /* timers reload after counting zero, so reduce the count by 1 */
218
219 tcnt--;
220
221 printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
222 tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
223
224 /* check to see if timer is within 16bit range... */
225 if (tcnt > 0xffff) {
226 panic("setup_timer: HZ is too small, cannot configure timer!");
227 return;
228 }
229
230 __raw_writel(tcfg1, S3C2410_TCFG1);
231 __raw_writel(tcfg0, S3C2410_TCFG0);
232
233 timer_startval = tcnt;
234 __raw_writel(tcnt, S3C2410_TCNTB(4));
235
236 /* ensure timer is stopped... */
237
238 tcon &= ~(7<<20);
239 tcon |= S3C2410_TCON_T4RELOAD;
240 tcon |= S3C2410_TCON_T4MANUALUPD;
241
242 __raw_writel(tcon, S3C2410_TCON);
243 __raw_writel(tcnt, S3C2410_TCNTB(4));
244 __raw_writel(tcnt, S3C2410_TCMPB(4));
245
246 /* start the timer running */
247 tcon |= S3C2410_TCON_T4START;
248 tcon &= ~S3C2410_TCON_T4MANUALUPD;
249 __raw_writel(tcon, S3C2410_TCON);
250}
251
252static void __init s3c2410_timer_init (void)
253{
254 s3c2410_timer_setup();
255 setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
256}
257
258struct sys_timer s3c24xx_timer = {
259 .init = s3c2410_timer_init,
260 .offset = s3c2410_gettimeoffset,
261 .resume = s3c2410_timer_setup
262};
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 22b0e1cdd4bf..bcd562ac1d3d 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -35,7 +35,7 @@
35#include <asm/io.h> 35#include <asm/io.h>
36#include <asm/irq.h> 36#include <asm/irq.h>
37 37
38#include "devs.h" 38#include <asm/plat-s3c24xx/devs.h>
39#include "usb-simtec.h" 39#include "usb-simtec.h"
40 40
41/* control power and monitor over-current events on various Simtec 41/* control power and monitor over-current events on various Simtec
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 22:48:59 -0500