diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-11-23 06:41:32 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-11-30 07:24:47 -0500 |
commit | 10dd5ce28d78e2440e8fa1135d17e33399d75340 (patch) | |
tree | d2e76765a57e7e47a9c424f99c3a22bf99c6da64 /arch/arm/mach-s3c2410 | |
parent | 127e477e0cd8da4d3058709ab2dc7b92dccbcba5 (diff) |
[ARM] Remove compatibility layer for ARM irqs
set_irq_chipdata -> set_irq_chip_data
get_irq_chipdata -> get_irq_chip_data
do_level_IRQ -> handle_level_irq
do_edge_IRQ -> handle_edge_irq
do_simple_IRQ -> handle_simple_irq
irqdesc -> irq_desc
irqchip -> irq_chip
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r-- | arch/arm/mach-s3c2410/bast-irq.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-s3c2410/irq.c | 48 | ||||
-rw-r--r-- | arch/arm/mach-s3c2410/irq.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-s3c2410/s3c2412-irq.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-s3c2410/s3c2440-irq.c | 10 | ||||
-rw-r--r-- | arch/arm/mach-s3c2410/s3c244x-irq.c | 12 |
6 files changed, 42 insertions, 42 deletions
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index 23d5beea5568..379efe70778c 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c | |||
@@ -88,7 +88,7 @@ bast_pc104_mask(unsigned int irqno) | |||
88 | static void | 88 | static void |
89 | bast_pc104_maskack(unsigned int irqno) | 89 | bast_pc104_maskack(unsigned int irqno) |
90 | { | 90 | { |
91 | struct irqdesc *desc = irq_desc + IRQ_ISA; | 91 | struct irq_desc *desc = irq_desc + IRQ_ISA; |
92 | 92 | ||
93 | bast_pc104_mask(irqno); | 93 | bast_pc104_mask(irqno); |
94 | desc->chip->ack(IRQ_ISA); | 94 | desc->chip->ack(IRQ_ISA); |
@@ -104,7 +104,7 @@ bast_pc104_unmask(unsigned int irqno) | |||
104 | __raw_writeb(temp, BAST_VA_PC104_IRQMASK); | 104 | __raw_writeb(temp, BAST_VA_PC104_IRQMASK); |
105 | } | 105 | } |
106 | 106 | ||
107 | static struct irqchip bast_pc104_chip = { | 107 | static struct irq_chip bast_pc104_chip = { |
108 | .mask = bast_pc104_mask, | 108 | .mask = bast_pc104_mask, |
109 | .unmask = bast_pc104_unmask, | 109 | .unmask = bast_pc104_unmask, |
110 | .ack = bast_pc104_maskack | 110 | .ack = bast_pc104_maskack |
@@ -112,7 +112,7 @@ static struct irqchip bast_pc104_chip = { | |||
112 | 112 | ||
113 | static void | 113 | static void |
114 | bast_irq_pc104_demux(unsigned int irq, | 114 | bast_irq_pc104_demux(unsigned int irq, |
115 | struct irqdesc *desc) | 115 | struct irq_desc *desc) |
116 | { | 116 | { |
117 | unsigned int stat; | 117 | unsigned int stat; |
118 | unsigned int irqno; | 118 | unsigned int irqno; |
@@ -157,7 +157,7 @@ static __init int bast_irq_init(void) | |||
157 | unsigned int irqno = bast_pc104_irqs[i]; | 157 | unsigned int irqno = bast_pc104_irqs[i]; |
158 | 158 | ||
159 | set_irq_chip(irqno, &bast_pc104_chip); | 159 | set_irq_chip(irqno, &bast_pc104_chip); |
160 | set_irq_handler(irqno, do_level_IRQ); | 160 | set_irq_handler(irqno, handle_level_irq); |
161 | set_irq_flags(irqno, IRQF_VALID); | 161 | set_irq_flags(irqno, IRQF_VALID); |
162 | } | 162 | } |
163 | } | 163 | } |
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 683b3491ba3c..e7d2ad96ae68 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c | |||
@@ -180,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno) | |||
180 | __raw_writel(mask, S3C2410_INTMSK); | 180 | __raw_writel(mask, S3C2410_INTMSK); |
181 | } | 181 | } |
182 | 182 | ||
183 | struct irqchip s3c_irq_level_chip = { | 183 | struct irq_chip s3c_irq_level_chip = { |
184 | .name = "s3c-level", | 184 | .name = "s3c-level", |
185 | .ack = s3c_irq_maskack, | 185 | .ack = s3c_irq_maskack, |
186 | .mask = s3c_irq_mask, | 186 | .mask = s3c_irq_mask, |
@@ -188,7 +188,7 @@ struct irqchip s3c_irq_level_chip = { | |||
188 | .set_wake = s3c_irq_wake | 188 | .set_wake = s3c_irq_wake |
189 | }; | 189 | }; |
190 | 190 | ||
191 | static struct irqchip s3c_irq_chip = { | 191 | static struct irq_chip s3c_irq_chip = { |
192 | .name = "s3c", | 192 | .name = "s3c", |
193 | .ack = s3c_irq_ack, | 193 | .ack = s3c_irq_ack, |
194 | .mask = s3c_irq_mask, | 194 | .mask = s3c_irq_mask, |
@@ -344,7 +344,7 @@ s3c_irqext_type(unsigned int irq, unsigned int type) | |||
344 | return 0; | 344 | return 0; |
345 | } | 345 | } |
346 | 346 | ||
347 | static struct irqchip s3c_irqext_chip = { | 347 | static struct irq_chip s3c_irqext_chip = { |
348 | .name = "s3c-ext", | 348 | .name = "s3c-ext", |
349 | .mask = s3c_irqext_mask, | 349 | .mask = s3c_irqext_mask, |
350 | .unmask = s3c_irqext_unmask, | 350 | .unmask = s3c_irqext_unmask, |
@@ -353,7 +353,7 @@ static struct irqchip s3c_irqext_chip = { | |||
353 | .set_wake = s3c_irqext_wake | 353 | .set_wake = s3c_irqext_wake |
354 | }; | 354 | }; |
355 | 355 | ||
356 | static struct irqchip s3c_irq_eint0t4 = { | 356 | static struct irq_chip s3c_irq_eint0t4 = { |
357 | .name = "s3c-ext0", | 357 | .name = "s3c-ext0", |
358 | .ack = s3c_irq_ack, | 358 | .ack = s3c_irq_ack, |
359 | .mask = s3c_irq_mask, | 359 | .mask = s3c_irq_mask, |
@@ -390,7 +390,7 @@ s3c_irq_uart0_ack(unsigned int irqno) | |||
390 | s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); | 390 | s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); |
391 | } | 391 | } |
392 | 392 | ||
393 | static struct irqchip s3c_irq_uart0 = { | 393 | static struct irq_chip s3c_irq_uart0 = { |
394 | .name = "s3c-uart0", | 394 | .name = "s3c-uart0", |
395 | .mask = s3c_irq_uart0_mask, | 395 | .mask = s3c_irq_uart0_mask, |
396 | .unmask = s3c_irq_uart0_unmask, | 396 | .unmask = s3c_irq_uart0_unmask, |
@@ -417,7 +417,7 @@ s3c_irq_uart1_ack(unsigned int irqno) | |||
417 | s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); | 417 | s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); |
418 | } | 418 | } |
419 | 419 | ||
420 | static struct irqchip s3c_irq_uart1 = { | 420 | static struct irq_chip s3c_irq_uart1 = { |
421 | .name = "s3c-uart1", | 421 | .name = "s3c-uart1", |
422 | .mask = s3c_irq_uart1_mask, | 422 | .mask = s3c_irq_uart1_mask, |
423 | .unmask = s3c_irq_uart1_unmask, | 423 | .unmask = s3c_irq_uart1_unmask, |
@@ -444,7 +444,7 @@ s3c_irq_uart2_ack(unsigned int irqno) | |||
444 | s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); | 444 | s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); |
445 | } | 445 | } |
446 | 446 | ||
447 | static struct irqchip s3c_irq_uart2 = { | 447 | static struct irq_chip s3c_irq_uart2 = { |
448 | .name = "s3c-uart2", | 448 | .name = "s3c-uart2", |
449 | .mask = s3c_irq_uart2_mask, | 449 | .mask = s3c_irq_uart2_mask, |
450 | .unmask = s3c_irq_uart2_unmask, | 450 | .unmask = s3c_irq_uart2_unmask, |
@@ -471,7 +471,7 @@ s3c_irq_adc_ack(unsigned int irqno) | |||
471 | s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); | 471 | s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); |
472 | } | 472 | } |
473 | 473 | ||
474 | static struct irqchip s3c_irq_adc = { | 474 | static struct irq_chip s3c_irq_adc = { |
475 | .name = "s3c-adc", | 475 | .name = "s3c-adc", |
476 | .mask = s3c_irq_adc_mask, | 476 | .mask = s3c_irq_adc_mask, |
477 | .unmask = s3c_irq_adc_unmask, | 477 | .unmask = s3c_irq_adc_unmask, |
@@ -480,11 +480,11 @@ static struct irqchip s3c_irq_adc = { | |||
480 | 480 | ||
481 | /* irq demux for adc */ | 481 | /* irq demux for adc */ |
482 | static void s3c_irq_demux_adc(unsigned int irq, | 482 | static void s3c_irq_demux_adc(unsigned int irq, |
483 | struct irqdesc *desc) | 483 | struct irq_desc *desc) |
484 | { | 484 | { |
485 | unsigned int subsrc, submsk; | 485 | unsigned int subsrc, submsk; |
486 | unsigned int offset = 9; | 486 | unsigned int offset = 9; |
487 | struct irqdesc *mydesc; | 487 | struct irq_desc *mydesc; |
488 | 488 | ||
489 | /* read the current pending interrupts, and the mask | 489 | /* read the current pending interrupts, and the mask |
490 | * for what it is available */ | 490 | * for what it is available */ |
@@ -512,7 +512,7 @@ static void s3c_irq_demux_uart(unsigned int start) | |||
512 | { | 512 | { |
513 | unsigned int subsrc, submsk; | 513 | unsigned int subsrc, submsk; |
514 | unsigned int offset = start - IRQ_S3CUART_RX0; | 514 | unsigned int offset = start - IRQ_S3CUART_RX0; |
515 | struct irqdesc *desc; | 515 | struct irq_desc *desc; |
516 | 516 | ||
517 | /* read the current pending interrupts, and the mask | 517 | /* read the current pending interrupts, and the mask |
518 | * for what it is available */ | 518 | * for what it is available */ |
@@ -549,7 +549,7 @@ static void s3c_irq_demux_uart(unsigned int start) | |||
549 | 549 | ||
550 | static void | 550 | static void |
551 | s3c_irq_demux_uart0(unsigned int irq, | 551 | s3c_irq_demux_uart0(unsigned int irq, |
552 | struct irqdesc *desc) | 552 | struct irq_desc *desc) |
553 | { | 553 | { |
554 | irq = irq; | 554 | irq = irq; |
555 | s3c_irq_demux_uart(IRQ_S3CUART_RX0); | 555 | s3c_irq_demux_uart(IRQ_S3CUART_RX0); |
@@ -557,7 +557,7 @@ s3c_irq_demux_uart0(unsigned int irq, | |||
557 | 557 | ||
558 | static void | 558 | static void |
559 | s3c_irq_demux_uart1(unsigned int irq, | 559 | s3c_irq_demux_uart1(unsigned int irq, |
560 | struct irqdesc *desc) | 560 | struct irq_desc *desc) |
561 | { | 561 | { |
562 | irq = irq; | 562 | irq = irq; |
563 | s3c_irq_demux_uart(IRQ_S3CUART_RX1); | 563 | s3c_irq_demux_uart(IRQ_S3CUART_RX1); |
@@ -565,7 +565,7 @@ s3c_irq_demux_uart1(unsigned int irq, | |||
565 | 565 | ||
566 | static void | 566 | static void |
567 | s3c_irq_demux_uart2(unsigned int irq, | 567 | s3c_irq_demux_uart2(unsigned int irq, |
568 | struct irqdesc *desc) | 568 | struct irq_desc *desc) |
569 | { | 569 | { |
570 | irq = irq; | 570 | irq = irq; |
571 | s3c_irq_demux_uart(IRQ_S3CUART_RX2); | 571 | s3c_irq_demux_uart(IRQ_S3CUART_RX2); |
@@ -573,7 +573,7 @@ s3c_irq_demux_uart2(unsigned int irq, | |||
573 | 573 | ||
574 | static void | 574 | static void |
575 | s3c_irq_demux_extint8(unsigned int irq, | 575 | s3c_irq_demux_extint8(unsigned int irq, |
576 | struct irqdesc *desc) | 576 | struct irq_desc *desc) |
577 | { | 577 | { |
578 | unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); | 578 | unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); |
579 | unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); | 579 | unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); |
@@ -595,7 +595,7 @@ s3c_irq_demux_extint8(unsigned int irq, | |||
595 | 595 | ||
596 | static void | 596 | static void |
597 | s3c_irq_demux_extint4t7(unsigned int irq, | 597 | s3c_irq_demux_extint4t7(unsigned int irq, |
598 | struct irqdesc *desc) | 598 | struct irq_desc *desc) |
599 | { | 599 | { |
600 | unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); | 600 | unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); |
601 | unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); | 601 | unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); |
@@ -738,7 +738,7 @@ void __init s3c24xx_init_irq(void) | |||
738 | case IRQ_UART2: | 738 | case IRQ_UART2: |
739 | case IRQ_ADCPARENT: | 739 | case IRQ_ADCPARENT: |
740 | set_irq_chip(irqno, &s3c_irq_level_chip); | 740 | set_irq_chip(irqno, &s3c_irq_level_chip); |
741 | set_irq_handler(irqno, do_level_IRQ); | 741 | set_irq_handler(irqno, handle_level_irq); |
742 | break; | 742 | break; |
743 | 743 | ||
744 | case IRQ_RESERVED6: | 744 | case IRQ_RESERVED6: |
@@ -749,7 +749,7 @@ void __init s3c24xx_init_irq(void) | |||
749 | default: | 749 | default: |
750 | //irqdbf("registering irq %d (s3c irq)\n", irqno); | 750 | //irqdbf("registering irq %d (s3c irq)\n", irqno); |
751 | set_irq_chip(irqno, &s3c_irq_chip); | 751 | set_irq_chip(irqno, &s3c_irq_chip); |
752 | set_irq_handler(irqno, do_edge_IRQ); | 752 | set_irq_handler(irqno, handle_edge_irq); |
753 | set_irq_flags(irqno, IRQF_VALID); | 753 | set_irq_flags(irqno, IRQF_VALID); |
754 | } | 754 | } |
755 | } | 755 | } |
@@ -769,14 +769,14 @@ void __init s3c24xx_init_irq(void) | |||
769 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { | 769 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { |
770 | irqdbf("registering irq %d (ext int)\n", irqno); | 770 | irqdbf("registering irq %d (ext int)\n", irqno); |
771 | set_irq_chip(irqno, &s3c_irq_eint0t4); | 771 | set_irq_chip(irqno, &s3c_irq_eint0t4); |
772 | set_irq_handler(irqno, do_edge_IRQ); | 772 | set_irq_handler(irqno, handle_edge_irq); |
773 | set_irq_flags(irqno, IRQF_VALID); | 773 | set_irq_flags(irqno, IRQF_VALID); |
774 | } | 774 | } |
775 | 775 | ||
776 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { | 776 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { |
777 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); | 777 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); |
778 | set_irq_chip(irqno, &s3c_irqext_chip); | 778 | set_irq_chip(irqno, &s3c_irqext_chip); |
779 | set_irq_handler(irqno, do_edge_IRQ); | 779 | set_irq_handler(irqno, handle_edge_irq); |
780 | set_irq_flags(irqno, IRQF_VALID); | 780 | set_irq_flags(irqno, IRQF_VALID); |
781 | } | 781 | } |
782 | 782 | ||
@@ -787,28 +787,28 @@ void __init s3c24xx_init_irq(void) | |||
787 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { | 787 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { |
788 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); | 788 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); |
789 | set_irq_chip(irqno, &s3c_irq_uart0); | 789 | set_irq_chip(irqno, &s3c_irq_uart0); |
790 | set_irq_handler(irqno, do_level_IRQ); | 790 | set_irq_handler(irqno, handle_level_irq); |
791 | set_irq_flags(irqno, IRQF_VALID); | 791 | set_irq_flags(irqno, IRQF_VALID); |
792 | } | 792 | } |
793 | 793 | ||
794 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { | 794 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { |
795 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); | 795 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); |
796 | set_irq_chip(irqno, &s3c_irq_uart1); | 796 | set_irq_chip(irqno, &s3c_irq_uart1); |
797 | set_irq_handler(irqno, do_level_IRQ); | 797 | set_irq_handler(irqno, handle_level_irq); |
798 | set_irq_flags(irqno, IRQF_VALID); | 798 | set_irq_flags(irqno, IRQF_VALID); |
799 | } | 799 | } |
800 | 800 | ||
801 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { | 801 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { |
802 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); | 802 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); |
803 | set_irq_chip(irqno, &s3c_irq_uart2); | 803 | set_irq_chip(irqno, &s3c_irq_uart2); |
804 | set_irq_handler(irqno, do_level_IRQ); | 804 | set_irq_handler(irqno, handle_level_irq); |
805 | set_irq_flags(irqno, IRQF_VALID); | 805 | set_irq_flags(irqno, IRQF_VALID); |
806 | } | 806 | } |
807 | 807 | ||
808 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { | 808 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { |
809 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); | 809 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); |
810 | set_irq_chip(irqno, &s3c_irq_adc); | 810 | set_irq_chip(irqno, &s3c_irq_adc); |
811 | set_irq_handler(irqno, do_edge_IRQ); | 811 | set_irq_handler(irqno, handle_edge_irq); |
812 | set_irq_flags(irqno, IRQF_VALID); | 812 | set_irq_flags(irqno, IRQF_VALID); |
813 | } | 813 | } |
814 | 814 | ||
diff --git a/arch/arm/mach-s3c2410/irq.h b/arch/arm/mach-s3c2410/irq.h index 842a9f42c97b..3686a0082245 100644 --- a/arch/arm/mach-s3c2410/irq.h +++ b/arch/arm/mach-s3c2410/irq.h | |||
@@ -17,7 +17,7 @@ | |||
17 | 17 | ||
18 | #define EXTINT_OFF (IRQ_EINT4 - 4) | 18 | #define EXTINT_OFF (IRQ_EINT4 - 4) |
19 | 19 | ||
20 | extern struct irqchip s3c_irq_level_chip; | 20 | extern struct irq_chip s3c_irq_level_chip; |
21 | 21 | ||
22 | static inline void | 22 | static inline void |
23 | s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, | 23 | s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, |
diff --git a/arch/arm/mach-s3c2410/s3c2412-irq.c b/arch/arm/mach-s3c2410/s3c2412-irq.c index 7f741547658f..ffcc30b23a80 100644 --- a/arch/arm/mach-s3c2410/s3c2412-irq.c +++ b/arch/arm/mach-s3c2410/s3c2412-irq.c | |||
@@ -98,7 +98,7 @@ s3c2412_irq_unmask(unsigned int irqno) | |||
98 | __raw_writel(mask & ~bitval, S3C2410_INTMSK); | 98 | __raw_writel(mask & ~bitval, S3C2410_INTMSK); |
99 | } | 99 | } |
100 | 100 | ||
101 | static struct irqchip s3c2412_irq_eint0t4 = { | 101 | static struct irq_chip s3c2412_irq_eint0t4 = { |
102 | .ack = s3c2412_irq_ack, | 102 | .ack = s3c2412_irq_ack, |
103 | .mask = s3c2412_irq_mask, | 103 | .mask = s3c2412_irq_mask, |
104 | .unmask = s3c2412_irq_unmask, | 104 | .unmask = s3c2412_irq_unmask, |
@@ -112,7 +112,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev) | |||
112 | 112 | ||
113 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { | 113 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { |
114 | set_irq_chip(irqno, &s3c2412_irq_eint0t4); | 114 | set_irq_chip(irqno, &s3c2412_irq_eint0t4); |
115 | set_irq_handler(irqno, do_edge_IRQ); | 115 | set_irq_handler(irqno, handle_edge_irq); |
116 | set_irq_flags(irqno, IRQF_VALID); | 116 | set_irq_flags(irqno, IRQF_VALID); |
117 | } | 117 | } |
118 | 118 | ||
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c index 39db0752d53b..1ba19b27ab05 100644 --- a/arch/arm/mach-s3c2410/s3c2440-irq.c +++ b/arch/arm/mach-s3c2410/s3c2440-irq.c | |||
@@ -42,10 +42,10 @@ | |||
42 | /* WDT/AC97 */ | 42 | /* WDT/AC97 */ |
43 | 43 | ||
44 | static void s3c_irq_demux_wdtac97(unsigned int irq, | 44 | static void s3c_irq_demux_wdtac97(unsigned int irq, |
45 | struct irqdesc *desc) | 45 | struct irq_desc *desc) |
46 | { | 46 | { |
47 | unsigned int subsrc, submsk; | 47 | unsigned int subsrc, submsk; |
48 | struct irqdesc *mydesc; | 48 | struct irq_desc *mydesc; |
49 | 49 | ||
50 | /* read the current pending interrupts, and the mask | 50 | /* read the current pending interrupts, and the mask |
51 | * for what it is available */ | 51 | * for what it is available */ |
@@ -90,7 +90,7 @@ s3c_irq_wdtac97_ack(unsigned int irqno) | |||
90 | s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13); | 90 | s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13); |
91 | } | 91 | } |
92 | 92 | ||
93 | static struct irqchip s3c_irq_wdtac97 = { | 93 | static struct irq_chip s3c_irq_wdtac97 = { |
94 | .mask = s3c_irq_wdtac97_mask, | 94 | .mask = s3c_irq_wdtac97_mask, |
95 | .unmask = s3c_irq_wdtac97_unmask, | 95 | .unmask = s3c_irq_wdtac97_unmask, |
96 | .ack = s3c_irq_wdtac97_ack, | 96 | .ack = s3c_irq_wdtac97_ack, |
@@ -105,12 +105,12 @@ static int s3c2440_irq_add(struct sys_device *sysdev) | |||
105 | /* add new chained handler for wdt, ac7 */ | 105 | /* add new chained handler for wdt, ac7 */ |
106 | 106 | ||
107 | set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); | 107 | set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); |
108 | set_irq_handler(IRQ_WDT, do_level_IRQ); | 108 | set_irq_handler(IRQ_WDT, handle_level_irq); |
109 | set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); | 109 | set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); |
110 | 110 | ||
111 | for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { | 111 | for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { |
112 | set_irq_chip(irqno, &s3c_irq_wdtac97); | 112 | set_irq_chip(irqno, &s3c_irq_wdtac97); |
113 | set_irq_handler(irqno, do_level_IRQ); | 113 | set_irq_handler(irqno, handle_level_irq); |
114 | set_irq_flags(irqno, IRQF_VALID); | 114 | set_irq_flags(irqno, IRQF_VALID); |
115 | } | 115 | } |
116 | 116 | ||
diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c index 146f2109dd90..ede94636a72a 100644 --- a/arch/arm/mach-s3c2410/s3c244x-irq.c +++ b/arch/arm/mach-s3c2410/s3c244x-irq.c | |||
@@ -42,10 +42,10 @@ | |||
42 | /* camera irq */ | 42 | /* camera irq */ |
43 | 43 | ||
44 | static void s3c_irq_demux_cam(unsigned int irq, | 44 | static void s3c_irq_demux_cam(unsigned int irq, |
45 | struct irqdesc *desc) | 45 | struct irq_desc *desc) |
46 | { | 46 | { |
47 | unsigned int subsrc, submsk; | 47 | unsigned int subsrc, submsk; |
48 | struct irqdesc *mydesc; | 48 | struct irq_desc *mydesc; |
49 | 49 | ||
50 | /* read the current pending interrupts, and the mask | 50 | /* read the current pending interrupts, and the mask |
51 | * for what it is available */ | 51 | * for what it is available */ |
@@ -89,7 +89,7 @@ s3c_irq_cam_ack(unsigned int irqno) | |||
89 | s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11); | 89 | s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11); |
90 | } | 90 | } |
91 | 91 | ||
92 | static struct irqchip s3c_irq_cam = { | 92 | static struct irq_chip s3c_irq_cam = { |
93 | .mask = s3c_irq_cam_mask, | 93 | .mask = s3c_irq_cam_mask, |
94 | .unmask = s3c_irq_cam_unmask, | 94 | .unmask = s3c_irq_cam_unmask, |
95 | .ack = s3c_irq_cam_ack, | 95 | .ack = s3c_irq_cam_ack, |
@@ -100,18 +100,18 @@ static int s3c244x_irq_add(struct sys_device *sysdev) | |||
100 | unsigned int irqno; | 100 | unsigned int irqno; |
101 | 101 | ||
102 | set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); | 102 | set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); |
103 | set_irq_handler(IRQ_NFCON, do_level_IRQ); | 103 | set_irq_handler(IRQ_NFCON, handle_level_irq); |
104 | set_irq_flags(IRQ_NFCON, IRQF_VALID); | 104 | set_irq_flags(IRQ_NFCON, IRQF_VALID); |
105 | 105 | ||
106 | /* add chained handler for camera */ | 106 | /* add chained handler for camera */ |
107 | 107 | ||
108 | set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); | 108 | set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); |
109 | set_irq_handler(IRQ_CAM, do_level_IRQ); | 109 | set_irq_handler(IRQ_CAM, handle_level_irq); |
110 | set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); | 110 | set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); |
111 | 111 | ||
112 | for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { | 112 | for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { |
113 | set_irq_chip(irqno, &s3c_irq_cam); | 113 | set_irq_chip(irqno, &s3c_irq_cam); |
114 | set_irq_handler(irqno, do_level_IRQ); | 114 | set_irq_handler(irqno, handle_level_irq); |
115 | set_irq_flags(irqno, IRQF_VALID); | 115 | set_irq_flags(irqno, IRQF_VALID); |
116 | } | 116 | } |
117 | 117 | ||