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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/arm/mach-s3c2410/sleep.S
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
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1/* linux/arch/arm/mach-s3c2410/sleep.S
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Power Manager (Suspend-To-RAM) support
7 *
8 * Based on PXA/SA1100 sleep code by:
9 * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
10 * Cliff Brake, (c) 2001
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25*/
26
27#include <linux/config.h>
28#include <linux/linkage.h>
29#include <asm/assembler.h>
30#include <asm/hardware.h>
31#include <asm/arch/map.h>
32
33#include <asm/arch/regs-gpio.h>
34#include <asm/arch/regs-clock.h>
35#include <asm/arch/regs-mem.h>
36#include <asm/arch/regs-serial.h>
37
38/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
39 * reset the UART configuration, only enable if you really need this!
40*/
41//#define CONFIG_DEBUG_RESUME
42
43 .text
44
45 /* s3c2410_cpu_suspend
46 *
47 * put the cpu into sleep mode
48 *
49 * entry:
50 * r0 = sleep save block
51 */
52
53ENTRY(s3c2410_cpu_suspend)
54 stmfd sp!, { r4 - r12, lr }
55
56 @@ store co-processor registers
57
58 mrc p15, 0, r4, c15, c1, 0 @ CP access register
59 mrc p15, 0, r5, c13, c0, 0 @ PID
60 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
61 mrc p15, 0, r7, c2, c0, 0 @ translation table base address
62 mrc p15, 0, r8, c2, c0, 0 @ auxiliary control register
63 mrc p15, 0, r9, c1, c0, 0 @ control register
64
65 stmia r0, { r4 - r13 }
66
67 @@ flush the caches to ensure everything is back out to
68 @@ SDRAM before the core powers down
69
70 bl arm920_flush_kern_cache_all
71
72 @@ prepare cpu to sleep
73
74 ldr r4, =S3C2410_REFRESH
75 ldr r5, =S3C2410_MISCCR
76 ldr r6, =S3C2410_CLKCON
77 ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB)
78 ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB)
79 ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB)
80
81 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
82 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
83 orr r9, r9, #S3C2410_CLKCON_POWER @ power down command
84
85 teq pc, #0 @ first as a trial-run to load cache
86 bl s3c2410_do_sleep
87 teq r0, r0 @ now do it for real
88 b s3c2410_do_sleep @
89
90 @@ align next bit of code to cache line
91 .align 8
92s3c2410_do_sleep:
93 streq r7, [ r4 ] @ SDRAM sleep command
94 streq r8, [ r5 ] @ SDRAM power-down config
95 streq r9, [ r6 ] @ CPU sleep
961: beq 1b
97 mov pc, r14
98
99 @@ return to the caller, after having the MMU
100 @@ turned on, this restores the last bits from the
101 @@ stack
102resume_with_mmu:
103 ldmfd sp!, { r4 - r12, pc }
104
105 .ltorg
106
107 @@ the next bits sit in the .data segment, even though they
108 @@ happen to be code... the s3c2410_sleep_save_phys needs to be
109 @@ accessed by the resume code before it can restore the MMU.
110 @@ This means that the variable has to be close enough for the
111 @@ code to read it... since the .text segment needs to be RO,
112 @@ the data segment can be the only place to put this code.
113
114 .data
115
116 .global s3c2410_sleep_save_phys
117s3c2410_sleep_save_phys:
118 .word 0
119
120 /* s3c2410_cpu_resume
121 *
122 * resume code entry for bootloader to call
123 *
124 * we must put this code here in the data segment as we have no
125 * other way of restoring the stack pointer after sleep, and we
126 * must not write to the code segment (code is read-only)
127 */
128
129ENTRY(s3c2410_cpu_resume)
130 mov r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC
131 msr cpsr_c, r0
132
133 @@ load UART to allow us to print the two characters for
134 @@ resume debug
135
136 mov r2, #S3C2410_PA_UART & 0xff000000
137 orr r2, r2, #S3C2410_PA_UART & 0xff000
138
139#if 0
140 /* SMDK2440 LED set */
141 mov r14, #S3C2410_PA_GPIO
142 ldr r12, [ r14, #0x54 ]
143 bic r12, r12, #3<<4
144 orr r12, r12, #1<<7
145 str r12, [ r14, #0x54 ]
146#endif
147
148#ifdef CONFIG_DEBUG_RESUME
149 mov r3, #'L'
150 strb r3, [ r2, #S3C2410_UTXH ]
1511001:
152 ldrb r14, [ r3, #S3C2410_UTRSTAT ]
153 tst r14, #S3C2410_UTRSTAT_TXE
154 beq 1001b
155#endif /* CONFIG_DEBUG_RESUME */
156
157 mov r1, #0
158 mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
159 mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
160
161 ldr r0, s3c2410_sleep_save_phys @ address of restore block
162 ldmia r0, { r4 - r13 }
163
164 mcr p15, 0, r4, c15, c1, 0 @ CP access register
165 mcr p15, 0, r5, c13, c0, 0 @ PID
166 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
167 mcr p15, 0, r7, c2, c0, 0 @ translation table base
168 mcr p15, 0, r8, c1, c1, 0 @ auxilliary control
169
170#ifdef CONFIG_DEBUG_RESUME
171 mov r3, #'R'
172 strb r3, [ r2, #S3C2410_UTXH ]
173#endif
174
175 ldr r2, =resume_with_mmu
176 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc
177 nop @ second-to-last before mmu
178 mov pc, r2 @ go back to virtual address
179
180 .ltorg