diff options
author | Ben Dooks <ben-linux@fluff.org> | 2006-03-20 12:10:04 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-03-21 17:06:02 -0500 |
commit | 8e40a2f91c6e73726a75381e4438478eb5964cb7 (patch) | |
tree | b0b66666c84151a2c382e189e2fbcc619d1edfb0 /arch/arm/mach-s3c2410/s3c2440-clock.c | |
parent | 766636cc3630ae3b9827e7b4b1f566572963f1ef (diff) |
[ARM] 3330/1: S3C24XX - move UPLL to main clock
Patch from Ben Dooks
Move the UPLL clock registration to the central
clock file, and add an enable method
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410/s3c2440-clock.c')
-rw-r--r-- | arch/arm/mach-s3c2410/s3c2440-clock.c | 19 |
1 files changed, 1 insertions, 18 deletions
diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c b/arch/arm/mach-s3c2410/s3c2440-clock.c index b557a2be8a01..2d0fa03a257a 100644 --- a/arch/arm/mach-s3c2410/s3c2440-clock.c +++ b/arch/arm/mach-s3c2410/s3c2440-clock.c | |||
@@ -45,11 +45,6 @@ | |||
45 | 45 | ||
46 | /* S3C2440 extended clock support */ | 46 | /* S3C2440 extended clock support */ |
47 | 47 | ||
48 | static struct clk s3c2440_clk_upll = { | ||
49 | .name = "upll", | ||
50 | .id = -1, | ||
51 | }; | ||
52 | |||
53 | static struct clk s3c2440_clk_cam = { | 48 | static struct clk s3c2440_clk_cam = { |
54 | .name = "camif", | 49 | .name = "camif", |
55 | .id = -1, | 50 | .id = -1, |
@@ -66,22 +61,11 @@ static struct clk s3c2440_clk_ac97 = { | |||
66 | 61 | ||
67 | static int s3c2440_clk_add(struct sys_device *sysdev) | 62 | static int s3c2440_clk_add(struct sys_device *sysdev) |
68 | { | 63 | { |
69 | unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); | ||
70 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); | 64 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); |
71 | struct clk *clk_h; | 65 | struct clk *clk_h; |
72 | struct clk *clk_p; | 66 | struct clk *clk_p; |
73 | struct clk *clk_xtal; | ||
74 | |||
75 | clk_xtal = clk_get(NULL, "xtal"); | ||
76 | if (IS_ERR(clk_xtal)) { | ||
77 | printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n"); | ||
78 | return -EINVAL; | ||
79 | } | ||
80 | |||
81 | s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate); | ||
82 | 67 | ||
83 | printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n", | 68 | printk("S3C2440: Clock Support, DVS %s\n", |
84 | print_mhz(s3c2440_clk_upll.rate), | ||
85 | (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); | 69 | (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); |
86 | 70 | ||
87 | clk_p = clk_get(NULL, "pclk"); | 71 | clk_p = clk_get(NULL, "pclk"); |
@@ -97,7 +81,6 @@ static int s3c2440_clk_add(struct sys_device *sysdev) | |||
97 | 81 | ||
98 | s3c24xx_register_clock(&s3c2440_clk_ac97); | 82 | s3c24xx_register_clock(&s3c2440_clk_ac97); |
99 | s3c24xx_register_clock(&s3c2440_clk_cam); | 83 | s3c24xx_register_clock(&s3c2440_clk_cam); |
100 | s3c24xx_register_clock(&s3c2440_clk_upll); | ||
101 | 84 | ||
102 | clk_disable(&s3c2440_clk_ac97); | 85 | clk_disable(&s3c2440_clk_ac97); |
103 | clk_disable(&s3c2440_clk_cam); | 86 | clk_disable(&s3c2440_clk_cam); |