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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/arm/mach-s3c2410/pm.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/arm/mach-s3c2410/pm.c')
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1 files changed, 672 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
new file mode 100644
index 000000000000..13a48ee77484
--- /dev/null
+++ b/arch/arm/mach-s3c2410/pm.c
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1/* linux/arch/arm/mach-s3c2410/pm.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Power Manager (Suspend-To-RAM) support
7 *
8 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * Parts based on arch/arm/mach-pxa/pm.c
25 *
26 * Thanks to Dimitry Andric for debugging
27 *
28 * Modifications:
29 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
30*/
31
32#include <linux/config.h>
33#include <linux/init.h>
34#include <linux/suspend.h>
35#include <linux/errno.h>
36#include <linux/time.h>
37#include <linux/interrupt.h>
38#include <linux/crc32.h>
39#include <linux/ioport.h>
40#include <linux/delay.h>
41
42#include <asm/hardware.h>
43#include <asm/io.h>
44
45#include <asm/arch/regs-serial.h>
46#include <asm/arch/regs-clock.h>
47#include <asm/arch/regs-gpio.h>
48#include <asm/arch/regs-mem.h>
49#include <asm/arch/regs-irq.h>
50
51#include <asm/mach/time.h>
52
53#include "pm.h"
54
55/* for external use */
56
57unsigned long s3c_pm_flags;
58
59/* cache functions from arch/arm/mm/proc-arm920.S */
60
61extern void arm920_flush_kern_cache_all(void);
62
63#define PFX "s3c24xx-pm: "
64
65static struct sleep_save core_save[] = {
66 SAVE_ITEM(S3C2410_LOCKTIME),
67 SAVE_ITEM(S3C2410_CLKCON),
68
69 /* we restore the timings here, with the proviso that the board
70 * brings the system up in an slower, or equal frequency setting
71 * to the original system.
72 *
73 * if we cannot guarantee this, then things are going to go very
74 * wrong here, as we modify the refresh and both pll settings.
75 */
76
77 SAVE_ITEM(S3C2410_BWSCON),
78 SAVE_ITEM(S3C2410_BANKCON0),
79 SAVE_ITEM(S3C2410_BANKCON1),
80 SAVE_ITEM(S3C2410_BANKCON2),
81 SAVE_ITEM(S3C2410_BANKCON3),
82 SAVE_ITEM(S3C2410_BANKCON4),
83 SAVE_ITEM(S3C2410_BANKCON5),
84
85 SAVE_ITEM(S3C2410_CLKDIVN),
86 SAVE_ITEM(S3C2410_MPLLCON),
87 SAVE_ITEM(S3C2410_UPLLCON),
88 SAVE_ITEM(S3C2410_CLKSLOW),
89 SAVE_ITEM(S3C2410_REFRESH),
90};
91
92/* this lot should be really saved by the IRQ code */
93static struct sleep_save irq_save[] = {
94 SAVE_ITEM(S3C2410_EXTINT0),
95 SAVE_ITEM(S3C2410_EXTINT1),
96 SAVE_ITEM(S3C2410_EXTINT2),
97 SAVE_ITEM(S3C2410_EINFLT0),
98 SAVE_ITEM(S3C2410_EINFLT1),
99 SAVE_ITEM(S3C2410_EINFLT2),
100 SAVE_ITEM(S3C2410_EINFLT3),
101 SAVE_ITEM(S3C2410_EINTMASK),
102 SAVE_ITEM(S3C2410_INTMSK)
103};
104
105static struct sleep_save gpio_save[] = {
106 SAVE_ITEM(S3C2410_GPACON),
107 SAVE_ITEM(S3C2410_GPADAT),
108
109 SAVE_ITEM(S3C2410_GPBCON),
110 SAVE_ITEM(S3C2410_GPBDAT),
111 SAVE_ITEM(S3C2410_GPBUP),
112
113 SAVE_ITEM(S3C2410_GPCCON),
114 SAVE_ITEM(S3C2410_GPCDAT),
115 SAVE_ITEM(S3C2410_GPCUP),
116
117 SAVE_ITEM(S3C2410_GPDCON),
118 SAVE_ITEM(S3C2410_GPDDAT),
119 SAVE_ITEM(S3C2410_GPDUP),
120
121 SAVE_ITEM(S3C2410_GPECON),
122 SAVE_ITEM(S3C2410_GPEDAT),
123 SAVE_ITEM(S3C2410_GPEUP),
124
125 SAVE_ITEM(S3C2410_GPFCON),
126 SAVE_ITEM(S3C2410_GPFDAT),
127 SAVE_ITEM(S3C2410_GPFUP),
128
129 SAVE_ITEM(S3C2410_GPGCON),
130 SAVE_ITEM(S3C2410_GPGDAT),
131 SAVE_ITEM(S3C2410_GPGUP),
132
133 SAVE_ITEM(S3C2410_GPHCON),
134 SAVE_ITEM(S3C2410_GPHDAT),
135 SAVE_ITEM(S3C2410_GPHUP),
136
137 SAVE_ITEM(S3C2410_DCLKCON),
138};
139
140#ifdef CONFIG_S3C2410_PM_DEBUG
141
142#define SAVE_UART(va) \
143 SAVE_ITEM((va) + S3C2410_ULCON), \
144 SAVE_ITEM((va) + S3C2410_UCON), \
145 SAVE_ITEM((va) + S3C2410_UFCON), \
146 SAVE_ITEM((va) + S3C2410_UMCON), \
147 SAVE_ITEM((va) + S3C2410_UBRDIV)
148
149static struct sleep_save uart_save[] = {
150 SAVE_UART(S3C24XX_VA_UART0),
151 SAVE_UART(S3C24XX_VA_UART1),
152#ifndef CONFIG_CPU_S3C2400
153 SAVE_UART(S3C24XX_VA_UART2),
154#endif
155};
156
157/* debug
158 *
159 * we send the debug to printascii() to allow it to be seen if the
160 * system never wakes up from the sleep
161*/
162
163extern void printascii(const char *);
164
165static void pm_dbg(const char *fmt, ...)
166{
167 va_list va;
168 char buff[256];
169
170 va_start(va, fmt);
171 vsprintf(buff, fmt, va);
172 va_end(va);
173
174 printascii(buff);
175}
176
177static void s3c2410_pm_debug_init(void)
178{
179 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
180
181 /* re-start uart clocks */
182 tmp |= S3C2410_CLKCON_UART0;
183 tmp |= S3C2410_CLKCON_UART1;
184 tmp |= S3C2410_CLKCON_UART2;
185
186 __raw_writel(tmp, S3C2410_CLKCON);
187 udelay(10);
188}
189
190#define DBG(fmt...) pm_dbg(fmt)
191#else
192#define DBG(fmt...) printk(KERN_DEBUG fmt)
193
194#define s3c2410_pm_debug_init() do { } while(0)
195
196static struct sleep_save uart_save[] = {};
197#endif
198
199#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
200
201/* suspend checking code...
202 *
203 * this next area does a set of crc checks over all the installed
204 * memory, so the system can verify if the resume was ok.
205 *
206 * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
207 * increasing it will mean that the area corrupted will be less easy to spot,
208 * and reducing the size will cause the CRC save area to grow
209*/
210
211#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
212
213static u32 crc_size; /* size needed for the crc block */
214static u32 *crcs; /* allocated over suspend/resume */
215
216typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
217
218/* s3c2410_pm_run_res
219 *
220 * go thorugh the given resource list, and look for system ram
221*/
222
223static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
224{
225 while (ptr != NULL) {
226 if (ptr->child != NULL)
227 s3c2410_pm_run_res(ptr->child, fn, arg);
228
229 if ((ptr->flags & IORESOURCE_MEM) &&
230 strcmp(ptr->name, "System RAM") == 0) {
231 DBG("Found system RAM at %08lx..%08lx\n",
232 ptr->start, ptr->end);
233 arg = (fn)(ptr, arg);
234 }
235
236 ptr = ptr->sibling;
237 }
238}
239
240static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
241{
242 s3c2410_pm_run_res(&iomem_resource, fn, arg);
243}
244
245static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
246{
247 u32 size = (u32)(res->end - res->start)+1;
248
249 size += CHECK_CHUNKSIZE-1;
250 size /= CHECK_CHUNKSIZE;
251
252 DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
253
254 *val += size * sizeof(u32);
255 return val;
256}
257
258/* s3c2410_pm_prepare_check
259 *
260 * prepare the necessary information for creating the CRCs. This
261 * must be done before the final save, as it will require memory
262 * allocating, and thus touching bits of the kernel we do not
263 * know about.
264*/
265
266static void s3c2410_pm_check_prepare(void)
267{
268 crc_size = 0;
269
270 s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
271
272 DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
273
274 crcs = kmalloc(crc_size+4, GFP_KERNEL);
275 if (crcs == NULL)
276 printk(KERN_ERR "Cannot allocated CRC save area\n");
277}
278
279static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
280{
281 unsigned long addr, left;
282
283 for (addr = res->start; addr < res->end;
284 addr += CHECK_CHUNKSIZE) {
285 left = res->end - addr;
286
287 if (left > CHECK_CHUNKSIZE)
288 left = CHECK_CHUNKSIZE;
289
290 *val = crc32_le(~0, phys_to_virt(addr), left);
291 val++;
292 }
293
294 return val;
295}
296
297/* s3c2410_pm_check_store
298 *
299 * compute the CRC values for the memory blocks before the final
300 * sleep.
301*/
302
303static void s3c2410_pm_check_store(void)
304{
305 if (crcs != NULL)
306 s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
307}
308
309/* in_region
310 *
311 * return TRUE if the area defined by ptr..ptr+size contatins the
312 * what..what+whatsz
313*/
314
315static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
316{
317 if ((what+whatsz) < ptr)
318 return 0;
319
320 if (what > (ptr+size))
321 return 0;
322
323 return 1;
324}
325
326static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
327{
328 void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
329 unsigned long addr;
330 unsigned long left;
331 void *ptr;
332 u32 calc;
333
334 for (addr = res->start; addr < res->end;
335 addr += CHECK_CHUNKSIZE) {
336 left = res->end - addr;
337
338 if (left > CHECK_CHUNKSIZE)
339 left = CHECK_CHUNKSIZE;
340
341 ptr = phys_to_virt(addr);
342
343 if (in_region(ptr, left, crcs, crc_size)) {
344 DBG("skipping %08lx, has crc block in\n", addr);
345 goto skip_check;
346 }
347
348 if (in_region(ptr, left, save_at, 32*4 )) {
349 DBG("skipping %08lx, has save block in\n", addr);
350 goto skip_check;
351 }
352
353 /* calculate and check the checksum */
354
355 calc = crc32_le(~0, ptr, left);
356 if (calc != *val) {
357 printk(KERN_ERR PFX "Restore CRC error at "
358 "%08lx (%08x vs %08x)\n", addr, calc, *val);
359
360 DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
361 addr, calc, *val);
362 }
363
364 skip_check:
365 val++;
366 }
367
368 return val;
369}
370
371/* s3c2410_pm_check_restore
372 *
373 * check the CRCs after the restore event and free the memory used
374 * to hold them
375*/
376
377static void s3c2410_pm_check_restore(void)
378{
379 if (crcs != NULL) {
380 s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
381 kfree(crcs);
382 crcs = NULL;
383 }
384}
385
386#else
387
388#define s3c2410_pm_check_prepare() do { } while(0)
389#define s3c2410_pm_check_restore() do { } while(0)
390#define s3c2410_pm_check_store() do { } while(0)
391#endif
392
393/* helper functions to save and restore register state */
394
395void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
396{
397 for (; count > 0; count--, ptr++) {
398 ptr->val = __raw_readl(ptr->reg);
399 DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
400 }
401}
402
403/* s3c2410_pm_do_restore
404 *
405 * restore the system from the given list of saved registers
406 *
407 * Note, we do not use DBG() in here, as the system may not have
408 * restore the UARTs state yet
409*/
410
411void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
412{
413 for (; count > 0; count--, ptr++) {
414 printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
415 ptr->reg, ptr->val, __raw_readl(ptr->reg));
416
417 __raw_writel(ptr->val, ptr->reg);
418 }
419}
420
421/* s3c2410_pm_do_restore_core
422 *
423 * similar to s3c2410_pm_do_restore_core
424 *
425 * WARNING: Do not put any debug in here that may effect memory or use
426 * peripherals, as things may be changing!
427*/
428
429static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
430{
431 for (; count > 0; count--, ptr++) {
432 __raw_writel(ptr->val, ptr->reg);
433 }
434}
435
436/* s3c2410_pm_show_resume_irqs
437 *
438 * print any IRQs asserted at resume time (ie, we woke from)
439*/
440
441static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
442 unsigned long mask)
443{
444 int i;
445
446 which &= ~mask;
447
448 for (i = 0; i <= 31; i++) {
449 if ((which) & (1L<<i)) {
450 DBG("IRQ %d asserted at resume\n", start+i);
451 }
452 }
453}
454
455/* s3c2410_pm_check_resume_pin
456 *
457 * check to see if the pin is configured correctly for sleep mode, and
458 * make any necessary adjustments if it is not
459*/
460
461static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
462{
463 unsigned long irqstate;
464 unsigned long pinstate;
465 int irq = s3c2410_gpio_getirq(pin);
466
467 if (irqoffs < 4)
468 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
469 else
470 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
471
472 pinstate = s3c2410_gpio_getcfg(pin);
473 pinstate >>= S3C2410_GPIO_OFFSET(pin)*2;
474
475 if (!irqstate) {
476 if (pinstate == 0x02)
477 DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
478 } else {
479 if (pinstate == 0x02) {
480 DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
481 s3c2410_gpio_cfgpin(pin, 0x00);
482 }
483 }
484}
485
486/* s3c2410_pm_configure_extint
487 *
488 * configure all external interrupt pins
489*/
490
491static void s3c2410_pm_configure_extint(void)
492{
493 int pin;
494
495 /* for each of the external interrupts (EINT0..EINT15) we
496 * need to check wether it is an external interrupt source,
497 * and then configure it as an input if it is not
498 */
499
500 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
501 s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
502 }
503
504 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
505 s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
506 }
507}
508
509#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
510
511/* s3c2410_pm_enter
512 *
513 * central control for sleep/resume process
514*/
515
516static int s3c2410_pm_enter(suspend_state_t state)
517{
518 unsigned long regs_save[16];
519 unsigned long tmp;
520
521 /* ensure the debug is initialised (if enabled) */
522
523 s3c2410_pm_debug_init();
524
525 DBG("s3c2410_pm_enter(%d)\n", state);
526
527 if (state != PM_SUSPEND_MEM) {
528 printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
529 return -EINVAL;
530 }
531
532 /* check if we have anything to wake-up with... bad things seem
533 * to happen if you suspend with no wakeup (system will often
534 * require a full power-cycle)
535 */
536
537 if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
538 !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
539 printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
540 printk(KERN_ERR PFX "Aborting sleep\n");
541 return -EINVAL;
542 }
543
544 /* prepare check area if configured */
545
546 s3c2410_pm_check_prepare();
547
548 /* store the physical address of the register recovery block */
549
550 s3c2410_sleep_save_phys = virt_to_phys(regs_save);
551
552 DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
553
554 /* ensure at least GESTATUS3 has the resume address */
555
556 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
557
558 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
559 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
560
561 /* save all necessary core registers not covered by the drivers */
562
563 s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
564 s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
565 s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
566 s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
567
568 /* set the irq configuration for wake */
569
570 s3c2410_pm_configure_extint();
571
572 DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
573 s3c_irqwake_intmask, s3c_irqwake_eintmask);
574
575 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
576 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
577
578 /* ack any outstanding external interrupts before we go to sleep */
579
580 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
581
582 /* flush cache back to ram */
583
584 arm920_flush_kern_cache_all();
585
586 s3c2410_pm_check_store();
587
588 // need to make some form of time-delta
589
590 /* send the cpu to sleep... */
591
592 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
593
594 s3c2410_cpu_suspend(regs_save);
595
596 /* unset the return-from-sleep flag, to ensure reset */
597
598 tmp = __raw_readl(S3C2410_GSTATUS2);
599 tmp &= S3C2410_GSTATUS2_OFFRESET;
600 __raw_writel(tmp, S3C2410_GSTATUS2);
601
602 /* restore the system state */
603
604 s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
605 s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
606 s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
607 s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
608
609 s3c2410_pm_debug_init();
610
611 /* check what irq (if any) restored the system */
612
613 DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
614 __raw_readl(S3C2410_SRCPND),
615 __raw_readl(S3C2410_EINTPEND));
616
617 s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
618 s3c_irqwake_intmask);
619
620 s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
621 s3c_irqwake_eintmask);
622
623 DBG("post sleep, preparing to return\n");
624
625 s3c2410_pm_check_restore();
626
627 /* ok, let's return from sleep */
628
629 DBG("S3C2410 PM Resume (post-restore)\n");
630 return 0;
631}
632
633/*
634 * Called after processes are frozen, but before we shut down devices.
635 */
636static int s3c2410_pm_prepare(suspend_state_t state)
637{
638 return 0;
639}
640
641/*
642 * Called after devices are re-setup, but before processes are thawed.
643 */
644static int s3c2410_pm_finish(suspend_state_t state)
645{
646 return 0;
647}
648
649/*
650 * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
651 */
652static struct pm_ops s3c2410_pm_ops = {
653 .pm_disk_mode = PM_DISK_FIRMWARE,
654 .prepare = s3c2410_pm_prepare,
655 .enter = s3c2410_pm_enter,
656 .finish = s3c2410_pm_finish,
657};
658
659/* s3c2410_pm_init
660 *
661 * Attach the power management functions. This should be called
662 * from the board specific initialisation if the board supports
663 * it.
664*/
665
666int __init s3c2410_pm_init(void)
667{
668 printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
669
670 pm_set_ops(&s3c2410_pm_ops);
671 return 0;
672}