aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s3c2410/mach-qt2410.c
diff options
context:
space:
mode:
authorKrzysztof Helt <krzysztof.h1@wp.pl>2007-10-16 04:28:58 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-16 12:43:16 -0400
commitf28ef573ad09596b771b67c276bbc5f49281fa9d (patch)
tree5061be2ae82f513a8c23e220b8a97f30b08ec34a /arch/arm/mach-s3c2410/mach-qt2410.c
parent9939a481cd66a109e4ad09328df1bd0540e0aa84 (diff)
s3c2410fb: remove lcdcon3 register from s3c2410fb_display
This patch removes unused lcdcon3 register from the s3c2410fb_display structure. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/arm/mach-s3c2410/mach-qt2410.c')
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c111
1 files changed, 45 insertions, 66 deletions
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 0c1ff0a41a99..0a746f7f639f 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -98,30 +98,23 @@ static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
98static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = { 98static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
99 { 99 {
100 /* Configuration for 640x480 SHARP LQ080V3DG01 */ 100 /* Configuration for 640x480 SHARP LQ080V3DG01 */
101 .regs = { 101 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
102 S3C2410_LCDCON1_TFT |
103 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
102 104
103 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | 105 .lcdcon2 = S3C2410_LCDCON2_VBPD(18) | /* 19 */
104 S3C2410_LCDCON1_TFT | 106 S3C2410_LCDCON2_LINEVAL(479) |
105 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */ 107 S3C2410_LCDCON2_VFPD(10) | /* 11 */
108 S3C2410_LCDCON2_VSPW(14), /* 15 */
106 109
107 .lcdcon2 = S3C2410_LCDCON2_VBPD(18) | /* 19 */ 110 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
108 S3C2410_LCDCON2_LINEVAL(479) | 111 S3C2410_LCDCON4_HSPW(95), /* 96 */
109 S3C2410_LCDCON2_VFPD(10) | /* 11 */
110 S3C2410_LCDCON2_VSPW(14), /* 15 */
111 112
112 .lcdcon3 = S3C2410_LCDCON3_HBPD(43) | /* 44 */ 113 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
113 S3C2410_LCDCON3_HOZVAL(639) | /* 640 */ 114 S3C2410_LCDCON5_INVVLINE |
114 S3C2410_LCDCON3_HFPD(115), /* 116 */ 115 S3C2410_LCDCON5_INVVFRAME |
115 116 S3C2410_LCDCON5_PWREN |
116 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | 117 S3C2410_LCDCON5_HWSWP,
117 S3C2410_LCDCON4_HSPW(95), /* 96 */
118
119 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
120 S3C2410_LCDCON5_INVVLINE |
121 S3C2410_LCDCON5_INVVFRAME |
122 S3C2410_LCDCON5_PWREN |
123 S3C2410_LCDCON5_HWSWP,
124 },
125 118
126 .type = S3C2410_LCDCON1_TFT, 119 .type = S3C2410_LCDCON1_TFT,
127 .width = 640, 120 .width = 640,
@@ -135,30 +128,23 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
135 }, 128 },
136 { 129 {
137 /* Configuration for 480x640 toppoly TD028TTEC1 */ 130 /* Configuration for 480x640 toppoly TD028TTEC1 */
138 .regs = { 131 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
139 132 S3C2410_LCDCON1_TFT |
140 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | 133 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
141 S3C2410_LCDCON1_TFT |
142 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
143
144 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | /* 2 */
145 S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
146 S3C2410_LCDCON2_VFPD(3) | /* 4 */
147 S3C2410_LCDCON2_VSPW(1), /* 2 */
148 134
149 .lcdcon3 = S3C2410_LCDCON3_HBPD(7) | /* 8 */ 135 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | /* 2 */
150 S3C2410_LCDCON3_HOZVAL(479) | /* 479 */ 136 S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
151 S3C2410_LCDCON3_HFPD(23), /* 24 */ 137 S3C2410_LCDCON2_VFPD(3) | /* 4 */
138 S3C2410_LCDCON2_VSPW(1), /* 2 */
152 139
153 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | 140 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
154 S3C2410_LCDCON4_HSPW(7), /* 8 */ 141 S3C2410_LCDCON4_HSPW(7), /* 8 */
155 142
156 .lcdcon5 = S3C2410_LCDCON5_FRM565 | 143 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
157 S3C2410_LCDCON5_INVVLINE | 144 S3C2410_LCDCON5_INVVLINE |
158 S3C2410_LCDCON5_INVVFRAME | 145 S3C2410_LCDCON5_INVVFRAME |
159 S3C2410_LCDCON5_PWREN | 146 S3C2410_LCDCON5_PWREN |
160 S3C2410_LCDCON5_HWSWP, 147 S3C2410_LCDCON5_HWSWP,
161 },
162 148
163 .type = S3C2410_LCDCON1_TFT, 149 .type = S3C2410_LCDCON1_TFT,
164 .width = 480, 150 .width = 480,
@@ -171,30 +157,23 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
171 }, 157 },
172 { 158 {
173 /* Config for 240x320 LCD */ 159 /* Config for 240x320 LCD */
174 .regs = { 160 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
175 161 S3C2410_LCDCON1_TFT |
176 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | 162 S3C2410_LCDCON1_CLKVAL(0x04),
177 S3C2410_LCDCON1_TFT | 163
178 S3C2410_LCDCON1_CLKVAL(0x04), 164 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
179 165 S3C2410_LCDCON2_LINEVAL(319) |
180 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | 166 S3C2410_LCDCON2_VFPD(6) |
181 S3C2410_LCDCON2_LINEVAL(319) | 167 S3C2410_LCDCON2_VSPW(3),
182 S3C2410_LCDCON2_VFPD(6) | 168
183 S3C2410_LCDCON2_VSPW(3), 169 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
184 170 S3C2410_LCDCON4_HSPW(3),
185 .lcdcon3 = S3C2410_LCDCON3_HBPD(12) | 171
186 S3C2410_LCDCON3_HOZVAL(239) | 172 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
187 S3C2410_LCDCON3_HFPD(7), 173 S3C2410_LCDCON5_INVVLINE |
188 174 S3C2410_LCDCON5_INVVFRAME |
189 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | 175 S3C2410_LCDCON5_PWREN |
190 S3C2410_LCDCON4_HSPW(3), 176 S3C2410_LCDCON5_HWSWP,
191
192 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
193 S3C2410_LCDCON5_INVVLINE |
194 S3C2410_LCDCON5_INVVFRAME |
195 S3C2410_LCDCON5_PWREN |
196 S3C2410_LCDCON5_HWSWP,
197 },
198 177
199 .type = S3C2410_LCDCON1_TFT, 178 .type = S3C2410_LCDCON1_TFT,
200 .width = 240, 179 .width = 240,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 10:37:48 -0500