aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s3c2410/irq.c
diff options
context:
space:
mode:
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-11-23 06:41:32 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-11-30 07:24:47 -0500
commit10dd5ce28d78e2440e8fa1135d17e33399d75340 (patch)
treed2e76765a57e7e47a9c424f99c3a22bf99c6da64 /arch/arm/mach-s3c2410/irq.c
parent127e477e0cd8da4d3058709ab2dc7b92dccbcba5 (diff)
[ARM] Remove compatibility layer for ARM irqs
set_irq_chipdata -> set_irq_chip_data get_irq_chipdata -> get_irq_chip_data do_level_IRQ -> handle_level_irq do_edge_IRQ -> handle_edge_irq do_simple_IRQ -> handle_simple_irq irqdesc -> irq_desc irqchip -> irq_chip Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410/irq.c')
-rw-r--r--arch/arm/mach-s3c2410/irq.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 683b3491ba3c..e7d2ad96ae68 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -180,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno)
180 __raw_writel(mask, S3C2410_INTMSK); 180 __raw_writel(mask, S3C2410_INTMSK);
181} 181}
182 182
183struct irqchip s3c_irq_level_chip = { 183struct irq_chip s3c_irq_level_chip = {
184 .name = "s3c-level", 184 .name = "s3c-level",
185 .ack = s3c_irq_maskack, 185 .ack = s3c_irq_maskack,
186 .mask = s3c_irq_mask, 186 .mask = s3c_irq_mask,
@@ -188,7 +188,7 @@ struct irqchip s3c_irq_level_chip = {
188 .set_wake = s3c_irq_wake 188 .set_wake = s3c_irq_wake
189}; 189};
190 190
191static struct irqchip s3c_irq_chip = { 191static struct irq_chip s3c_irq_chip = {
192 .name = "s3c", 192 .name = "s3c",
193 .ack = s3c_irq_ack, 193 .ack = s3c_irq_ack,
194 .mask = s3c_irq_mask, 194 .mask = s3c_irq_mask,
@@ -344,7 +344,7 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
344 return 0; 344 return 0;
345} 345}
346 346
347static struct irqchip s3c_irqext_chip = { 347static struct irq_chip s3c_irqext_chip = {
348 .name = "s3c-ext", 348 .name = "s3c-ext",
349 .mask = s3c_irqext_mask, 349 .mask = s3c_irqext_mask,
350 .unmask = s3c_irqext_unmask, 350 .unmask = s3c_irqext_unmask,
@@ -353,7 +353,7 @@ static struct irqchip s3c_irqext_chip = {
353 .set_wake = s3c_irqext_wake 353 .set_wake = s3c_irqext_wake
354}; 354};
355 355
356static struct irqchip s3c_irq_eint0t4 = { 356static struct irq_chip s3c_irq_eint0t4 = {
357 .name = "s3c-ext0", 357 .name = "s3c-ext0",
358 .ack = s3c_irq_ack, 358 .ack = s3c_irq_ack,
359 .mask = s3c_irq_mask, 359 .mask = s3c_irq_mask,
@@ -390,7 +390,7 @@ s3c_irq_uart0_ack(unsigned int irqno)
390 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); 390 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
391} 391}
392 392
393static struct irqchip s3c_irq_uart0 = { 393static struct irq_chip s3c_irq_uart0 = {
394 .name = "s3c-uart0", 394 .name = "s3c-uart0",
395 .mask = s3c_irq_uart0_mask, 395 .mask = s3c_irq_uart0_mask,
396 .unmask = s3c_irq_uart0_unmask, 396 .unmask = s3c_irq_uart0_unmask,
@@ -417,7 +417,7 @@ s3c_irq_uart1_ack(unsigned int irqno)
417 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); 417 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
418} 418}
419 419
420static struct irqchip s3c_irq_uart1 = { 420static struct irq_chip s3c_irq_uart1 = {
421 .name = "s3c-uart1", 421 .name = "s3c-uart1",
422 .mask = s3c_irq_uart1_mask, 422 .mask = s3c_irq_uart1_mask,
423 .unmask = s3c_irq_uart1_unmask, 423 .unmask = s3c_irq_uart1_unmask,
@@ -444,7 +444,7 @@ s3c_irq_uart2_ack(unsigned int irqno)
444 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); 444 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
445} 445}
446 446
447static struct irqchip s3c_irq_uart2 = { 447static struct irq_chip s3c_irq_uart2 = {
448 .name = "s3c-uart2", 448 .name = "s3c-uart2",
449 .mask = s3c_irq_uart2_mask, 449 .mask = s3c_irq_uart2_mask,
450 .unmask = s3c_irq_uart2_unmask, 450 .unmask = s3c_irq_uart2_unmask,
@@ -471,7 +471,7 @@ s3c_irq_adc_ack(unsigned int irqno)
471 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); 471 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
472} 472}
473 473
474static struct irqchip s3c_irq_adc = { 474static struct irq_chip s3c_irq_adc = {
475 .name = "s3c-adc", 475 .name = "s3c-adc",
476 .mask = s3c_irq_adc_mask, 476 .mask = s3c_irq_adc_mask,
477 .unmask = s3c_irq_adc_unmask, 477 .unmask = s3c_irq_adc_unmask,
@@ -480,11 +480,11 @@ static struct irqchip s3c_irq_adc = {
480 480
481/* irq demux for adc */ 481/* irq demux for adc */
482static void s3c_irq_demux_adc(unsigned int irq, 482static void s3c_irq_demux_adc(unsigned int irq,
483 struct irqdesc *desc) 483 struct irq_desc *desc)
484{ 484{
485 unsigned int subsrc, submsk; 485 unsigned int subsrc, submsk;
486 unsigned int offset = 9; 486 unsigned int offset = 9;
487 struct irqdesc *mydesc; 487 struct irq_desc *mydesc;
488 488
489 /* read the current pending interrupts, and the mask 489 /* read the current pending interrupts, and the mask
490 * for what it is available */ 490 * for what it is available */
@@ -512,7 +512,7 @@ static void s3c_irq_demux_uart(unsigned int start)
512{ 512{
513 unsigned int subsrc, submsk; 513 unsigned int subsrc, submsk;
514 unsigned int offset = start - IRQ_S3CUART_RX0; 514 unsigned int offset = start - IRQ_S3CUART_RX0;
515 struct irqdesc *desc; 515 struct irq_desc *desc;
516 516
517 /* read the current pending interrupts, and the mask 517 /* read the current pending interrupts, and the mask
518 * for what it is available */ 518 * for what it is available */
@@ -549,7 +549,7 @@ static void s3c_irq_demux_uart(unsigned int start)
549 549
550static void 550static void
551s3c_irq_demux_uart0(unsigned int irq, 551s3c_irq_demux_uart0(unsigned int irq,
552 struct irqdesc *desc) 552 struct irq_desc *desc)
553{ 553{
554 irq = irq; 554 irq = irq;
555 s3c_irq_demux_uart(IRQ_S3CUART_RX0); 555 s3c_irq_demux_uart(IRQ_S3CUART_RX0);
@@ -557,7 +557,7 @@ s3c_irq_demux_uart0(unsigned int irq,
557 557
558static void 558static void
559s3c_irq_demux_uart1(unsigned int irq, 559s3c_irq_demux_uart1(unsigned int irq,
560 struct irqdesc *desc) 560 struct irq_desc *desc)
561{ 561{
562 irq = irq; 562 irq = irq;
563 s3c_irq_demux_uart(IRQ_S3CUART_RX1); 563 s3c_irq_demux_uart(IRQ_S3CUART_RX1);
@@ -565,7 +565,7 @@ s3c_irq_demux_uart1(unsigned int irq,
565 565
566static void 566static void
567s3c_irq_demux_uart2(unsigned int irq, 567s3c_irq_demux_uart2(unsigned int irq,
568 struct irqdesc *desc) 568 struct irq_desc *desc)
569{ 569{
570 irq = irq; 570 irq = irq;
571 s3c_irq_demux_uart(IRQ_S3CUART_RX2); 571 s3c_irq_demux_uart(IRQ_S3CUART_RX2);
@@ -573,7 +573,7 @@ s3c_irq_demux_uart2(unsigned int irq,
573 573
574static void 574static void
575s3c_irq_demux_extint8(unsigned int irq, 575s3c_irq_demux_extint8(unsigned int irq,
576 struct irqdesc *desc) 576 struct irq_desc *desc)
577{ 577{
578 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 578 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
579 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 579 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -595,7 +595,7 @@ s3c_irq_demux_extint8(unsigned int irq,
595 595
596static void 596static void
597s3c_irq_demux_extint4t7(unsigned int irq, 597s3c_irq_demux_extint4t7(unsigned int irq,
598 struct irqdesc *desc) 598 struct irq_desc *desc)
599{ 599{
600 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 600 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
601 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 601 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -738,7 +738,7 @@ void __init s3c24xx_init_irq(void)
738 case IRQ_UART2: 738 case IRQ_UART2:
739 case IRQ_ADCPARENT: 739 case IRQ_ADCPARENT:
740 set_irq_chip(irqno, &s3c_irq_level_chip); 740 set_irq_chip(irqno, &s3c_irq_level_chip);
741 set_irq_handler(irqno, do_level_IRQ); 741 set_irq_handler(irqno, handle_level_irq);
742 break; 742 break;
743 743
744 case IRQ_RESERVED6: 744 case IRQ_RESERVED6:
@@ -749,7 +749,7 @@ void __init s3c24xx_init_irq(void)
749 default: 749 default:
750 //irqdbf("registering irq %d (s3c irq)\n", irqno); 750 //irqdbf("registering irq %d (s3c irq)\n", irqno);
751 set_irq_chip(irqno, &s3c_irq_chip); 751 set_irq_chip(irqno, &s3c_irq_chip);
752 set_irq_handler(irqno, do_edge_IRQ); 752 set_irq_handler(irqno, handle_edge_irq);
753 set_irq_flags(irqno, IRQF_VALID); 753 set_irq_flags(irqno, IRQF_VALID);
754 } 754 }
755 } 755 }
@@ -769,14 +769,14 @@ void __init s3c24xx_init_irq(void)
769 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 769 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
770 irqdbf("registering irq %d (ext int)\n", irqno); 770 irqdbf("registering irq %d (ext int)\n", irqno);
771 set_irq_chip(irqno, &s3c_irq_eint0t4); 771 set_irq_chip(irqno, &s3c_irq_eint0t4);
772 set_irq_handler(irqno, do_edge_IRQ); 772 set_irq_handler(irqno, handle_edge_irq);
773 set_irq_flags(irqno, IRQF_VALID); 773 set_irq_flags(irqno, IRQF_VALID);
774 } 774 }
775 775
776 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { 776 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
777 irqdbf("registering irq %d (extended s3c irq)\n", irqno); 777 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
778 set_irq_chip(irqno, &s3c_irqext_chip); 778 set_irq_chip(irqno, &s3c_irqext_chip);
779 set_irq_handler(irqno, do_edge_IRQ); 779 set_irq_handler(irqno, handle_edge_irq);
780 set_irq_flags(irqno, IRQF_VALID); 780 set_irq_flags(irqno, IRQF_VALID);
781 } 781 }
782 782
@@ -787,28 +787,28 @@ void __init s3c24xx_init_irq(void)
787 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { 787 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
788 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); 788 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
789 set_irq_chip(irqno, &s3c_irq_uart0); 789 set_irq_chip(irqno, &s3c_irq_uart0);
790 set_irq_handler(irqno, do_level_IRQ); 790 set_irq_handler(irqno, handle_level_irq);
791 set_irq_flags(irqno, IRQF_VALID); 791 set_irq_flags(irqno, IRQF_VALID);
792 } 792 }
793 793
794 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { 794 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
795 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); 795 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
796 set_irq_chip(irqno, &s3c_irq_uart1); 796 set_irq_chip(irqno, &s3c_irq_uart1);
797 set_irq_handler(irqno, do_level_IRQ); 797 set_irq_handler(irqno, handle_level_irq);
798 set_irq_flags(irqno, IRQF_VALID); 798 set_irq_flags(irqno, IRQF_VALID);
799 } 799 }
800 800
801 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { 801 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
802 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); 802 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
803 set_irq_chip(irqno, &s3c_irq_uart2); 803 set_irq_chip(irqno, &s3c_irq_uart2);
804 set_irq_handler(irqno, do_level_IRQ); 804 set_irq_handler(irqno, handle_level_irq);
805 set_irq_flags(irqno, IRQF_VALID); 805 set_irq_flags(irqno, IRQF_VALID);
806 } 806 }
807 807
808 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { 808 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
809 irqdbf("registering irq %d (s3c adc irq)\n", irqno); 809 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
810 set_irq_chip(irqno, &s3c_irq_adc); 810 set_irq_chip(irqno, &s3c_irq_adc);
811 set_irq_handler(irqno, do_edge_IRQ); 811 set_irq_handler(irqno, handle_edge_irq);
812 set_irq_flags(irqno, IRQF_VALID); 812 set_irq_flags(irqno, IRQF_VALID);
813 } 813 }
814 814