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authorBen Dooks <ben-linux@fluff.org>2006-06-24 16:21:33 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-24 16:21:33 -0400
commit44cc7c9c15124c4506da96304e5f9eb88200fc35 (patch)
tree911dcdfc55ed609a79f7c1c23c918e709b6e3cdf /arch/arm/mach-s3c2410/irq.c
parent46491c94d39a519178ba8c6b5b5d6a839210124d (diff)
[ARM] 3641/1: S3C2412: Fixup gpio register naming
Patch from Ben Dooks The current S3C2412 has used to moving S3C24XX_ for the generic form of an register has been moved from the S3C2410. Fixup S3C2410_EXTINTx and S3C2410_EINFLTx to S3C24XX_EXTINTx and S3C24XX_EXTINTx Depends on Patch #3635/1, Patch #3640/1 Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410/irq.c')
-rw-r--r--arch/arm/mach-s3c2410/irq.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 66d8c068e940..46465742ed79 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -275,28 +275,28 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
275 if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3)) 275 if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
276 { 276 {
277 gpcon_reg = S3C2410_GPFCON; 277 gpcon_reg = S3C2410_GPFCON;
278 extint_reg = S3C2410_EXTINT0; 278 extint_reg = S3C24XX_EXTINT0;
279 gpcon_offset = (irq - IRQ_EINT0) * 2; 279 gpcon_offset = (irq - IRQ_EINT0) * 2;
280 extint_offset = (irq - IRQ_EINT0) * 4; 280 extint_offset = (irq - IRQ_EINT0) * 4;
281 } 281 }
282 else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7)) 282 else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
283 { 283 {
284 gpcon_reg = S3C2410_GPFCON; 284 gpcon_reg = S3C2410_GPFCON;
285 extint_reg = S3C2410_EXTINT0; 285 extint_reg = S3C24XX_EXTINT0;
286 gpcon_offset = (irq - (EXTINT_OFF)) * 2; 286 gpcon_offset = (irq - (EXTINT_OFF)) * 2;
287 extint_offset = (irq - (EXTINT_OFF)) * 4; 287 extint_offset = (irq - (EXTINT_OFF)) * 4;
288 } 288 }
289 else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15)) 289 else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
290 { 290 {
291 gpcon_reg = S3C2410_GPGCON; 291 gpcon_reg = S3C2410_GPGCON;
292 extint_reg = S3C2410_EXTINT1; 292 extint_reg = S3C24XX_EXTINT1;
293 gpcon_offset = (irq - IRQ_EINT8) * 2; 293 gpcon_offset = (irq - IRQ_EINT8) * 2;
294 extint_offset = (irq - IRQ_EINT8) * 4; 294 extint_offset = (irq - IRQ_EINT8) * 4;
295 } 295 }
296 else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23)) 296 else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
297 { 297 {
298 gpcon_reg = S3C2410_GPGCON; 298 gpcon_reg = S3C2410_GPGCON;
299 extint_reg = S3C2410_EXTINT2; 299 extint_reg = S3C24XX_EXTINT2;
300 gpcon_offset = (irq - IRQ_EINT8) * 2; 300 gpcon_offset = (irq - IRQ_EINT8) * 2;
301 extint_offset = (irq - IRQ_EINT16) * 4; 301 extint_offset = (irq - IRQ_EINT16) * 4;
302 } else 302 } else