[ARM] S3C24XX: Split pll code out of regs-clock.h

Move the PLL calculation code into it's own header
file for re-use with the other plat-s3c24xx based
systems such as the S3C24A0.

Note, we change the name of s3c2410_get_pll to the
more generically named s3c24xx_get_pll as well as
the related defintions.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>

1 files changed, 0 insertions, 33 deletions

diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
index b3f90aa78076..2a5d90e957fb 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
@@ -42,13 +42,6 @@
 #define S3C2410_CLKCON_IIS           (1<<17)
 #define S3C2410_CLKCON_SPI           (1<<18)
 
-#define S3C2410_PLLCON_MDIVSHIFT     12
-#define S3C2410_PLLCON_PDIVSHIFT     4
-#define S3C2410_PLLCON_SDIVSHIFT     0
-#define S3C2410_PLLCON_MDIVMASK      ((1<<(1+(19-12)))-1)
-#define S3C2410_PLLCON_PDIVMASK      ((1<<5)-1)
-#define S3C2410_PLLCON_SDIVMASK      3
-
 /* DCLKCON register addresses in gpio.h */
 
 #define S3C2410_DCLKCON_DCLK0EN      (1<<0)
@@ -76,32 +69,6 @@
 #define S3C2410_CLKSLOW_SLOWVAL(x)      (x)
 #define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
 
-#ifndef __ASSEMBLY__
-
-#include <asm/div64.h>
-
-static inline unsigned int
-s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
-{
-        unsigned int mdiv, pdiv, sdiv;
-        uint64_t fvco;
-
-        mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
-        pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
-        sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
-
-        mdiv &= S3C2410_PLLCON_MDIVMASK;
-        pdiv &= S3C2410_PLLCON_PDIVMASK;
-        sdiv &= S3C2410_PLLCON_SDIVMASK;
-
-        fvco = (uint64_t)baseclk * (mdiv + 8);
-        do_div(fvco, (pdiv + 2) << sdiv);
-
-        return (unsigned int)fvco;
-}
-
-#endif /* __ASSEMBLY__ */
-
 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 
 /* extra registers */