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authorBen Dooks <ben-linux@fluff.org>2009-05-18 11:32:29 -0400
committerBen Dooks <ben-linux@fluff.org>2009-05-18 11:32:29 -0400
commitbcb8a0d6f5e73c61a5290b4faaaa48dfa629e6b0 (patch)
tree6a4345fe0f908d60f52085b97818be705c62af8e /arch/arm/mach-s3c2410/include
parent543899f610799426babb5313682fd9c249e34677 (diff)
parent0b13406a1f1928ec71e81dde52cb62d72ffd28ef (diff)
[ARM] S3C: Merge next-s3c64xx-dma2 into for-rmk-devel
Merge branch 'next-s3c64xx-dma2' into for-rmk-devel Conflicts: arch/arm/plat-s3c64xx/Makefile
Diffstat (limited to 'arch/arm/mach-s3c2410/include')
-rw-r--r--arch/arm/mach-s3c2410/include/mach/dma.h265
1 files changed, 7 insertions, 258 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 13358ce2128c..c3a2629e0ded 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -3,7 +3,7 @@
3 * Copyright (C) 2003,2004,2006 Simtec Electronics 3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * Samsung S3C241XX DMA support 6 * Samsung S3C24XX DMA support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -13,8 +13,8 @@
13#ifndef __ASM_ARCH_DMA_H 13#ifndef __ASM_ARCH_DMA_H
14#define __ASM_ARCH_DMA_H __FILE__ 14#define __ASM_ARCH_DMA_H __FILE__
15 15
16#include <plat/dma.h>
16#include <linux/sysdev.h> 17#include <linux/sysdev.h>
17#include <mach/hardware.h>
18 18
19#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ 19#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
20 20
@@ -55,9 +55,9 @@ enum dma_ch {
55 55
56/* we have 4 dma channels */ 56/* we have 4 dma channels */
57#ifndef CONFIG_CPU_S3C2443 57#ifndef CONFIG_CPU_S3C2443
58#define S3C2410_DMA_CHANNELS (4) 58#define S3C_DMA_CHANNELS (4)
59#else 59#else
60#define S3C2410_DMA_CHANNELS (6) 60#define S3C_DMA_CHANNELS (6)
61#endif 61#endif
62 62
63/* types */ 63/* types */
@@ -68,7 +68,6 @@ enum s3c2410_dma_state {
68 S3C2410_DMA_PAUSED 68 S3C2410_DMA_PAUSED
69}; 69};
70 70
71
72/* enum s3c2410_dma_loadst 71/* enum s3c2410_dma_loadst
73 * 72 *
74 * This represents the state of the DMA engine, wrt to the loaded / running 73 * This represents the state of the DMA engine, wrt to the loaded / running
@@ -104,32 +103,6 @@ enum s3c2410_dma_loadst {
104 S3C2410_DMALOAD_1LOADED_1RUNNING, 103 S3C2410_DMALOAD_1LOADED_1RUNNING,
105}; 104};
106 105
107enum s3c2410_dma_buffresult {
108 S3C2410_RES_OK,
109 S3C2410_RES_ERR,
110 S3C2410_RES_ABORT
111};
112
113enum s3c2410_dmasrc {
114 S3C2410_DMASRC_HW, /* source is memory */
115 S3C2410_DMASRC_MEM /* source is hardware */
116};
117
118/* enum s3c2410_chan_op
119 *
120 * operation codes passed to the DMA code by the user, and also used
121 * to inform the current channel owner of any changes to the system state
122*/
123
124enum s3c2410_chan_op {
125 S3C2410_DMAOP_START,
126 S3C2410_DMAOP_STOP,
127 S3C2410_DMAOP_PAUSE,
128 S3C2410_DMAOP_RESUME,
129 S3C2410_DMAOP_FLUSH,
130 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
131 S3C2410_DMAOP_STARTED, /* indicate channel started */
132};
133 106
134/* flags */ 107/* flags */
135 108
@@ -139,17 +112,14 @@ enum s3c2410_chan_op {
139 112
140/* dma buffer */ 113/* dma buffer */
141 114
142struct s3c2410_dma_client { 115struct s3c2410_dma_buf;
143 char *name;
144};
145 116
146/* s3c2410_dma_buf_s 117/* s3c2410_dma_buf
147 * 118 *
148 * internally used buffer structure to describe a queued or running 119 * internally used buffer structure to describe a queued or running
149 * buffer. 120 * buffer.
150*/ 121*/
151 122
152struct s3c2410_dma_buf;
153struct s3c2410_dma_buf { 123struct s3c2410_dma_buf {
154 struct s3c2410_dma_buf *next; 124 struct s3c2410_dma_buf *next;
155 int magic; /* magic */ 125 int magic; /* magic */
@@ -161,20 +131,6 @@ struct s3c2410_dma_buf {
161 131
162/* [1] is this updated for both recv/send modes? */ 132/* [1] is this updated for both recv/send modes? */
163 133
164struct s3c2410_dma_chan;
165
166/* s3c2410_dma_cbfn_t
167 *
168 * buffer callback routine type
169*/
170
171typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
172 void *buf, int size,
173 enum s3c2410_dma_buffresult result);
174
175typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
176 enum s3c2410_chan_op );
177
178struct s3c2410_dma_stats { 134struct s3c2410_dma_stats {
179 unsigned long loads; 135 unsigned long loads;
180 unsigned long timeout_longest; 136 unsigned long timeout_longest;
@@ -206,10 +162,10 @@ struct s3c2410_dma_chan {
206 162
207 /* channel configuration */ 163 /* channel configuration */
208 enum s3c2410_dmasrc source; 164 enum s3c2410_dmasrc source;
165 enum dma_ch req_ch;
209 unsigned long dev_addr; 166 unsigned long dev_addr;
210 unsigned long load_timeout; 167 unsigned long load_timeout;
211 unsigned int flags; /* channel flags */ 168 unsigned int flags; /* channel flags */
212 unsigned int hw_cfg; /* last hw config */
213 169
214 struct s3c24xx_dma_map *map; /* channel hw maps */ 170 struct s3c24xx_dma_map *map; /* channel hw maps */
215 171
@@ -236,213 +192,6 @@ struct s3c2410_dma_chan {
236 struct sys_device dev; 192 struct sys_device dev;
237}; 193};
238 194
239/* the currently allocated channel information */
240extern struct s3c2410_dma_chan s3c2410_chans[];
241
242/* note, we don't really use dma_device_t at the moment */
243typedef unsigned long dma_device_t; 195typedef unsigned long dma_device_t;
244 196
245/* functions --------------------------------------------------------------- */
246
247/* s3c2410_dma_request
248 *
249 * request a dma channel exclusivley
250*/
251
252extern int s3c2410_dma_request(unsigned int channel,
253 struct s3c2410_dma_client *, void *dev);
254
255
256/* s3c2410_dma_ctrl
257 *
258 * change the state of the dma channel
259*/
260
261extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
262
263/* s3c2410_dma_setflags
264 *
265 * set the channel's flags to a given state
266*/
267
268extern int s3c2410_dma_setflags(unsigned int channel,
269 unsigned int flags);
270
271/* s3c2410_dma_free
272 *
273 * free the dma channel (will also abort any outstanding operations)
274*/
275
276extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
277
278/* s3c2410_dma_enqueue
279 *
280 * place the given buffer onto the queue of operations for the channel.
281 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
282 * drained before the buffer is given to the DMA system.
283*/
284
285extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
286 dma_addr_t data, int size);
287
288/* s3c2410_dma_config
289 *
290 * configure the dma channel
291*/
292
293extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon);
294
295/* s3c2410_dma_devconfig
296 *
297 * configure the device we're talking to
298*/
299
300extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
301 int hwcfg, unsigned long devaddr);
302
303/* s3c2410_dma_getposition
304 *
305 * get the position that the dma transfer is currently at
306*/
307
308extern int s3c2410_dma_getposition(unsigned int channel,
309 dma_addr_t *src, dma_addr_t *dest);
310
311extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
312extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
313
314/* DMA Register definitions */
315
316#define S3C2410_DMA_DISRC (0x00)
317#define S3C2410_DMA_DISRCC (0x04)
318#define S3C2410_DMA_DIDST (0x08)
319#define S3C2410_DMA_DIDSTC (0x0C)
320#define S3C2410_DMA_DCON (0x10)
321#define S3C2410_DMA_DSTAT (0x14)
322#define S3C2410_DMA_DCSRC (0x18)
323#define S3C2410_DMA_DCDST (0x1C)
324#define S3C2410_DMA_DMASKTRIG (0x20)
325#define S3C2412_DMA_DMAREQSEL (0x24)
326#define S3C2443_DMA_DMAREQSEL (0x24)
327
328#define S3C2410_DISRCC_INC (1<<0)
329#define S3C2410_DISRCC_APB (1<<1)
330
331#define S3C2410_DMASKTRIG_STOP (1<<2)
332#define S3C2410_DMASKTRIG_ON (1<<1)
333#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
334
335#define S3C2410_DCON_DEMAND (0<<31)
336#define S3C2410_DCON_HANDSHAKE (1<<31)
337#define S3C2410_DCON_SYNC_PCLK (0<<30)
338#define S3C2410_DCON_SYNC_HCLK (1<<30)
339
340#define S3C2410_DCON_INTREQ (1<<29)
341
342#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
343#define S3C2410_DCON_CH0_UART0 (1<<24)
344#define S3C2410_DCON_CH0_SDI (2<<24)
345#define S3C2410_DCON_CH0_TIMER (3<<24)
346#define S3C2410_DCON_CH0_USBEP1 (4<<24)
347
348#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
349#define S3C2410_DCON_CH1_UART1 (1<<24)
350#define S3C2410_DCON_CH1_I2SSDI (2<<24)
351#define S3C2410_DCON_CH1_SPI (3<<24)
352#define S3C2410_DCON_CH1_USBEP2 (4<<24)
353
354#define S3C2410_DCON_CH2_I2SSDO (0<<24)
355#define S3C2410_DCON_CH2_I2SSDI (1<<24)
356#define S3C2410_DCON_CH2_SDI (2<<24)
357#define S3C2410_DCON_CH2_TIMER (3<<24)
358#define S3C2410_DCON_CH2_USBEP3 (4<<24)
359
360#define S3C2410_DCON_CH3_UART2 (0<<24)
361#define S3C2410_DCON_CH3_SDI (1<<24)
362#define S3C2410_DCON_CH3_SPI (2<<24)
363#define S3C2410_DCON_CH3_TIMER (3<<24)
364#define S3C2410_DCON_CH3_USBEP4 (4<<24)
365
366#define S3C2410_DCON_SRCSHIFT (24)
367#define S3C2410_DCON_SRCMASK (7<<24)
368
369#define S3C2410_DCON_BYTE (0<<20)
370#define S3C2410_DCON_HALFWORD (1<<20)
371#define S3C2410_DCON_WORD (2<<20)
372
373#define S3C2410_DCON_AUTORELOAD (0<<22)
374#define S3C2410_DCON_NORELOAD (1<<22)
375#define S3C2410_DCON_HWTRIG (1<<23)
376
377#ifdef CONFIG_CPU_S3C2440
378#define S3C2440_DIDSTC_CHKINT (1<<2)
379
380#define S3C2440_DCON_CH0_I2SSDO (5<<24)
381#define S3C2440_DCON_CH0_PCMIN (6<<24)
382
383#define S3C2440_DCON_CH1_PCMOUT (5<<24)
384#define S3C2440_DCON_CH1_SDI (6<<24)
385
386#define S3C2440_DCON_CH2_PCMIN (5<<24)
387#define S3C2440_DCON_CH2_MICIN (6<<24)
388
389#define S3C2440_DCON_CH3_MICIN (5<<24)
390#define S3C2440_DCON_CH3_PCMOUT (6<<24)
391#endif
392
393#ifdef CONFIG_CPU_S3C2412
394
395#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
396
397#define S3C2412_DMAREQSEL_HW (1)
398
399#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
400#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
401#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
402#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
403#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
404#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
405#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
406#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
407#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
408#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
409#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
410#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
411#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
412#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
413#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
414#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
415#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
416#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
417#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
418#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
419
420#endif
421
422#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
423
424#define S3C2443_DMAREQSEL_HW (1)
425
426#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
427#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
428#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
429#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
430#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
431#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
432#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
433#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
434#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
435#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
436#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
437#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
438#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
439#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
440#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
441#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
442#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
443#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
444#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
445#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
446#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
447
448#endif /* __ASM_ARCH_DMA_H */ 197#endif /* __ASM_ARCH_DMA_H */