diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-08-05 11:14:15 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-08-07 04:55:48 -0400 |
commit | a09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch) | |
tree | 69689f467179891b498bd7423fcf61925173db31 /arch/arm/mach-s3c2410/include | |
parent | a1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff) |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410/include')
49 files changed, 5057 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h b/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h new file mode 100644 index 000000000000..1b614d5a81f3 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h | ||
2 | * | ||
3 | * Copyright (c) 2005 Simtec Electronics | ||
4 | * http://www.simtec.co.uk/products/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * ANUBIS - CPLD control constants | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_ANUBISCPLD_H | ||
15 | #define __ASM_ARCH_ANUBISCPLD_H | ||
16 | |||
17 | /* CTRL2 - NAND WP control, IDE Reset assert/check */ | ||
18 | |||
19 | #define ANUBIS_CTRL1_NANDSEL (0x3) | ||
20 | |||
21 | /* IDREG - revision */ | ||
22 | |||
23 | #define ANUBIS_IDREG_REVMASK (0x7) | ||
24 | |||
25 | #endif /* __ASM_ARCH_ANUBISCPLD_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h b/arch/arm/mach-s3c2410/include/mach/anubis-irq.h new file mode 100644 index 000000000000..a2a328134e34 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/anubis-irq.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/anubis-irq.h | ||
2 | * | ||
3 | * Copyright (c) 2005 Simtec Electronics | ||
4 | * http://www.simtec.co.uk/products/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * ANUBIS - IRQ Number definitions | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_ANUBISIRQ_H | ||
15 | #define __ASM_ARCH_ANUBISIRQ_H | ||
16 | |||
17 | #define IRQ_IDE0 IRQ_EINT2 | ||
18 | #define IRQ_IDE1 IRQ_EINT3 | ||
19 | #define IRQ_ASIX IRQ_EINT1 | ||
20 | |||
21 | #endif /* __ASM_ARCH_ANUBISIRQ_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-map.h b/arch/arm/mach-s3c2410/include/mach/anubis-map.h new file mode 100644 index 000000000000..c9deb3a5b2c3 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/anubis-map.h | |||
@@ -0,0 +1,38 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/anubis-map.h | ||
2 | * | ||
3 | * Copyright (c) 2005 Simtec Electronics | ||
4 | * http://www.simtec.co.uk/products/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * ANUBIS - Memory map definitions | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | /* needs arch/map.h including with this */ | ||
15 | |||
16 | #ifndef __ASM_ARCH_ANUBISMAP_H | ||
17 | #define __ASM_ARCH_ANUBISMAP_H | ||
18 | |||
19 | /* start peripherals off after the S3C2410 */ | ||
20 | |||
21 | #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) | ||
22 | |||
23 | #define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) | ||
24 | |||
25 | /* we put the CPLD registers next, to get them out of the way */ | ||
26 | |||
27 | #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */ | ||
28 | #define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) | ||
29 | |||
30 | #define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */ | ||
31 | #define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3<<23)) | ||
32 | |||
33 | #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) | ||
34 | #define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) | ||
35 | #define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000) | ||
36 | #define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000) | ||
37 | |||
38 | #endif /* __ASM_ARCH_ANUBISMAP_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/audio.h b/arch/arm/mach-s3c2410/include/mach/audio.h new file mode 100644 index 000000000000..de0e8da48bc3 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/audio.h | |||
@@ -0,0 +1,45 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/audio.h | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX - Audio platfrom_device info | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_AUDIO_H | ||
15 | #define __ASM_ARCH_AUDIO_H __FILE__ | ||
16 | |||
17 | /* struct s3c24xx_iis_ops | ||
18 | * | ||
19 | * called from the s3c24xx audio core to deal with the architecture | ||
20 | * or the codec's setup and control. | ||
21 | * | ||
22 | * the pointer to itself is passed through in case the caller wants to | ||
23 | * embed this in an larger structure for easy reference to it's context. | ||
24 | */ | ||
25 | |||
26 | struct s3c24xx_iis_ops { | ||
27 | struct module *owner; | ||
28 | |||
29 | int (*startup)(struct s3c24xx_iis_ops *me); | ||
30 | void (*shutdown)(struct s3c24xx_iis_ops *me); | ||
31 | int (*suspend)(struct s3c24xx_iis_ops *me); | ||
32 | int (*resume)(struct s3c24xx_iis_ops *me); | ||
33 | |||
34 | int (*open)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm); | ||
35 | int (*close)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm); | ||
36 | int (*prepare)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm, struct snd_pcm_runtime *rt); | ||
37 | }; | ||
38 | |||
39 | struct s3c24xx_platdata_iis { | ||
40 | const char *codec_clk; | ||
41 | struct s3c24xx_iis_ops *ops; | ||
42 | int (*match_dev)(struct device *dev); | ||
43 | }; | ||
44 | |||
45 | #endif /* __ASM_ARCH_AUDIO_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h new file mode 100644 index 000000000000..20493b048360 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h | |||
@@ -0,0 +1,53 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/bast-cpld.h | ||
2 | * | ||
3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * BAST - CPLD control constants | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_BASTCPLD_H | ||
14 | #define __ASM_ARCH_BASTCPLD_H | ||
15 | |||
16 | /* CTRL1 - Audio LR routing */ | ||
17 | |||
18 | #define BAST_CPLD_CTRL1_LRCOFF (0x00) | ||
19 | #define BAST_CPLD_CTRL1_LRCADC (0x01) | ||
20 | #define BAST_CPLD_CTRL1_LRCDAC (0x02) | ||
21 | #define BAST_CPLD_CTRL1_LRCARM (0x03) | ||
22 | #define BAST_CPLD_CTRL1_LRMASK (0x03) | ||
23 | |||
24 | /* CTRL2 - NAND WP control, IDE Reset assert/check */ | ||
25 | |||
26 | #define BAST_CPLD_CTRL2_WNAND (0x04) | ||
27 | #define BAST_CPLD_CTLR2_IDERST (0x08) | ||
28 | |||
29 | /* CTRL3 - rom write control, CPLD identity */ | ||
30 | |||
31 | #define BAST_CPLD_CTRL3_IDMASK (0x0e) | ||
32 | #define BAST_CPLD_CTRL3_ROMWEN (0x01) | ||
33 | |||
34 | /* CTRL4 - 8bit LCD interface control/status */ | ||
35 | |||
36 | #define BAST_CPLD_CTRL4_LLAT (0x01) | ||
37 | #define BAST_CPLD_CTRL4_LCDRW (0x02) | ||
38 | #define BAST_CPLD_CTRL4_LCDCMD (0x04) | ||
39 | #define BAST_CPLD_CTRL4_LCDE2 (0x01) | ||
40 | |||
41 | /* CTRL5 - DMA routing */ | ||
42 | |||
43 | #define BAST_CPLD_DMA0_PRIIDE (0<<0) | ||
44 | #define BAST_CPLD_DMA0_SECIDE (1<<0) | ||
45 | #define BAST_CPLD_DMA0_ISA15 (2<<0) | ||
46 | #define BAST_CPLD_DMA0_ISA36 (3<<0) | ||
47 | |||
48 | #define BAST_CPLD_DMA1_PRIIDE (0<<2) | ||
49 | #define BAST_CPLD_DMA1_SECIDE (1<<2) | ||
50 | #define BAST_CPLD_DMA1_ISA15 (2<<2) | ||
51 | #define BAST_CPLD_DMA1_ISA36 (3<<2) | ||
52 | |||
53 | #endif /* __ASM_ARCH_BASTCPLD_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-irq.h b/arch/arm/mach-s3c2410/include/mach/bast-irq.h new file mode 100644 index 000000000000..501c202b53cf --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/bast-irq.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/bast-irq.h | ||
2 | * | ||
3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Machine BAST - IRQ Number definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_BASTIRQ_H | ||
14 | #define __ASM_ARCH_BASTIRQ_H | ||
15 | |||
16 | /* irq numbers to onboard peripherals */ | ||
17 | |||
18 | #define IRQ_USBOC IRQ_EINT18 | ||
19 | #define IRQ_IDE0 IRQ_EINT16 | ||
20 | #define IRQ_IDE1 IRQ_EINT17 | ||
21 | #define IRQ_PCSERIAL1 IRQ_EINT15 | ||
22 | #define IRQ_PCSERIAL2 IRQ_EINT14 | ||
23 | #define IRQ_PCPARALLEL IRQ_EINT13 | ||
24 | #define IRQ_ASIX IRQ_EINT11 | ||
25 | #define IRQ_DM9000 IRQ_EINT10 | ||
26 | #define IRQ_ISA IRQ_EINT9 | ||
27 | #define IRQ_SMALERT IRQ_EINT8 | ||
28 | |||
29 | #endif /* __ASM_ARCH_BASTIRQ_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-map.h b/arch/arm/mach-s3c2410/include/mach/bast-map.h new file mode 100644 index 000000000000..c2c5baf07345 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/bast-map.h | |||
@@ -0,0 +1,146 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/bast-map.h | ||
2 | * | ||
3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Machine BAST - Memory map definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | /* needs arch/map.h including with this */ | ||
14 | |||
15 | /* ok, we've used up to 0x13000000, now we need to find space for the | ||
16 | * peripherals that live in the nGCS[x] areas, which are quite numerous | ||
17 | * in their space. We also have the board's CPLD to find register space | ||
18 | * for. | ||
19 | */ | ||
20 | |||
21 | #ifndef __ASM_ARCH_BASTMAP_H | ||
22 | #define __ASM_ARCH_BASTMAP_H | ||
23 | |||
24 | #define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) | ||
25 | |||
26 | /* we put the CPLD registers next, to get them out of the way */ | ||
27 | |||
28 | #define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */ | ||
29 | #define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000) | ||
30 | |||
31 | #define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */ | ||
32 | #define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000) | ||
33 | |||
34 | #define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */ | ||
35 | #define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000) | ||
36 | |||
37 | #define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */ | ||
38 | #define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000) | ||
39 | |||
40 | /* next, we have the PC104 ISA interrupt registers */ | ||
41 | |||
42 | #define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ | ||
43 | #define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000) | ||
44 | |||
45 | #define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ | ||
46 | #define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000) | ||
47 | |||
48 | #define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ | ||
49 | #define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000) | ||
50 | |||
51 | #define BAST_PA_LCD_RCMD1 (0x8800000) | ||
52 | #define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000) | ||
53 | |||
54 | #define BAST_PA_LCD_WCMD1 (0x8000000) | ||
55 | #define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000) | ||
56 | |||
57 | #define BAST_PA_LCD_RDATA1 (0x9800000) | ||
58 | #define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000) | ||
59 | |||
60 | #define BAST_PA_LCD_WDATA1 (0x9000000) | ||
61 | #define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000) | ||
62 | |||
63 | #define BAST_PA_LCD_RCMD2 (0xA800000) | ||
64 | #define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000) | ||
65 | |||
66 | #define BAST_PA_LCD_WCMD2 (0xA000000) | ||
67 | #define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000) | ||
68 | |||
69 | #define BAST_PA_LCD_RDATA2 (0xB800000) | ||
70 | #define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000) | ||
71 | |||
72 | #define BAST_PA_LCD_WDATA2 (0xB000000) | ||
73 | #define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000) | ||
74 | |||
75 | |||
76 | /* 0xE0000000 contains the IO space that is split by speed and | ||
77 | * wether the access is for 8 or 16bit IO... this ensures that | ||
78 | * the correct access is made | ||
79 | * | ||
80 | * 0x10000000 of space, partitioned as so: | ||
81 | * | ||
82 | * 0x00000000 to 0x04000000 8bit, slow | ||
83 | * 0x04000000 to 0x08000000 16bit, slow | ||
84 | * 0x08000000 to 0x0C000000 16bit, net | ||
85 | * 0x0C000000 to 0x10000000 16bit, fast | ||
86 | * | ||
87 | * each of these spaces has the following in: | ||
88 | * | ||
89 | * 0x00000000 to 0x01000000 16MB ISA IO space | ||
90 | * 0x01000000 to 0x02000000 16MB ISA memory space | ||
91 | * 0x02000000 to 0x02100000 1MB IDE primary channel | ||
92 | * 0x02100000 to 0x02200000 1MB IDE primary channel aux | ||
93 | * 0x02200000 to 0x02400000 1MB IDE secondary channel | ||
94 | * 0x02300000 to 0x02400000 1MB IDE secondary channel aux | ||
95 | * 0x02400000 to 0x02500000 1MB ASIX ethernet controller | ||
96 | * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller | ||
97 | * 0x02600000 to 0x02700000 1MB PC SuperIO controller | ||
98 | * | ||
99 | * the phyiscal layout of the zones are: | ||
100 | * nGCS2 - 8bit, slow | ||
101 | * nGCS3 - 16bit, slow | ||
102 | * nGCS4 - 16bit, net | ||
103 | * nGCS5 - 16bit, fast | ||
104 | */ | ||
105 | |||
106 | #define BAST_VA_MULTISPACE (0xE0000000) | ||
107 | |||
108 | #define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000) | ||
109 | #define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000) | ||
110 | #define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000) | ||
111 | #define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000) | ||
112 | #define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000) | ||
113 | #define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000) | ||
114 | #define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000) | ||
115 | #define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000) | ||
116 | #define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000) | ||
117 | |||
118 | #define BAST_VA_MULTISPACE (0xE0000000) | ||
119 | |||
120 | #define BAST_VAM_CS2 (0x00000000) | ||
121 | #define BAST_VAM_CS3 (0x04000000) | ||
122 | #define BAST_VAM_CS4 (0x08000000) | ||
123 | #define BAST_VAM_CS5 (0x0C000000) | ||
124 | |||
125 | /* physical offset addresses for the peripherals */ | ||
126 | |||
127 | #define BAST_PA_ISAIO (0x00000000) | ||
128 | #define BAST_PA_ASIXNET (0x01000000) | ||
129 | #define BAST_PA_SUPERIO (0x01800000) | ||
130 | #define BAST_PA_IDEPRI (0x02000000) | ||
131 | #define BAST_PA_IDEPRIAUX (0x02800000) | ||
132 | #define BAST_PA_IDESEC (0x03000000) | ||
133 | #define BAST_PA_IDESECAUX (0x03800000) | ||
134 | #define BAST_PA_ISAMEM (0x04000000) | ||
135 | #define BAST_PA_DM9000 (0x05000000) | ||
136 | |||
137 | /* some configurations for the peripherals */ | ||
138 | |||
139 | #define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2) | ||
140 | /* */ | ||
141 | |||
142 | #define BAST_ASIXNET_CS BAST_VAM_CS5 | ||
143 | #define BAST_IDE_CS BAST_VAM_CS5 | ||
144 | #define BAST_DM9000_CS BAST_VAM_CS4 | ||
145 | |||
146 | #endif /* __ASM_ARCH_BASTMAP_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h new file mode 100644 index 000000000000..61684cb8ce59 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/bast-pmu.h | ||
2 | * | ||
3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * Vincent Sanders <vince@simtec.co.uk> | ||
6 | * | ||
7 | * Machine BAST - Power Management chip | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_BASTPMU_H | ||
15 | #define __ASM_ARCH_BASTPMU_H "08_OCT_2004" | ||
16 | |||
17 | #define BASTPMU_REG_IDENT (0x00) | ||
18 | #define BASTPMU_REG_VERSION (0x01) | ||
19 | #define BASTPMU_REG_DDCCTRL (0x02) | ||
20 | #define BASTPMU_REG_POWER (0x03) | ||
21 | #define BASTPMU_REG_RESET (0x04) | ||
22 | #define BASTPMU_REG_GWO (0x05) | ||
23 | #define BASTPMU_REG_WOL (0x06) | ||
24 | #define BASTPMU_REG_WOR (0x07) | ||
25 | #define BASTPMU_REG_UID (0x09) | ||
26 | |||
27 | #define BASTPMU_EEPROM (0xC0) | ||
28 | |||
29 | #define BASTPMU_EEP_UID (BASTPMU_EEPROM + 0) | ||
30 | #define BASTPMU_EEP_WOL (BASTPMU_EEPROM + 8) | ||
31 | #define BASTPMU_EEP_WOR (BASTPMU_EEPROM + 9) | ||
32 | |||
33 | #define BASTPMU_IDENT_0 0x53 | ||
34 | #define BASTPMU_IDENT_1 0x42 | ||
35 | #define BASTPMU_IDENT_2 0x50 | ||
36 | #define BASTPMU_IDENT_3 0x4d | ||
37 | |||
38 | #define BASTPMU_RESET_GUARD (0x55) | ||
39 | |||
40 | #endif /* __ASM_ARCH_BASTPMU_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S new file mode 100644 index 000000000000..682df23087ab --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/debug-macro.S | |||
@@ -0,0 +1,102 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Debugging macro include header | ||
4 | * | ||
5 | * Copyright (C) 1994-1999 Russell King | ||
6 | * Copyright (C) 2005 Simtec Electronics | ||
7 | * | ||
8 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <mach/map.h> | ||
16 | #include <mach/regs-gpio.h> | ||
17 | #include <asm/plat-s3c/regs-serial.h> | ||
18 | |||
19 | #define S3C2410_UART1_OFF (0x4000) | ||
20 | #define SHIFT_2440TXF (14-9) | ||
21 | |||
22 | .macro addruart, rx | ||
23 | mrc p15, 0, \rx, c1, c0 | ||
24 | tst \rx, #1 | ||
25 | ldreq \rx, = S3C24XX_PA_UART | ||
26 | ldrne \rx, = S3C24XX_VA_UART | ||
27 | #if CONFIG_DEBUG_S3C_UART != 0 | ||
28 | add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) | ||
29 | #endif | ||
30 | .endm | ||
31 | |||
32 | .macro fifo_full_s3c24xx rd, rx | ||
33 | @ check for arm920 vs arm926. currently assume all arm926 | ||
34 | @ devices have an 64 byte FIFO identical to the s3c2440 | ||
35 | mrc p15, 0, \rd, c0, c0 | ||
36 | and \rd, \rd, #0xff0 | ||
37 | teq \rd, #0x260 | ||
38 | beq 1004f | ||
39 | mrc p15, 0, \rd, c1, c0 | ||
40 | tst \rd, #1 | ||
41 | addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) | ||
42 | addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) | ||
43 | bic \rd, \rd, #0xff000 | ||
44 | ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] | ||
45 | and \rd, \rd, #0x00ff0000 | ||
46 | teq \rd, #0x00440000 @ is it 2440? | ||
47 | 1004: | ||
48 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | ||
49 | moveq \rd, \rd, lsr #SHIFT_2440TXF | ||
50 | tst \rd, #S3C2410_UFSTAT_TXFULL | ||
51 | .endm | ||
52 | |||
53 | .macro fifo_full_s3c2410 rd, rx | ||
54 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | ||
55 | tst \rd, #S3C2410_UFSTAT_TXFULL | ||
56 | .endm | ||
57 | |||
58 | /* fifo level reading */ | ||
59 | |||
60 | .macro fifo_level_s3c24xx rd, rx | ||
61 | @ check for arm920 vs arm926. currently assume all arm926 | ||
62 | @ devices have an 64 byte FIFO identical to the s3c2440 | ||
63 | mrc p15, 0, \rd, c0, c0 | ||
64 | and \rd, \rd, #0xff0 | ||
65 | teq \rd, #0x260 | ||
66 | beq 10000f | ||
67 | mrc p15, 0, \rd, c1, c0 | ||
68 | tst \rd, #1 | ||
69 | addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) | ||
70 | addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) | ||
71 | bic \rd, \rd, #0xff000 | ||
72 | ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] | ||
73 | and \rd, \rd, #0x00ff0000 | ||
74 | teq \rd, #0x00440000 @ is it 2440? | ||
75 | |||
76 | 10000: | ||
77 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | ||
78 | andne \rd, \rd, #S3C2410_UFSTAT_TXMASK | ||
79 | andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK | ||
80 | .endm | ||
81 | |||
82 | .macro fifo_level_s3c2410 rd, rx | ||
83 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | ||
84 | and \rd, \rd, #S3C2410_UFSTAT_TXMASK | ||
85 | .endm | ||
86 | |||
87 | /* Select the correct implementation depending on the configuration. The | ||
88 | * S3C2440 will get selected by default, as these are the most widely | ||
89 | * used variants of these | ||
90 | */ | ||
91 | |||
92 | #if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY) | ||
93 | #define fifo_full fifo_full_s3c2410 | ||
94 | #define fifo_level fifo_level_s3c2410 | ||
95 | #elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY) | ||
96 | #define fifo_full fifo_full_s3c24xx | ||
97 | #define fifo_level fifo_level_s3c24xx | ||
98 | #endif | ||
99 | |||
100 | /* include the reset of the code which will do the work */ | ||
101 | |||
102 | #include <asm/plat-s3c/debug-macro.S> | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h new file mode 100644 index 000000000000..891b53cd69b8 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/dma.h | |||
@@ -0,0 +1,453 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/dma.h | ||
2 | * | ||
3 | * Copyright (C) 2003,2004,2006 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Samsung S3C241XX DMA support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_DMA_H | ||
14 | #define __ASM_ARCH_DMA_H __FILE__ | ||
15 | |||
16 | #include <linux/sysdev.h> | ||
17 | #include <mach/hardware.h> | ||
18 | |||
19 | /* | ||
20 | * This is the maximum DMA address(physical address) that can be DMAd to. | ||
21 | * | ||
22 | */ | ||
23 | #define MAX_DMA_ADDRESS 0x40000000 | ||
24 | #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ | ||
25 | |||
26 | /* We use `virtual` dma channels to hide the fact we have only a limited | ||
27 | * number of DMA channels, and not of all of them (dependant on the device) | ||
28 | * can be attached to any DMA source. We therefore let the DMA core handle | ||
29 | * the allocation of hardware channels to clients. | ||
30 | */ | ||
31 | |||
32 | enum dma_ch { | ||
33 | DMACH_XD0, | ||
34 | DMACH_XD1, | ||
35 | DMACH_SDI, | ||
36 | DMACH_SPI0, | ||
37 | DMACH_SPI1, | ||
38 | DMACH_UART0, | ||
39 | DMACH_UART1, | ||
40 | DMACH_UART2, | ||
41 | DMACH_TIMER, | ||
42 | DMACH_I2S_IN, | ||
43 | DMACH_I2S_OUT, | ||
44 | DMACH_PCM_IN, | ||
45 | DMACH_PCM_OUT, | ||
46 | DMACH_MIC_IN, | ||
47 | DMACH_USB_EP1, | ||
48 | DMACH_USB_EP2, | ||
49 | DMACH_USB_EP3, | ||
50 | DMACH_USB_EP4, | ||
51 | DMACH_UART0_SRC2, /* s3c2412 second uart sources */ | ||
52 | DMACH_UART1_SRC2, | ||
53 | DMACH_UART2_SRC2, | ||
54 | DMACH_UART3, /* s3c2443 has extra uart */ | ||
55 | DMACH_UART3_SRC2, | ||
56 | DMACH_MAX, /* the end entry */ | ||
57 | }; | ||
58 | |||
59 | #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ | ||
60 | |||
61 | /* we have 4 dma channels */ | ||
62 | #ifndef CONFIG_CPU_S3C2443 | ||
63 | #define S3C2410_DMA_CHANNELS (4) | ||
64 | #else | ||
65 | #define S3C2410_DMA_CHANNELS (6) | ||
66 | #endif | ||
67 | |||
68 | /* types */ | ||
69 | |||
70 | enum s3c2410_dma_state { | ||
71 | S3C2410_DMA_IDLE, | ||
72 | S3C2410_DMA_RUNNING, | ||
73 | S3C2410_DMA_PAUSED | ||
74 | }; | ||
75 | |||
76 | |||
77 | /* enum s3c2410_dma_loadst | ||
78 | * | ||
79 | * This represents the state of the DMA engine, wrt to the loaded / running | ||
80 | * transfers. Since we don't have any way of knowing exactly the state of | ||
81 | * the DMA transfers, we need to know the state to make decisions on wether | ||
82 | * we can | ||
83 | * | ||
84 | * S3C2410_DMA_NONE | ||
85 | * | ||
86 | * There are no buffers loaded (the channel should be inactive) | ||
87 | * | ||
88 | * S3C2410_DMA_1LOADED | ||
89 | * | ||
90 | * There is one buffer loaded, however it has not been confirmed to be | ||
91 | * loaded by the DMA engine. This may be because the channel is not | ||
92 | * yet running, or the DMA driver decided that it was too costly to | ||
93 | * sit and wait for it to happen. | ||
94 | * | ||
95 | * S3C2410_DMA_1RUNNING | ||
96 | * | ||
97 | * The buffer has been confirmed running, and not finisged | ||
98 | * | ||
99 | * S3C2410_DMA_1LOADED_1RUNNING | ||
100 | * | ||
101 | * There is a buffer waiting to be loaded by the DMA engine, and one | ||
102 | * currently running. | ||
103 | */ | ||
104 | |||
105 | enum s3c2410_dma_loadst { | ||
106 | S3C2410_DMALOAD_NONE, | ||
107 | S3C2410_DMALOAD_1LOADED, | ||
108 | S3C2410_DMALOAD_1RUNNING, | ||
109 | S3C2410_DMALOAD_1LOADED_1RUNNING, | ||
110 | }; | ||
111 | |||
112 | enum s3c2410_dma_buffresult { | ||
113 | S3C2410_RES_OK, | ||
114 | S3C2410_RES_ERR, | ||
115 | S3C2410_RES_ABORT | ||
116 | }; | ||
117 | |||
118 | enum s3c2410_dmasrc { | ||
119 | S3C2410_DMASRC_HW, /* source is memory */ | ||
120 | S3C2410_DMASRC_MEM /* source is hardware */ | ||
121 | }; | ||
122 | |||
123 | /* enum s3c2410_chan_op | ||
124 | * | ||
125 | * operation codes passed to the DMA code by the user, and also used | ||
126 | * to inform the current channel owner of any changes to the system state | ||
127 | */ | ||
128 | |||
129 | enum s3c2410_chan_op { | ||
130 | S3C2410_DMAOP_START, | ||
131 | S3C2410_DMAOP_STOP, | ||
132 | S3C2410_DMAOP_PAUSE, | ||
133 | S3C2410_DMAOP_RESUME, | ||
134 | S3C2410_DMAOP_FLUSH, | ||
135 | S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ | ||
136 | S3C2410_DMAOP_STARTED, /* indicate channel started */ | ||
137 | }; | ||
138 | |||
139 | /* flags */ | ||
140 | |||
141 | #define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about | ||
142 | * waiting for reloads */ | ||
143 | #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ | ||
144 | |||
145 | /* dma buffer */ | ||
146 | |||
147 | struct s3c2410_dma_client { | ||
148 | char *name; | ||
149 | }; | ||
150 | |||
151 | /* s3c2410_dma_buf_s | ||
152 | * | ||
153 | * internally used buffer structure to describe a queued or running | ||
154 | * buffer. | ||
155 | */ | ||
156 | |||
157 | struct s3c2410_dma_buf; | ||
158 | struct s3c2410_dma_buf { | ||
159 | struct s3c2410_dma_buf *next; | ||
160 | int magic; /* magic */ | ||
161 | int size; /* buffer size in bytes */ | ||
162 | dma_addr_t data; /* start of DMA data */ | ||
163 | dma_addr_t ptr; /* where the DMA got to [1] */ | ||
164 | void *id; /* client's id */ | ||
165 | }; | ||
166 | |||
167 | /* [1] is this updated for both recv/send modes? */ | ||
168 | |||
169 | struct s3c2410_dma_chan; | ||
170 | |||
171 | /* s3c2410_dma_cbfn_t | ||
172 | * | ||
173 | * buffer callback routine type | ||
174 | */ | ||
175 | |||
176 | typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *, | ||
177 | void *buf, int size, | ||
178 | enum s3c2410_dma_buffresult result); | ||
179 | |||
180 | typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *, | ||
181 | enum s3c2410_chan_op ); | ||
182 | |||
183 | struct s3c2410_dma_stats { | ||
184 | unsigned long loads; | ||
185 | unsigned long timeout_longest; | ||
186 | unsigned long timeout_shortest; | ||
187 | unsigned long timeout_avg; | ||
188 | unsigned long timeout_failed; | ||
189 | }; | ||
190 | |||
191 | struct s3c2410_dma_map; | ||
192 | |||
193 | /* struct s3c2410_dma_chan | ||
194 | * | ||
195 | * full state information for each DMA channel | ||
196 | */ | ||
197 | |||
198 | struct s3c2410_dma_chan { | ||
199 | /* channel state flags and information */ | ||
200 | unsigned char number; /* number of this dma channel */ | ||
201 | unsigned char in_use; /* channel allocated */ | ||
202 | unsigned char irq_claimed; /* irq claimed for channel */ | ||
203 | unsigned char irq_enabled; /* irq enabled for channel */ | ||
204 | unsigned char xfer_unit; /* size of an transfer */ | ||
205 | |||
206 | /* channel state */ | ||
207 | |||
208 | enum s3c2410_dma_state state; | ||
209 | enum s3c2410_dma_loadst load_state; | ||
210 | struct s3c2410_dma_client *client; | ||
211 | |||
212 | /* channel configuration */ | ||
213 | enum s3c2410_dmasrc source; | ||
214 | unsigned long dev_addr; | ||
215 | unsigned long load_timeout; | ||
216 | unsigned int flags; /* channel flags */ | ||
217 | unsigned int hw_cfg; /* last hw config */ | ||
218 | |||
219 | struct s3c24xx_dma_map *map; /* channel hw maps */ | ||
220 | |||
221 | /* channel's hardware position and configuration */ | ||
222 | void __iomem *regs; /* channels registers */ | ||
223 | void __iomem *addr_reg; /* data address register */ | ||
224 | unsigned int irq; /* channel irq */ | ||
225 | unsigned long dcon; /* default value of DCON */ | ||
226 | |||
227 | /* driver handles */ | ||
228 | s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ | ||
229 | s3c2410_dma_opfn_t op_fn; /* channel op callback */ | ||
230 | |||
231 | /* stats gathering */ | ||
232 | struct s3c2410_dma_stats *stats; | ||
233 | struct s3c2410_dma_stats stats_store; | ||
234 | |||
235 | /* buffer list and information */ | ||
236 | struct s3c2410_dma_buf *curr; /* current dma buffer */ | ||
237 | struct s3c2410_dma_buf *next; /* next buffer to load */ | ||
238 | struct s3c2410_dma_buf *end; /* end of queue */ | ||
239 | |||
240 | /* system device */ | ||
241 | struct sys_device dev; | ||
242 | }; | ||
243 | |||
244 | /* the currently allocated channel information */ | ||
245 | extern struct s3c2410_dma_chan s3c2410_chans[]; | ||
246 | |||
247 | /* note, we don't really use dma_device_t at the moment */ | ||
248 | typedef unsigned long dma_device_t; | ||
249 | |||
250 | /* functions --------------------------------------------------------------- */ | ||
251 | |||
252 | /* s3c2410_dma_request | ||
253 | * | ||
254 | * request a dma channel exclusivley | ||
255 | */ | ||
256 | |||
257 | extern int s3c2410_dma_request(dmach_t channel, | ||
258 | struct s3c2410_dma_client *, void *dev); | ||
259 | |||
260 | |||
261 | /* s3c2410_dma_ctrl | ||
262 | * | ||
263 | * change the state of the dma channel | ||
264 | */ | ||
265 | |||
266 | extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op); | ||
267 | |||
268 | /* s3c2410_dma_setflags | ||
269 | * | ||
270 | * set the channel's flags to a given state | ||
271 | */ | ||
272 | |||
273 | extern int s3c2410_dma_setflags(dmach_t channel, | ||
274 | unsigned int flags); | ||
275 | |||
276 | /* s3c2410_dma_free | ||
277 | * | ||
278 | * free the dma channel (will also abort any outstanding operations) | ||
279 | */ | ||
280 | |||
281 | extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *); | ||
282 | |||
283 | /* s3c2410_dma_enqueue | ||
284 | * | ||
285 | * place the given buffer onto the queue of operations for the channel. | ||
286 | * The buffer must be allocated from dma coherent memory, or the Dcache/WB | ||
287 | * drained before the buffer is given to the DMA system. | ||
288 | */ | ||
289 | |||
290 | extern int s3c2410_dma_enqueue(dmach_t channel, void *id, | ||
291 | dma_addr_t data, int size); | ||
292 | |||
293 | /* s3c2410_dma_config | ||
294 | * | ||
295 | * configure the dma channel | ||
296 | */ | ||
297 | |||
298 | extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon); | ||
299 | |||
300 | /* s3c2410_dma_devconfig | ||
301 | * | ||
302 | * configure the device we're talking to | ||
303 | */ | ||
304 | |||
305 | extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, | ||
306 | int hwcfg, unsigned long devaddr); | ||
307 | |||
308 | /* s3c2410_dma_getposition | ||
309 | * | ||
310 | * get the position that the dma transfer is currently at | ||
311 | */ | ||
312 | |||
313 | extern int s3c2410_dma_getposition(dmach_t channel, | ||
314 | dma_addr_t *src, dma_addr_t *dest); | ||
315 | |||
316 | extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn); | ||
317 | extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); | ||
318 | |||
319 | /* DMA Register definitions */ | ||
320 | |||
321 | #define S3C2410_DMA_DISRC (0x00) | ||
322 | #define S3C2410_DMA_DISRCC (0x04) | ||
323 | #define S3C2410_DMA_DIDST (0x08) | ||
324 | #define S3C2410_DMA_DIDSTC (0x0C) | ||
325 | #define S3C2410_DMA_DCON (0x10) | ||
326 | #define S3C2410_DMA_DSTAT (0x14) | ||
327 | #define S3C2410_DMA_DCSRC (0x18) | ||
328 | #define S3C2410_DMA_DCDST (0x1C) | ||
329 | #define S3C2410_DMA_DMASKTRIG (0x20) | ||
330 | #define S3C2412_DMA_DMAREQSEL (0x24) | ||
331 | #define S3C2443_DMA_DMAREQSEL (0x24) | ||
332 | |||
333 | #define S3C2410_DISRCC_INC (1<<0) | ||
334 | #define S3C2410_DISRCC_APB (1<<1) | ||
335 | |||
336 | #define S3C2410_DMASKTRIG_STOP (1<<2) | ||
337 | #define S3C2410_DMASKTRIG_ON (1<<1) | ||
338 | #define S3C2410_DMASKTRIG_SWTRIG (1<<0) | ||
339 | |||
340 | #define S3C2410_DCON_DEMAND (0<<31) | ||
341 | #define S3C2410_DCON_HANDSHAKE (1<<31) | ||
342 | #define S3C2410_DCON_SYNC_PCLK (0<<30) | ||
343 | #define S3C2410_DCON_SYNC_HCLK (1<<30) | ||
344 | |||
345 | #define S3C2410_DCON_INTREQ (1<<29) | ||
346 | |||
347 | #define S3C2410_DCON_CH0_XDREQ0 (0<<24) | ||
348 | #define S3C2410_DCON_CH0_UART0 (1<<24) | ||
349 | #define S3C2410_DCON_CH0_SDI (2<<24) | ||
350 | #define S3C2410_DCON_CH0_TIMER (3<<24) | ||
351 | #define S3C2410_DCON_CH0_USBEP1 (4<<24) | ||
352 | |||
353 | #define S3C2410_DCON_CH1_XDREQ1 (0<<24) | ||
354 | #define S3C2410_DCON_CH1_UART1 (1<<24) | ||
355 | #define S3C2410_DCON_CH1_I2SSDI (2<<24) | ||
356 | #define S3C2410_DCON_CH1_SPI (3<<24) | ||
357 | #define S3C2410_DCON_CH1_USBEP2 (4<<24) | ||
358 | |||
359 | #define S3C2410_DCON_CH2_I2SSDO (0<<24) | ||
360 | #define S3C2410_DCON_CH2_I2SSDI (1<<24) | ||
361 | #define S3C2410_DCON_CH2_SDI (2<<24) | ||
362 | #define S3C2410_DCON_CH2_TIMER (3<<24) | ||
363 | #define S3C2410_DCON_CH2_USBEP3 (4<<24) | ||
364 | |||
365 | #define S3C2410_DCON_CH3_UART2 (0<<24) | ||
366 | #define S3C2410_DCON_CH3_SDI (1<<24) | ||
367 | #define S3C2410_DCON_CH3_SPI (2<<24) | ||
368 | #define S3C2410_DCON_CH3_TIMER (3<<24) | ||
369 | #define S3C2410_DCON_CH3_USBEP4 (4<<24) | ||
370 | |||
371 | #define S3C2410_DCON_SRCSHIFT (24) | ||
372 | #define S3C2410_DCON_SRCMASK (7<<24) | ||
373 | |||
374 | #define S3C2410_DCON_BYTE (0<<20) | ||
375 | #define S3C2410_DCON_HALFWORD (1<<20) | ||
376 | #define S3C2410_DCON_WORD (2<<20) | ||
377 | |||
378 | #define S3C2410_DCON_AUTORELOAD (0<<22) | ||
379 | #define S3C2410_DCON_NORELOAD (1<<22) | ||
380 | #define S3C2410_DCON_HWTRIG (1<<23) | ||
381 | |||
382 | #ifdef CONFIG_CPU_S3C2440 | ||
383 | #define S3C2440_DIDSTC_CHKINT (1<<2) | ||
384 | |||
385 | #define S3C2440_DCON_CH0_I2SSDO (5<<24) | ||
386 | #define S3C2440_DCON_CH0_PCMIN (6<<24) | ||
387 | |||
388 | #define S3C2440_DCON_CH1_PCMOUT (5<<24) | ||
389 | #define S3C2440_DCON_CH1_SDI (6<<24) | ||
390 | |||
391 | #define S3C2440_DCON_CH2_PCMIN (5<<24) | ||
392 | #define S3C2440_DCON_CH2_MICIN (6<<24) | ||
393 | |||
394 | #define S3C2440_DCON_CH3_MICIN (5<<24) | ||
395 | #define S3C2440_DCON_CH3_PCMOUT (6<<24) | ||
396 | #endif | ||
397 | |||
398 | #ifdef CONFIG_CPU_S3C2412 | ||
399 | |||
400 | #define S3C2412_DMAREQSEL_SRC(x) ((x)<<1) | ||
401 | |||
402 | #define S3C2412_DMAREQSEL_HW (1) | ||
403 | |||
404 | #define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0) | ||
405 | #define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1) | ||
406 | #define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2) | ||
407 | #define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3) | ||
408 | #define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4) | ||
409 | #define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5) | ||
410 | #define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9) | ||
411 | #define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10) | ||
412 | #define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13) | ||
413 | #define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14) | ||
414 | #define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15) | ||
415 | #define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16) | ||
416 | #define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17) | ||
417 | #define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18) | ||
418 | #define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19) | ||
419 | #define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20) | ||
420 | #define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21) | ||
421 | #define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) | ||
422 | #define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) | ||
423 | #define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) | ||
424 | |||
425 | #endif | ||
426 | |||
427 | #define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) | ||
428 | |||
429 | #define S3C2443_DMAREQSEL_HW (1) | ||
430 | |||
431 | #define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0) | ||
432 | #define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1) | ||
433 | #define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2) | ||
434 | #define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3) | ||
435 | #define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4) | ||
436 | #define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5) | ||
437 | #define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9) | ||
438 | #define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10) | ||
439 | #define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17) | ||
440 | #define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18) | ||
441 | #define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19) | ||
442 | #define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20) | ||
443 | #define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21) | ||
444 | #define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22) | ||
445 | #define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23) | ||
446 | #define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24) | ||
447 | #define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) | ||
448 | #define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) | ||
449 | #define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) | ||
450 | #define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) | ||
451 | #define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) | ||
452 | |||
453 | #endif /* __ASM_ARCH_DMA_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/entry-macro.S b/arch/arm/mach-s3c2410/include/mach/entry-macro.S new file mode 100644 index 000000000000..473b3cd37d9b --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/entry-macro.S | |||
@@ -0,0 +1,78 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-s3c2410/include/mach/entry-macro.S | ||
3 | * | ||
4 | * Low-level IRQ helper macros for S3C2410-based platforms | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | /* We have a problem that the INTOFFSET register does not always | ||
12 | * show one interrupt. Occasionally we get two interrupts through | ||
13 | * the prioritiser, and this causes the INTOFFSET register to show | ||
14 | * what looks like the logical-or of the two interrupt numbers. | ||
15 | * | ||
16 | * Thanks to Klaus, Shannon, et al for helping to debug this problem | ||
17 | */ | ||
18 | |||
19 | #define INTPND (0x10) | ||
20 | #define INTOFFSET (0x14) | ||
21 | |||
22 | #include <mach/hardware.h> | ||
23 | #include <asm/irq.h> | ||
24 | |||
25 | .macro get_irqnr_preamble, base, tmp | ||
26 | .endm | ||
27 | |||
28 | .macro arch_ret_to_user, tmp1, tmp2 | ||
29 | .endm | ||
30 | |||
31 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
32 | |||
33 | mov \base, #S3C24XX_VA_IRQ | ||
34 | |||
35 | @@ try the interrupt offset register, since it is there | ||
36 | |||
37 | ldr \irqstat, [ \base, #INTPND ] | ||
38 | teq \irqstat, #0 | ||
39 | beq 1002f | ||
40 | ldr \irqnr, [ \base, #INTOFFSET ] | ||
41 | mov \tmp, #1 | ||
42 | tst \irqstat, \tmp, lsl \irqnr | ||
43 | bne 1001f | ||
44 | |||
45 | @@ the number specified is not a valid irq, so try | ||
46 | @@ and work it out for ourselves | ||
47 | |||
48 | mov \irqnr, #0 @@ start here | ||
49 | |||
50 | @@ work out which irq (if any) we got | ||
51 | |||
52 | movs \tmp, \irqstat, lsl#16 | ||
53 | addeq \irqnr, \irqnr, #16 | ||
54 | moveq \irqstat, \irqstat, lsr#16 | ||
55 | tst \irqstat, #0xff | ||
56 | addeq \irqnr, \irqnr, #8 | ||
57 | moveq \irqstat, \irqstat, lsr#8 | ||
58 | tst \irqstat, #0xf | ||
59 | addeq \irqnr, \irqnr, #4 | ||
60 | moveq \irqstat, \irqstat, lsr#4 | ||
61 | tst \irqstat, #0x3 | ||
62 | addeq \irqnr, \irqnr, #2 | ||
63 | moveq \irqstat, \irqstat, lsr#2 | ||
64 | tst \irqstat, #0x1 | ||
65 | addeq \irqnr, \irqnr, #1 | ||
66 | |||
67 | @@ we have the value | ||
68 | 1001: | ||
69 | adds \irqnr, \irqnr, #IRQ_EINT0 | ||
70 | 1002: | ||
71 | @@ exit here, Z flag unset if IRQ | ||
72 | |||
73 | .endm | ||
74 | |||
75 | /* currently don't need an disable_fiq macro */ | ||
76 | |||
77 | .macro disable_fiq | ||
78 | .endm | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/fb.h b/arch/arm/mach-s3c2410/include/mach/fb.h new file mode 100644 index 000000000000..eee0654eb8fb --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/fb.h | |||
@@ -0,0 +1,74 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/fb.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org> | ||
4 | * | ||
5 | * Inspired by pxafb.h | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARM_FB_H | ||
13 | #define __ASM_ARM_FB_H | ||
14 | |||
15 | #include <mach/regs-lcd.h> | ||
16 | |||
17 | struct s3c2410fb_hw { | ||
18 | unsigned long lcdcon1; | ||
19 | unsigned long lcdcon2; | ||
20 | unsigned long lcdcon3; | ||
21 | unsigned long lcdcon4; | ||
22 | unsigned long lcdcon5; | ||
23 | }; | ||
24 | |||
25 | /* LCD description */ | ||
26 | struct s3c2410fb_display { | ||
27 | /* LCD type */ | ||
28 | unsigned type; | ||
29 | |||
30 | /* Screen size */ | ||
31 | unsigned short width; | ||
32 | unsigned short height; | ||
33 | |||
34 | /* Screen info */ | ||
35 | unsigned short xres; | ||
36 | unsigned short yres; | ||
37 | unsigned short bpp; | ||
38 | |||
39 | unsigned pixclock; /* pixclock in picoseconds */ | ||
40 | unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */ | ||
41 | unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */ | ||
42 | unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */ | ||
43 | unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */ | ||
44 | unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */ | ||
45 | unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */ | ||
46 | |||
47 | /* lcd configuration registers */ | ||
48 | unsigned long lcdcon5; | ||
49 | }; | ||
50 | |||
51 | struct s3c2410fb_mach_info { | ||
52 | |||
53 | struct s3c2410fb_display *displays; /* attached diplays info */ | ||
54 | unsigned num_displays; /* number of defined displays */ | ||
55 | unsigned default_display; | ||
56 | |||
57 | /* GPIOs */ | ||
58 | |||
59 | unsigned long gpcup; | ||
60 | unsigned long gpcup_mask; | ||
61 | unsigned long gpccon; | ||
62 | unsigned long gpccon_mask; | ||
63 | unsigned long gpdup; | ||
64 | unsigned long gpdup_mask; | ||
65 | unsigned long gpdcon; | ||
66 | unsigned long gpdcon_mask; | ||
67 | |||
68 | /* lpc3600 control register */ | ||
69 | unsigned long lpcsel; | ||
70 | }; | ||
71 | |||
72 | extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *); | ||
73 | |||
74 | #endif /* __ASM_ARM_FB_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h new file mode 100644 index 000000000000..3b52b86498a6 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/gpio.h | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C2410 - GPIO lib support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #define gpio_get_value __gpio_get_value | ||
15 | #define gpio_set_value __gpio_set_value | ||
16 | #define gpio_cansleep __gpio_cansleep | ||
17 | |||
18 | #include <asm-generic/gpio.h> | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h new file mode 100644 index 000000000000..d8a832729a8a --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h | |||
@@ -0,0 +1,64 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/h1940-latch.h | ||
2 | * | ||
3 | * Copyright (c) 2005 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * iPAQ H1940 series - latch definitions | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_H1940_LATCH_H | ||
15 | #define __ASM_ARCH_H1940_LATCH_H | ||
16 | |||
17 | |||
18 | #ifndef __ASSEMBLY__ | ||
19 | #define H1940_LATCH ((void __force __iomem *)0xF8000000) | ||
20 | #else | ||
21 | #define H1940_LATCH 0xF8000000 | ||
22 | #endif | ||
23 | |||
24 | #define H1940_PA_LATCH (S3C2410_CS2) | ||
25 | |||
26 | /* SD layer latch */ | ||
27 | |||
28 | #define H1940_LATCH_SDQ1 (1<<16) | ||
29 | #define H1940_LATCH_LCD_P1 (1<<17) | ||
30 | #define H1940_LATCH_LCD_P2 (1<<18) | ||
31 | #define H1940_LATCH_LCD_P3 (1<<19) | ||
32 | #define H1940_LATCH_MAX1698_nSHUTDOWN (1<<20) /* LCD backlight */ | ||
33 | #define H1940_LATCH_LED_RED (1<<21) | ||
34 | #define H1940_LATCH_SDQ7 (1<<22) | ||
35 | #define H1940_LATCH_USB_DP (1<<23) | ||
36 | |||
37 | /* CPU layer latch */ | ||
38 | |||
39 | #define H1940_LATCH_UDA_POWER (1<<24) | ||
40 | #define H1940_LATCH_AUDIO_POWER (1<<25) | ||
41 | #define H1940_LATCH_SM803_ENABLE (1<<26) | ||
42 | #define H1940_LATCH_LCD_P4 (1<<27) | ||
43 | #define H1940_LATCH_CPUQ5 (1<<28) /* untraced */ | ||
44 | #define H1940_LATCH_BLUETOOTH_POWER (1<<29) /* active high */ | ||
45 | #define H1940_LATCH_LED_GREEN (1<<30) | ||
46 | #define H1940_LATCH_LED_FLASH (1<<31) | ||
47 | |||
48 | /* default settings */ | ||
49 | |||
50 | #define H1940_LATCH_DEFAULT \ | ||
51 | H1940_LATCH_LCD_P4 | \ | ||
52 | H1940_LATCH_SM803_ENABLE | \ | ||
53 | H1940_LATCH_SDQ1 | \ | ||
54 | H1940_LATCH_LCD_P1 | \ | ||
55 | H1940_LATCH_LCD_P2 | \ | ||
56 | H1940_LATCH_LCD_P3 | \ | ||
57 | H1940_LATCH_MAX1698_nSHUTDOWN | \ | ||
58 | H1940_LATCH_CPUQ5 | ||
59 | |||
60 | /* control functions */ | ||
61 | |||
62 | extern void h1940_latch_control(unsigned int clear, unsigned int set); | ||
63 | |||
64 | #endif /* __ASM_ARCH_H1940_LATCH_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940.h b/arch/arm/mach-s3c2410/include/mach/h1940.h new file mode 100644 index 000000000000..4559784129c0 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/h1940.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/h1940.h | ||
2 | * | ||
3 | * Copyright 2006 Ben Dooks <ben-linux@fluff.org> | ||
4 | * | ||
5 | * H1940 definitions | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_H1940_H | ||
13 | #define __ASM_ARCH_H1940_H | ||
14 | |||
15 | #define H1940_SUSPEND_CHECKSUM (0x30003ff8) | ||
16 | #define H1940_SUSPEND_RESUMEAT (0x30081000) | ||
17 | #define H1940_SUSPEND_CHECK (0x30080000) | ||
18 | |||
19 | extern void h1940_pm_return(void); | ||
20 | |||
21 | #endif /* __ASM_ARCH_H1940_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h new file mode 100644 index 000000000000..74d5a1a4024c --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/hardware.h | |||
@@ -0,0 +1,137 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/hardware.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - hardware | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_HARDWARE_H | ||
14 | #define __ASM_ARCH_HARDWARE_H | ||
15 | |||
16 | #ifndef __ASSEMBLY__ | ||
17 | |||
18 | /* external functions for GPIO support | ||
19 | * | ||
20 | * These allow various different clients to access the same GPIO | ||
21 | * registers without conflicting. If your driver only owns the entire | ||
22 | * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. | ||
23 | */ | ||
24 | |||
25 | /* s3c2410_gpio_cfgpin | ||
26 | * | ||
27 | * set the configuration of the given pin to the value passed. | ||
28 | * | ||
29 | * eg: | ||
30 | * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); | ||
31 | * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); | ||
32 | */ | ||
33 | |||
34 | extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); | ||
35 | |||
36 | extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); | ||
37 | |||
38 | /* s3c2410_gpio_getirq | ||
39 | * | ||
40 | * turn the given pin number into the corresponding IRQ number | ||
41 | * | ||
42 | * returns: | ||
43 | * < 0 = no interrupt for this pin | ||
44 | * >=0 = interrupt number for the pin | ||
45 | */ | ||
46 | |||
47 | extern int s3c2410_gpio_getirq(unsigned int pin); | ||
48 | |||
49 | /* s3c2410_gpio_irq2pin | ||
50 | * | ||
51 | * turn the given irq number into the corresponding GPIO number | ||
52 | * | ||
53 | * returns: | ||
54 | * < 0 = no pin | ||
55 | * >=0 = gpio pin number | ||
56 | */ | ||
57 | |||
58 | extern int s3c2410_gpio_irq2pin(unsigned int irq); | ||
59 | |||
60 | #ifdef CONFIG_CPU_S3C2400 | ||
61 | |||
62 | extern int s3c2400_gpio_getirq(unsigned int pin); | ||
63 | |||
64 | #endif /* CONFIG_CPU_S3C2400 */ | ||
65 | |||
66 | /* s3c2410_gpio_irqfilter | ||
67 | * | ||
68 | * set the irq filtering on the given pin | ||
69 | * | ||
70 | * on = 0 => disable filtering | ||
71 | * 1 => enable filtering | ||
72 | * | ||
73 | * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with | ||
74 | * width of filter (0 through 63) | ||
75 | * | ||
76 | * | ||
77 | */ | ||
78 | |||
79 | extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, | ||
80 | unsigned int config); | ||
81 | |||
82 | /* s3c2410_gpio_pullup | ||
83 | * | ||
84 | * configure the pull-up control on the given pin | ||
85 | * | ||
86 | * to = 1 => disable the pull-up | ||
87 | * 0 => enable the pull-up | ||
88 | * | ||
89 | * eg; | ||
90 | * | ||
91 | * s3c2410_gpio_pullup(S3C2410_GPB0, 0); | ||
92 | * s3c2410_gpio_pullup(S3C2410_GPE8, 0); | ||
93 | */ | ||
94 | |||
95 | extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); | ||
96 | |||
97 | /* s3c2410_gpio_getpull | ||
98 | * | ||
99 | * Read the state of the pull-up on a given pin | ||
100 | * | ||
101 | * return: | ||
102 | * < 0 => error code | ||
103 | * 0 => enabled | ||
104 | * 1 => disabled | ||
105 | */ | ||
106 | |||
107 | extern int s3c2410_gpio_getpull(unsigned int pin); | ||
108 | |||
109 | extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); | ||
110 | |||
111 | extern unsigned int s3c2410_gpio_getpin(unsigned int pin); | ||
112 | |||
113 | extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); | ||
114 | |||
115 | #ifdef CONFIG_CPU_S3C2440 | ||
116 | |||
117 | extern int s3c2440_set_dsc(unsigned int pin, unsigned int value); | ||
118 | |||
119 | #endif /* CONFIG_CPU_S3C2440 */ | ||
120 | |||
121 | #ifdef CONFIG_CPU_S3C2412 | ||
122 | |||
123 | extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state); | ||
124 | |||
125 | #endif /* CONFIG_CPU_S3C2412 */ | ||
126 | |||
127 | #endif /* __ASSEMBLY__ */ | ||
128 | |||
129 | #include <asm/sizes.h> | ||
130 | #include <mach/map.h> | ||
131 | |||
132 | /* machine specific hardware definitions should go after this */ | ||
133 | |||
134 | /* currently here until moved into config (todo) */ | ||
135 | #define CONFIG_NO_MULTIWORD_IO | ||
136 | |||
137 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/idle.h b/arch/arm/mach-s3c2410/include/mach/idle.h new file mode 100644 index 000000000000..e9ddd706b16e --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/idle.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/idle.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 CPU Idle controls | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_IDLE_H | ||
14 | #define __ASM_ARCH_IDLE_H __FILE__ | ||
15 | |||
16 | /* This allows the over-ride of the default idle code, in case there | ||
17 | * is any other things to be done over idle (like DVS) | ||
18 | */ | ||
19 | |||
20 | extern void (*s3c24xx_idle)(void); | ||
21 | |||
22 | extern void s3c24xx_default_idle(void); | ||
23 | |||
24 | #endif /* __ASM_ARCH_IDLE_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c2410/include/mach/io.h new file mode 100644 index 000000000000..9813dbf2ae4f --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/io.h | |||
@@ -0,0 +1,218 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-s3c2410/include/mach/io.h | ||
3 | * from arch/arm/mach-rpc/include/mach/io.h | ||
4 | * | ||
5 | * Copyright (C) 1997 Russell King | ||
6 | * (C) 2003 Simtec Electronics | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARM_ARCH_IO_H | ||
10 | #define __ASM_ARM_ARCH_IO_H | ||
11 | |||
12 | #include <mach/hardware.h> | ||
13 | |||
14 | #define IO_SPACE_LIMIT 0xffffffff | ||
15 | |||
16 | /* | ||
17 | * We use two different types of addressing - PC style addresses, and ARM | ||
18 | * addresses. PC style accesses the PC hardware with the normal PC IO | ||
19 | * addresses, eg 0x3f8 for serial#1. ARM addresses are above A28 | ||
20 | * and are translated to the start of IO. Note that all addresses are | ||
21 | * not shifted left! | ||
22 | */ | ||
23 | |||
24 | #define __PORT_PCIO(x) ((x) < (1<<28)) | ||
25 | |||
26 | #define PCIO_BASE (S3C24XX_VA_ISA_WORD) | ||
27 | #define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE) | ||
28 | #define PCIO_BASE_w (S3C24XX_VA_ISA_WORD) | ||
29 | #define PCIO_BASE_l (S3C24XX_VA_ISA_WORD) | ||
30 | /* | ||
31 | * Dynamic IO functions - let the compiler | ||
32 | * optimize the expressions | ||
33 | */ | ||
34 | |||
35 | #define DECLARE_DYN_OUT(sz,fnsuffix,instr) \ | ||
36 | static inline void __out##fnsuffix (unsigned int val, unsigned int port) \ | ||
37 | { \ | ||
38 | unsigned long temp; \ | ||
39 | __asm__ __volatile__( \ | ||
40 | "cmp %2, #(1<<28)\n\t" \ | ||
41 | "mov %0, %2\n\t" \ | ||
42 | "addcc %0, %0, %3\n\t" \ | ||
43 | "str" instr " %1, [%0, #0 ] @ out" #fnsuffix \ | ||
44 | : "=&r" (temp) \ | ||
45 | : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ | ||
46 | : "cc"); \ | ||
47 | } | ||
48 | |||
49 | |||
50 | #define DECLARE_DYN_IN(sz,fnsuffix,instr) \ | ||
51 | static inline unsigned sz __in##fnsuffix (unsigned int port) \ | ||
52 | { \ | ||
53 | unsigned long temp, value; \ | ||
54 | __asm__ __volatile__( \ | ||
55 | "cmp %2, #(1<<28)\n\t" \ | ||
56 | "mov %0, %2\n\t" \ | ||
57 | "addcc %0, %0, %3\n\t" \ | ||
58 | "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \ | ||
59 | : "=&r" (temp), "=r" (value) \ | ||
60 | : "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ | ||
61 | : "cc"); \ | ||
62 | return (unsigned sz)value; \ | ||
63 | } | ||
64 | |||
65 | static inline void __iomem *__ioaddr (unsigned long port) | ||
66 | { | ||
67 | return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port; | ||
68 | } | ||
69 | |||
70 | #define DECLARE_IO(sz,fnsuffix,instr) \ | ||
71 | DECLARE_DYN_IN(sz,fnsuffix,instr) \ | ||
72 | DECLARE_DYN_OUT(sz,fnsuffix,instr) | ||
73 | |||
74 | DECLARE_IO(char,b,"b") | ||
75 | DECLARE_IO(short,w,"h") | ||
76 | DECLARE_IO(int,l,"") | ||
77 | |||
78 | #undef DECLARE_IO | ||
79 | #undef DECLARE_DYN_IN | ||
80 | |||
81 | /* | ||
82 | * Constant address IO functions | ||
83 | * | ||
84 | * These have to be macros for the 'J' constraint to work - | ||
85 | * +/-4096 immediate operand. | ||
86 | */ | ||
87 | #define __outbc(value,port) \ | ||
88 | ({ \ | ||
89 | if (__PORT_PCIO((port))) \ | ||
90 | __asm__ __volatile__( \ | ||
91 | "strb %0, [%1, %2] @ outbc" \ | ||
92 | : : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \ | ||
93 | else \ | ||
94 | __asm__ __volatile__( \ | ||
95 | "strb %0, [%1, #0] @ outbc" \ | ||
96 | : : "r" (value), "r" ((port))); \ | ||
97 | }) | ||
98 | |||
99 | #define __inbc(port) \ | ||
100 | ({ \ | ||
101 | unsigned char result; \ | ||
102 | if (__PORT_PCIO((port))) \ | ||
103 | __asm__ __volatile__( \ | ||
104 | "ldrb %0, [%1, %2] @ inbc" \ | ||
105 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ | ||
106 | else \ | ||
107 | __asm__ __volatile__( \ | ||
108 | "ldrb %0, [%1, #0] @ inbc" \ | ||
109 | : "=r" (result) : "r" ((port))); \ | ||
110 | result; \ | ||
111 | }) | ||
112 | |||
113 | #define __outwc(value,port) \ | ||
114 | ({ \ | ||
115 | unsigned long v = value; \ | ||
116 | if (__PORT_PCIO((port))) { \ | ||
117 | if ((port) < 256 && (port) > -256) \ | ||
118 | __asm__ __volatile__( \ | ||
119 | "strh %0, [%1, %2] @ outwc" \ | ||
120 | : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ | ||
121 | else if ((port) > 0) \ | ||
122 | __asm__ __volatile__( \ | ||
123 | "strh %0, [%1, %2] @ outwc" \ | ||
124 | : : "r" (v), \ | ||
125 | "r" (PCIO_BASE + ((port) & ~0xff)), \ | ||
126 | "Jr" (((port) & 0xff))); \ | ||
127 | else \ | ||
128 | __asm__ __volatile__( \ | ||
129 | "strh %0, [%1, #0] @ outwc" \ | ||
130 | : : "r" (v), \ | ||
131 | "r" (PCIO_BASE + (port))); \ | ||
132 | } else \ | ||
133 | __asm__ __volatile__( \ | ||
134 | "strh %0, [%1, #0] @ outwc" \ | ||
135 | : : "r" (v), "r" ((port))); \ | ||
136 | }) | ||
137 | |||
138 | #define __inwc(port) \ | ||
139 | ({ \ | ||
140 | unsigned short result; \ | ||
141 | if (__PORT_PCIO((port))) { \ | ||
142 | if ((port) < 256 && (port) > -256 ) \ | ||
143 | __asm__ __volatile__( \ | ||
144 | "ldrh %0, [%1, %2] @ inwc" \ | ||
145 | : "=r" (result) \ | ||
146 | : "r" (PCIO_BASE), \ | ||
147 | "Jr" ((port))); \ | ||
148 | else if ((port) > 0) \ | ||
149 | __asm__ __volatile__( \ | ||
150 | "ldrh %0, [%1, %2] @ inwc" \ | ||
151 | : "=r" (result) \ | ||
152 | : "r" (PCIO_BASE + ((port) & ~0xff)), \ | ||
153 | "Jr" (((port) & 0xff))); \ | ||
154 | else \ | ||
155 | __asm__ __volatile__( \ | ||
156 | "ldrh %0, [%1, #0] @ inwc" \ | ||
157 | : "=r" (result) \ | ||
158 | : "r" (PCIO_BASE + ((port)))); \ | ||
159 | } else \ | ||
160 | __asm__ __volatile__( \ | ||
161 | "ldrh %0, [%1, #0] @ inwc" \ | ||
162 | : "=r" (result) : "r" ((port))); \ | ||
163 | result; \ | ||
164 | }) | ||
165 | |||
166 | #define __outlc(value,port) \ | ||
167 | ({ \ | ||
168 | unsigned long v = value; \ | ||
169 | if (__PORT_PCIO((port))) \ | ||
170 | __asm__ __volatile__( \ | ||
171 | "str %0, [%1, %2] @ outlc" \ | ||
172 | : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ | ||
173 | else \ | ||
174 | __asm__ __volatile__( \ | ||
175 | "str %0, [%1, #0] @ outlc" \ | ||
176 | : : "r" (v), "r" ((port))); \ | ||
177 | }) | ||
178 | |||
179 | #define __inlc(port) \ | ||
180 | ({ \ | ||
181 | unsigned long result; \ | ||
182 | if (__PORT_PCIO((port))) \ | ||
183 | __asm__ __volatile__( \ | ||
184 | "ldr %0, [%1, %2] @ inlc" \ | ||
185 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ | ||
186 | else \ | ||
187 | __asm__ __volatile__( \ | ||
188 | "ldr %0, [%1, #0] @ inlc" \ | ||
189 | : "=r" (result) : "r" ((port))); \ | ||
190 | result; \ | ||
191 | }) | ||
192 | |||
193 | #define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port))) | ||
194 | |||
195 | #define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) | ||
196 | #define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) | ||
197 | #define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) | ||
198 | #define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) | ||
199 | #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) | ||
200 | #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) | ||
201 | #define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) | ||
202 | /* the following macro is deprecated */ | ||
203 | #define ioaddr(port) __ioaddr((port)) | ||
204 | |||
205 | #define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) | ||
206 | #define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) | ||
207 | #define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l) | ||
208 | |||
209 | #define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) | ||
210 | #define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) | ||
211 | #define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l) | ||
212 | |||
213 | /* | ||
214 | * 1:1 mapping for ioremapped regions. | ||
215 | */ | ||
216 | #define __mem_pci(x) (x) | ||
217 | |||
218 | #endif | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h new file mode 100644 index 000000000000..950c71bf1489 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h | |||
@@ -0,0 +1,166 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/irqs.h | ||
2 | * | ||
3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | |||
12 | #ifndef __ASM_ARCH_IRQS_H | ||
13 | #define __ASM_ARCH_IRQS_H __FILE__ | ||
14 | |||
15 | #ifndef __ASM_ARM_IRQ_H | ||
16 | #error "Do not include this directly, instead #include <asm/irq.h>" | ||
17 | #endif | ||
18 | |||
19 | /* we keep the first set of CPU IRQs out of the range of | ||
20 | * the ISA space, so that the PC104 has them to itself | ||
21 | * and we don't end up having to do horrible things to the | ||
22 | * standard ISA drivers.... | ||
23 | */ | ||
24 | |||
25 | #define S3C2410_CPUIRQ_OFFSET (16) | ||
26 | |||
27 | #define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) | ||
28 | |||
29 | /* main cpu interrupts */ | ||
30 | #define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ | ||
31 | #define IRQ_EINT1 S3C2410_IRQ(1) | ||
32 | #define IRQ_EINT2 S3C2410_IRQ(2) | ||
33 | #define IRQ_EINT3 S3C2410_IRQ(3) | ||
34 | #define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ | ||
35 | #define IRQ_EINT8t23 S3C2410_IRQ(5) | ||
36 | #define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ | ||
37 | #define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ | ||
38 | #define IRQ_BATT_FLT S3C2410_IRQ(7) | ||
39 | #define IRQ_TICK S3C2410_IRQ(8) /* 24 */ | ||
40 | #define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ | ||
41 | #define IRQ_TIMER0 S3C2410_IRQ(10) | ||
42 | #define IRQ_TIMER1 S3C2410_IRQ(11) | ||
43 | #define IRQ_TIMER2 S3C2410_IRQ(12) | ||
44 | #define IRQ_TIMER3 S3C2410_IRQ(13) | ||
45 | #define IRQ_TIMER4 S3C2410_IRQ(14) | ||
46 | #define IRQ_UART2 S3C2410_IRQ(15) | ||
47 | #define IRQ_LCD S3C2410_IRQ(16) /* 32 */ | ||
48 | #define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ | ||
49 | #define IRQ_DMA1 S3C2410_IRQ(18) | ||
50 | #define IRQ_DMA2 S3C2410_IRQ(19) | ||
51 | #define IRQ_DMA3 S3C2410_IRQ(20) | ||
52 | #define IRQ_SDI S3C2410_IRQ(21) | ||
53 | #define IRQ_SPI0 S3C2410_IRQ(22) | ||
54 | #define IRQ_UART1 S3C2410_IRQ(23) | ||
55 | #define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ | ||
56 | #define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ | ||
57 | #define IRQ_USBD S3C2410_IRQ(25) | ||
58 | #define IRQ_USBH S3C2410_IRQ(26) | ||
59 | #define IRQ_IIC S3C2410_IRQ(27) | ||
60 | #define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ | ||
61 | #define IRQ_SPI1 S3C2410_IRQ(29) | ||
62 | #define IRQ_RTC S3C2410_IRQ(30) | ||
63 | #define IRQ_ADCPARENT S3C2410_IRQ(31) | ||
64 | |||
65 | /* interrupts generated from the external interrupts sources */ | ||
66 | #define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ | ||
67 | #define IRQ_EINT5 S3C2410_IRQ(33) | ||
68 | #define IRQ_EINT6 S3C2410_IRQ(34) | ||
69 | #define IRQ_EINT7 S3C2410_IRQ(35) | ||
70 | #define IRQ_EINT8 S3C2410_IRQ(36) | ||
71 | #define IRQ_EINT9 S3C2410_IRQ(37) | ||
72 | #define IRQ_EINT10 S3C2410_IRQ(38) | ||
73 | #define IRQ_EINT11 S3C2410_IRQ(39) | ||
74 | #define IRQ_EINT12 S3C2410_IRQ(40) | ||
75 | #define IRQ_EINT13 S3C2410_IRQ(41) | ||
76 | #define IRQ_EINT14 S3C2410_IRQ(42) | ||
77 | #define IRQ_EINT15 S3C2410_IRQ(43) | ||
78 | #define IRQ_EINT16 S3C2410_IRQ(44) | ||
79 | #define IRQ_EINT17 S3C2410_IRQ(45) | ||
80 | #define IRQ_EINT18 S3C2410_IRQ(46) | ||
81 | #define IRQ_EINT19 S3C2410_IRQ(47) | ||
82 | #define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ | ||
83 | #define IRQ_EINT21 S3C2410_IRQ(49) | ||
84 | #define IRQ_EINT22 S3C2410_IRQ(50) | ||
85 | #define IRQ_EINT23 S3C2410_IRQ(51) | ||
86 | |||
87 | |||
88 | #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) | ||
89 | |||
90 | #define IRQ_LCD_FIFO S3C2410_IRQ(52) | ||
91 | #define IRQ_LCD_FRAME S3C2410_IRQ(53) | ||
92 | |||
93 | /* IRQs for the interal UARTs, and ADC | ||
94 | * these need to be ordered in number of appearance in the | ||
95 | * SUBSRC mask register | ||
96 | */ | ||
97 | |||
98 | #define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) | ||
99 | |||
100 | #define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ | ||
101 | #define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) | ||
102 | #define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) | ||
103 | |||
104 | #define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ | ||
105 | #define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) | ||
106 | #define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) | ||
107 | |||
108 | #define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ | ||
109 | #define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) | ||
110 | #define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) | ||
111 | |||
112 | #define IRQ_TC S3C2410_IRQSUB(9) | ||
113 | #define IRQ_ADC S3C2410_IRQSUB(10) | ||
114 | |||
115 | /* extra irqs for s3c2412 */ | ||
116 | |||
117 | #define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) | ||
118 | |||
119 | #define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) | ||
120 | #define IRQ_S3C2412_CF S3C2410_IRQSUB(14) | ||
121 | |||
122 | /* extra irqs for s3c2440 */ | ||
123 | |||
124 | #define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ | ||
125 | #define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ | ||
126 | #define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) | ||
127 | #define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) | ||
128 | |||
129 | /* irqs for s3c2443 */ | ||
130 | |||
131 | #define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ | ||
132 | #define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ | ||
133 | #define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ | ||
134 | #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ | ||
135 | #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ | ||
136 | |||
137 | #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) | ||
138 | #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) | ||
139 | #define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) | ||
140 | #define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) | ||
141 | |||
142 | #define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) | ||
143 | #define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) | ||
144 | #define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) | ||
145 | #define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) | ||
146 | #define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) | ||
147 | #define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) | ||
148 | |||
149 | /* UART3 */ | ||
150 | #define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) | ||
151 | #define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) | ||
152 | #define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) | ||
153 | |||
154 | #define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) | ||
155 | #define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) | ||
156 | |||
157 | #ifdef CONFIG_CPU_S3C2443 | ||
158 | #define NR_IRQS (IRQ_S3C2443_AC97+1) | ||
159 | #else | ||
160 | #define NR_IRQS (IRQ_S3C2440_AC97+1) | ||
161 | #endif | ||
162 | |||
163 | /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ | ||
164 | #define FIQ_START IRQ_EINT0 | ||
165 | |||
166 | #endif /* __ASM_ARCH_IRQ_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h b/arch/arm/mach-s3c2410/include/mach/leds-gpio.h new file mode 100644 index 000000000000..d8a7672519b6 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/leds-gpio.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/leds-gpio.h | ||
2 | * | ||
3 | * Copyright (c) 2006 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX - LEDs GPIO connector | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_LEDSGPIO_H | ||
15 | #define __ASM_ARCH_LEDSGPIO_H "leds-gpio.h" | ||
16 | |||
17 | #define S3C24XX_LEDF_ACTLOW (1<<0) /* LED is on when GPIO low */ | ||
18 | #define S3C24XX_LEDF_TRISTATE (1<<1) /* tristate to turn off */ | ||
19 | |||
20 | struct s3c24xx_led_platdata { | ||
21 | unsigned int gpio; | ||
22 | unsigned int flags; | ||
23 | |||
24 | char *name; | ||
25 | char *def_trigger; | ||
26 | }; | ||
27 | |||
28 | #endif /* __ASM_ARCH_LEDSGPIO_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h new file mode 100644 index 000000000000..64bf7e94a5bf --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/map.h | |||
@@ -0,0 +1,178 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/map.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - Memory map definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_MAP_H | ||
14 | #define __ASM_ARCH_MAP_H | ||
15 | |||
16 | #include <asm/plat-s3c/map.h> | ||
17 | |||
18 | #define S3C2410_ADDR(x) S3C_ADDR(x) | ||
19 | |||
20 | /* interrupt controller is the first thing we put in, to make | ||
21 | * the assembly code for the irq detection easier | ||
22 | */ | ||
23 | #define S3C24XX_VA_IRQ S3C_VA_IRQ | ||
24 | #define S3C2410_PA_IRQ (0x4A000000) | ||
25 | #define S3C24XX_SZ_IRQ SZ_1M | ||
26 | |||
27 | /* memory controller registers */ | ||
28 | #define S3C24XX_VA_MEMCTRL S3C_VA_MEM | ||
29 | #define S3C2410_PA_MEMCTRL (0x48000000) | ||
30 | #define S3C24XX_SZ_MEMCTRL SZ_1M | ||
31 | |||
32 | /* USB host controller */ | ||
33 | #define S3C2410_PA_USBHOST (0x49000000) | ||
34 | #define S3C24XX_SZ_USBHOST SZ_1M | ||
35 | |||
36 | /* DMA controller */ | ||
37 | #define S3C2410_PA_DMA (0x4B000000) | ||
38 | #define S3C24XX_SZ_DMA SZ_1M | ||
39 | |||
40 | /* Clock and Power management */ | ||
41 | #define S3C24XX_VA_CLKPWR S3C_VA_SYS | ||
42 | #define S3C2410_PA_CLKPWR (0x4C000000) | ||
43 | #define S3C24XX_SZ_CLKPWR SZ_1M | ||
44 | |||
45 | /* LCD controller */ | ||
46 | #define S3C2410_PA_LCD (0x4D000000) | ||
47 | #define S3C24XX_SZ_LCD SZ_1M | ||
48 | |||
49 | /* NAND flash controller */ | ||
50 | #define S3C2410_PA_NAND (0x4E000000) | ||
51 | #define S3C24XX_SZ_NAND SZ_1M | ||
52 | |||
53 | /* UARTs */ | ||
54 | #define S3C24XX_VA_UART S3C_VA_UART | ||
55 | #define S3C2410_PA_UART (0x50000000) | ||
56 | #define S3C24XX_SZ_UART SZ_1M | ||
57 | |||
58 | /* Timers */ | ||
59 | #define S3C24XX_VA_TIMER S3C_VA_TIMER | ||
60 | #define S3C2410_PA_TIMER (0x51000000) | ||
61 | #define S3C24XX_SZ_TIMER SZ_1M | ||
62 | |||
63 | /* USB Device port */ | ||
64 | #define S3C2410_PA_USBDEV (0x52000000) | ||
65 | #define S3C24XX_SZ_USBDEV SZ_1M | ||
66 | |||
67 | /* Watchdog */ | ||
68 | #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG | ||
69 | #define S3C2410_PA_WATCHDOG (0x53000000) | ||
70 | #define S3C24XX_SZ_WATCHDOG SZ_1M | ||
71 | |||
72 | /* IIC hardware controller */ | ||
73 | #define S3C2410_PA_IIC (0x54000000) | ||
74 | #define S3C24XX_SZ_IIC SZ_1M | ||
75 | |||
76 | /* IIS controller */ | ||
77 | #define S3C2410_PA_IIS (0x55000000) | ||
78 | #define S3C24XX_SZ_IIS SZ_1M | ||
79 | |||
80 | /* GPIO ports */ | ||
81 | |||
82 | /* the calculation for the VA of this must ensure that | ||
83 | * it is the same distance apart from the UART in the | ||
84 | * phsyical address space, as the initial mapping for the IO | ||
85 | * is done as a 1:1 maping. This puts it (currently) at | ||
86 | * 0xFA800000, which is not in the way of any current mapping | ||
87 | * by the base system. | ||
88 | */ | ||
89 | |||
90 | #define S3C2410_PA_GPIO (0x56000000) | ||
91 | #define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) | ||
92 | #define S3C24XX_SZ_GPIO SZ_1M | ||
93 | |||
94 | /* RTC */ | ||
95 | #define S3C2410_PA_RTC (0x57000000) | ||
96 | #define S3C24XX_SZ_RTC SZ_1M | ||
97 | |||
98 | /* ADC */ | ||
99 | #define S3C2410_PA_ADC (0x58000000) | ||
100 | #define S3C24XX_SZ_ADC SZ_1M | ||
101 | |||
102 | /* SPI */ | ||
103 | #define S3C2410_PA_SPI (0x59000000) | ||
104 | #define S3C24XX_SZ_SPI SZ_1M | ||
105 | |||
106 | /* SDI */ | ||
107 | #define S3C2410_PA_SDI (0x5A000000) | ||
108 | #define S3C24XX_SZ_SDI SZ_1M | ||
109 | |||
110 | /* CAMIF */ | ||
111 | #define S3C2440_PA_CAMIF (0x4F000000) | ||
112 | #define S3C2440_SZ_CAMIF SZ_1M | ||
113 | |||
114 | /* AC97 */ | ||
115 | |||
116 | #define S3C2440_PA_AC97 (0x5B000000) | ||
117 | #define S3C2440_SZ_AC97 SZ_1M | ||
118 | |||
119 | /* S3C2443 High-speed SD/MMC */ | ||
120 | #define S3C2443_PA_HSMMC (0x4A800000) | ||
121 | #define S3C2443_SZ_HSMMC (256) | ||
122 | |||
123 | /* ISA style IO, for each machine to sort out mappings for, if it | ||
124 | * implements it. We reserve two 16M regions for ISA. | ||
125 | */ | ||
126 | |||
127 | #define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) | ||
128 | #define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) | ||
129 | |||
130 | /* physical addresses of all the chip-select areas */ | ||
131 | |||
132 | #define S3C2410_CS0 (0x00000000) | ||
133 | #define S3C2410_CS1 (0x08000000) | ||
134 | #define S3C2410_CS2 (0x10000000) | ||
135 | #define S3C2410_CS3 (0x18000000) | ||
136 | #define S3C2410_CS4 (0x20000000) | ||
137 | #define S3C2410_CS5 (0x28000000) | ||
138 | #define S3C2410_CS6 (0x30000000) | ||
139 | #define S3C2410_CS7 (0x38000000) | ||
140 | |||
141 | #define S3C2410_SDRAM_PA (S3C2410_CS6) | ||
142 | |||
143 | /* Use a single interface for common resources between S3C24XX cpus */ | ||
144 | |||
145 | #define S3C24XX_PA_IRQ S3C2410_PA_IRQ | ||
146 | #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL | ||
147 | #define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST | ||
148 | #define S3C24XX_PA_DMA S3C2410_PA_DMA | ||
149 | #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR | ||
150 | #define S3C24XX_PA_LCD S3C2410_PA_LCD | ||
151 | #define S3C24XX_PA_UART S3C2410_PA_UART | ||
152 | #define S3C24XX_PA_TIMER S3C2410_PA_TIMER | ||
153 | #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV | ||
154 | #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG | ||
155 | #define S3C24XX_PA_IIC S3C2410_PA_IIC | ||
156 | #define S3C24XX_PA_IIS S3C2410_PA_IIS | ||
157 | #define S3C24XX_PA_GPIO S3C2410_PA_GPIO | ||
158 | #define S3C24XX_PA_RTC S3C2410_PA_RTC | ||
159 | #define S3C24XX_PA_ADC S3C2410_PA_ADC | ||
160 | #define S3C24XX_PA_SPI S3C2410_PA_SPI | ||
161 | |||
162 | /* deal with the registers that move under the 2412/2413 */ | ||
163 | |||
164 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | ||
165 | #ifndef __ASSEMBLY__ | ||
166 | extern void __iomem *s3c24xx_va_gpio2; | ||
167 | #endif | ||
168 | #ifdef CONFIG_CPU_S3C2412_ONLY | ||
169 | #define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) | ||
170 | #else | ||
171 | #define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 | ||
172 | #endif | ||
173 | #else | ||
174 | #define s3c24xx_va_gpio2 S3C24XX_VA_GPIO | ||
175 | #define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO | ||
176 | #endif | ||
177 | |||
178 | #endif /* __ASM_ARCH_MAP_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/memory.h b/arch/arm/mach-s3c2410/include/mach/memory.h new file mode 100644 index 000000000000..93782628a786 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/memory.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/memory.h | ||
2 | * from arch/arm/mach-rpc/include/mach/memory.h | ||
3 | * | ||
4 | * Copyright (C) 1996,1997,1998 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_MEMORY_H | ||
12 | #define __ASM_ARCH_MEMORY_H | ||
13 | |||
14 | #define PHYS_OFFSET UL(0x30000000) | ||
15 | |||
16 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
17 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
18 | |||
19 | #endif | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h b/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h new file mode 100644 index 000000000000..e9e36b0abbac --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h | ||
2 | * | ||
3 | * Copyright 2005 Simtec Electronics | ||
4 | * http://www.simtec.co.uk/products/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * OSIRIS - CPLD control constants | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_OSIRISCPLD_H | ||
15 | #define __ASM_ARCH_OSIRISCPLD_H | ||
16 | |||
17 | /* CTRL0 - NAND WP control */ | ||
18 | |||
19 | #define OSIRIS_CTRL0_NANDSEL (0x3) | ||
20 | #define OSIRIS_CTRL0_BOOT_INT (1<<3) | ||
21 | #define OSIRIS_CTRL0_PCMCIA (1<<4) | ||
22 | #define OSIRIS_CTRL0_FIX8 (1<<5) | ||
23 | #define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6) | ||
24 | #define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7) | ||
25 | |||
26 | #define OSIRIS_CTRL1_FIX8 (1<<0) | ||
27 | |||
28 | #define OSIRIS_ID_REVMASK (0x7) | ||
29 | |||
30 | #endif /* __ASM_ARCH_OSIRISCPLD_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-map.h b/arch/arm/mach-s3c2410/include/mach/osiris-map.h new file mode 100644 index 000000000000..639eff523d4e --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/osiris-map.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/osiris-map.h | ||
2 | * | ||
3 | * (c) 2005 Simtec Electronics | ||
4 | * http://www.simtec.co.uk/products/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * OSIRIS - Memory map definitions | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | /* needs arch/map.h including with this */ | ||
15 | |||
16 | #ifndef __ASM_ARCH_OSIRISMAP_H | ||
17 | #define __ASM_ARCH_OSIRISMAP_H | ||
18 | |||
19 | /* start peripherals off after the S3C2410 */ | ||
20 | |||
21 | #define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000)) | ||
22 | |||
23 | #define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26)) | ||
24 | |||
25 | /* we put the CPLD registers next, to get them out of the way */ | ||
26 | |||
27 | #define OSIRIS_VA_CTRL0 OSIRIS_IOADDR(0x00000000) | ||
28 | #define OSIRIS_PA_CTRL0 (OSIRIS_PA_CPLD) | ||
29 | |||
30 | #define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00100000) | ||
31 | #define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD + (1<<23)) | ||
32 | |||
33 | #define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00200000) | ||
34 | #define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (2<<23)) | ||
35 | |||
36 | #define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00300000) | ||
37 | #define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23)) | ||
38 | |||
39 | #define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000) | ||
40 | #define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23)) | ||
41 | |||
42 | #endif /* __ASM_ARCH_OSIRISMAP_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/otom-map.h b/arch/arm/mach-s3c2410/include/mach/otom-map.h new file mode 100644 index 000000000000..f9277a52c145 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/otom-map.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/otom-map.h | ||
2 | * | ||
3 | * (c) 2005 Guillaume GOURAT / NexVision | ||
4 | * guillaume.gourat@nexvision.fr | ||
5 | * | ||
6 | * NexVision OTOM board memory map definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | /* needs arch/map.h including with this */ | ||
14 | |||
15 | /* ok, we've used up to 0x01300000, now we need to find space for the | ||
16 | * peripherals that live in the nGCS[x] areas, which are quite numerous | ||
17 | * in their space. | ||
18 | */ | ||
19 | |||
20 | #ifndef __ASM_ARCH_OTOMMAP_H | ||
21 | #define __ASM_ARCH_OTOMMAP_H | ||
22 | |||
23 | #define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */ | ||
24 | #define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */ | ||
25 | |||
26 | /* physical offset addresses for the peripherals */ | ||
27 | |||
28 | #define OTOM_PA_FLASH0_BASE (S3C2410_CS0) /* Bank 0 */ | ||
29 | |||
30 | #endif /* __ASM_ARCH_OTOMMAP_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h new file mode 100644 index 000000000000..d583688458a4 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h | |||
@@ -0,0 +1,197 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-clock.h | ||
2 | * | ||
3 | * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 clock register definitions | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARM_REGS_CLOCK | ||
14 | #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $" | ||
15 | |||
16 | #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) | ||
17 | |||
18 | #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s))) | ||
19 | |||
20 | #define S3C2410_LOCKTIME S3C2410_CLKREG(0x00) | ||
21 | #define S3C2410_MPLLCON S3C2410_CLKREG(0x04) | ||
22 | #define S3C2410_UPLLCON S3C2410_CLKREG(0x08) | ||
23 | #define S3C2410_CLKCON S3C2410_CLKREG(0x0C) | ||
24 | #define S3C2410_CLKSLOW S3C2410_CLKREG(0x10) | ||
25 | #define S3C2410_CLKDIVN S3C2410_CLKREG(0x14) | ||
26 | |||
27 | #define S3C2410_CLKCON_IDLE (1<<2) | ||
28 | #define S3C2410_CLKCON_POWER (1<<3) | ||
29 | #define S3C2410_CLKCON_NAND (1<<4) | ||
30 | #define S3C2410_CLKCON_LCDC (1<<5) | ||
31 | #define S3C2410_CLKCON_USBH (1<<6) | ||
32 | #define S3C2410_CLKCON_USBD (1<<7) | ||
33 | #define S3C2410_CLKCON_PWMT (1<<8) | ||
34 | #define S3C2410_CLKCON_SDI (1<<9) | ||
35 | #define S3C2410_CLKCON_UART0 (1<<10) | ||
36 | #define S3C2410_CLKCON_UART1 (1<<11) | ||
37 | #define S3C2410_CLKCON_UART2 (1<<12) | ||
38 | #define S3C2410_CLKCON_GPIO (1<<13) | ||
39 | #define S3C2410_CLKCON_RTC (1<<14) | ||
40 | #define S3C2410_CLKCON_ADC (1<<15) | ||
41 | #define S3C2410_CLKCON_IIC (1<<16) | ||
42 | #define S3C2410_CLKCON_IIS (1<<17) | ||
43 | #define S3C2410_CLKCON_SPI (1<<18) | ||
44 | |||
45 | #define S3C2410_PLLCON_MDIVSHIFT 12 | ||
46 | #define S3C2410_PLLCON_PDIVSHIFT 4 | ||
47 | #define S3C2410_PLLCON_SDIVSHIFT 0 | ||
48 | #define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) | ||
49 | #define S3C2410_PLLCON_PDIVMASK ((1<<5)-1) | ||
50 | #define S3C2410_PLLCON_SDIVMASK 3 | ||
51 | |||
52 | /* DCLKCON register addresses in gpio.h */ | ||
53 | |||
54 | #define S3C2410_DCLKCON_DCLK0EN (1<<0) | ||
55 | #define S3C2410_DCLKCON_DCLK0_PCLK (0<<1) | ||
56 | #define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) | ||
57 | #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) | ||
58 | #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) | ||
59 | #define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4) | ||
60 | #define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8) | ||
61 | |||
62 | #define S3C2410_DCLKCON_DCLK1EN (1<<16) | ||
63 | #define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) | ||
64 | #define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) | ||
65 | #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) | ||
66 | #define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24) | ||
67 | #define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20) | ||
68 | #define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24) | ||
69 | |||
70 | #define S3C2410_CLKDIVN_PDIVN (1<<0) | ||
71 | #define S3C2410_CLKDIVN_HDIVN (1<<1) | ||
72 | |||
73 | #define S3C2410_CLKSLOW_UCLK_OFF (1<<7) | ||
74 | #define S3C2410_CLKSLOW_MPLL_OFF (1<<5) | ||
75 | #define S3C2410_CLKSLOW_SLOW (1<<4) | ||
76 | #define S3C2410_CLKSLOW_SLOWVAL(x) (x) | ||
77 | #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) | ||
78 | |||
79 | #ifndef __ASSEMBLY__ | ||
80 | |||
81 | #include <asm/div64.h> | ||
82 | |||
83 | static inline unsigned int | ||
84 | s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) | ||
85 | { | ||
86 | unsigned int mdiv, pdiv, sdiv; | ||
87 | uint64_t fvco; | ||
88 | |||
89 | mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; | ||
90 | pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; | ||
91 | sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT; | ||
92 | |||
93 | mdiv &= S3C2410_PLLCON_MDIVMASK; | ||
94 | pdiv &= S3C2410_PLLCON_PDIVMASK; | ||
95 | sdiv &= S3C2410_PLLCON_SDIVMASK; | ||
96 | |||
97 | fvco = (uint64_t)baseclk * (mdiv + 8); | ||
98 | do_div(fvco, (pdiv + 2) << sdiv); | ||
99 | |||
100 | return (unsigned int)fvco; | ||
101 | } | ||
102 | |||
103 | #endif /* __ASSEMBLY__ */ | ||
104 | |||
105 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) | ||
106 | |||
107 | /* extra registers */ | ||
108 | #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) | ||
109 | |||
110 | #define S3C2440_CLKCON_CAMERA (1<<19) | ||
111 | #define S3C2440_CLKCON_AC97 (1<<20) | ||
112 | |||
113 | #define S3C2440_CLKDIVN_PDIVN (1<<0) | ||
114 | #define S3C2440_CLKDIVN_HDIVN_MASK (3<<1) | ||
115 | #define S3C2440_CLKDIVN_HDIVN_1 (0<<1) | ||
116 | #define S3C2440_CLKDIVN_HDIVN_2 (1<<1) | ||
117 | #define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1) | ||
118 | #define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1) | ||
119 | #define S3C2440_CLKDIVN_UCLK (1<<3) | ||
120 | |||
121 | #define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0) | ||
122 | #define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4) | ||
123 | #define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) | ||
124 | #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) | ||
125 | #define S3C2440_CAMDIVN_DVSEN (1<<12) | ||
126 | |||
127 | #define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) | ||
128 | |||
129 | #endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ | ||
130 | |||
131 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | ||
132 | |||
133 | #define S3C2412_OSCSET S3C2410_CLKREG(0x18) | ||
134 | #define S3C2412_CLKSRC S3C2410_CLKREG(0x1C) | ||
135 | |||
136 | #define S3C2412_PLLCON_OFF (1<<20) | ||
137 | |||
138 | #define S3C2412_CLKDIVN_PDIVN (1<<2) | ||
139 | #define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) | ||
140 | #define S3C2412_CLKDIVN_ARMDIVN (1<<3) | ||
141 | #define S3C2412_CLKDIVN_DVSEN (1<<4) | ||
142 | #define S3C2412_CLKDIVN_HALFHCLK (1<<5) | ||
143 | #define S3C2412_CLKDIVN_USB48DIV (1<<6) | ||
144 | #define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8) | ||
145 | #define S3C2412_CLKDIVN_UARTDIV_SHIFT (8) | ||
146 | #define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12) | ||
147 | #define S3C2412_CLKDIVN_I2SDIV_SHIFT (12) | ||
148 | #define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16) | ||
149 | #define S3C2412_CLKDIVN_CAMDIV_SHIFT (16) | ||
150 | |||
151 | #define S3C2412_CLKCON_WDT (1<<28) | ||
152 | #define S3C2412_CLKCON_SPI (1<<27) | ||
153 | #define S3C2412_CLKCON_IIS (1<<26) | ||
154 | #define S3C2412_CLKCON_IIC (1<<25) | ||
155 | #define S3C2412_CLKCON_ADC (1<<24) | ||
156 | #define S3C2412_CLKCON_RTC (1<<23) | ||
157 | #define S3C2412_CLKCON_GPIO (1<<22) | ||
158 | #define S3C2412_CLKCON_UART2 (1<<21) | ||
159 | #define S3C2412_CLKCON_UART1 (1<<20) | ||
160 | #define S3C2412_CLKCON_UART0 (1<<19) | ||
161 | #define S3C2412_CLKCON_SDI (1<<18) | ||
162 | #define S3C2412_CLKCON_PWMT (1<<17) | ||
163 | #define S3C2412_CLKCON_USBD (1<<16) | ||
164 | #define S3C2412_CLKCON_CAMCLK (1<<15) | ||
165 | #define S3C2412_CLKCON_UARTCLK (1<<14) | ||
166 | /* missing 13 */ | ||
167 | #define S3C2412_CLKCON_USB_HOST48 (1<<12) | ||
168 | #define S3C2412_CLKCON_USB_DEV48 (1<<11) | ||
169 | #define S3C2412_CLKCON_HCLKdiv2 (1<<10) | ||
170 | #define S3C2412_CLKCON_HCLKx2 (1<<9) | ||
171 | #define S3C2412_CLKCON_SDRAM (1<<8) | ||
172 | /* missing 7 */ | ||
173 | #define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH | ||
174 | #define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC | ||
175 | #define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND | ||
176 | #define S3C2412_CLKCON_DMA3 (1<<3) | ||
177 | #define S3C2412_CLKCON_DMA2 (1<<2) | ||
178 | #define S3C2412_CLKCON_DMA1 (1<<1) | ||
179 | #define S3C2412_CLKCON_DMA0 (1<<0) | ||
180 | |||
181 | /* clock sourec controls */ | ||
182 | |||
183 | #define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0) | ||
184 | #define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0) | ||
185 | #define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3) | ||
186 | #define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4) | ||
187 | #define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5) | ||
188 | #define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8) | ||
189 | #define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) | ||
190 | #define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) | ||
191 | #define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) | ||
192 | #define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12) | ||
193 | #define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14) | ||
194 | |||
195 | #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ | ||
196 | |||
197 | #endif /* __ASM_ARM_REGS_CLOCK */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h new file mode 100644 index 000000000000..3c3853cd3cf7 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h | |||
@@ -0,0 +1,184 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-dsc.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2440/S3C2412 Signal Drive Strength Control | ||
11 | */ | ||
12 | |||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_DSC_H | ||
15 | #define __ASM_ARCH_REGS_DSC_H "2440-dsc" | ||
16 | |||
17 | #if defined(CONFIG_CPU_S3C2412) | ||
18 | #define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) | ||
19 | #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) | ||
20 | #endif | ||
21 | |||
22 | #if defined(CONFIG_CPU_S3C244X) | ||
23 | |||
24 | #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) | ||
25 | #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) | ||
26 | |||
27 | #define S3C2440_SELECT_DSC0 (0) | ||
28 | #define S3C2440_SELECT_DSC1 (1<<31) | ||
29 | |||
30 | #define S3C2440_DSC_GETSHIFT(x) ((x) & 31) | ||
31 | |||
32 | #define S3C2440_DSC0_DISABLE (1<<31) | ||
33 | |||
34 | #define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8) | ||
35 | #define S3C2440_DSC0_ADDR_12mA (0<<8) | ||
36 | #define S3C2440_DSC0_ADDR_10mA (1<<8) | ||
37 | #define S3C2440_DSC0_ADDR_8mA (2<<8) | ||
38 | #define S3C2440_DSC0_ADDR_6mA (3<<8) | ||
39 | #define S3C2440_DSC0_ADDR_MASK (3<<8) | ||
40 | |||
41 | /* D24..D31 */ | ||
42 | #define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6) | ||
43 | #define S3C2440_DSC0_DATA3_12mA (0<<6) | ||
44 | #define S3C2440_DSC0_DATA3_10mA (1<<6) | ||
45 | #define S3C2440_DSC0_DATA3_8mA (2<<6) | ||
46 | #define S3C2440_DSC0_DATA3_6mA (3<<6) | ||
47 | #define S3C2440_DSC0_DATA3_MASK (3<<6) | ||
48 | |||
49 | /* D16..D23 */ | ||
50 | #define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4) | ||
51 | #define S3C2440_DSC0_DATA2_12mA (0<<4) | ||
52 | #define S3C2440_DSC0_DATA2_10mA (1<<4) | ||
53 | #define S3C2440_DSC0_DATA2_8mA (2<<4) | ||
54 | #define S3C2440_DSC0_DATA2_6mA (3<<4) | ||
55 | #define S3C2440_DSC0_DATA2_MASK (3<<4) | ||
56 | |||
57 | /* D8..D15 */ | ||
58 | #define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2) | ||
59 | #define S3C2440_DSC0_DATA1_12mA (0<<2) | ||
60 | #define S3C2440_DSC0_DATA1_10mA (1<<2) | ||
61 | #define S3C2440_DSC0_DATA1_8mA (2<<2) | ||
62 | #define S3C2440_DSC0_DATA1_6mA (3<<2) | ||
63 | #define S3C2440_DSC0_DATA1_MASK (3<<2) | ||
64 | |||
65 | /* D0..D7 */ | ||
66 | #define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0) | ||
67 | #define S3C2440_DSC0_DATA0_12mA (0<<0) | ||
68 | #define S3C2440_DSC0_DATA0_10mA (1<<0) | ||
69 | #define S3C2440_DSC0_DATA0_8mA (2<<0) | ||
70 | #define S3C2440_DSC0_DATA0_6mA (3<<0) | ||
71 | #define S3C2440_DSC0_DATA0_MASK (3<<0) | ||
72 | |||
73 | #define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28) | ||
74 | #define S3C2440_DSC1_SCK1_12mA (0<<28) | ||
75 | #define S3C2440_DSC1_SCK1_10mA (1<<28) | ||
76 | #define S3C2440_DSC1_SCK1_8mA (2<<28) | ||
77 | #define S3C2440_DSC1_SCK1_6mA (3<<28) | ||
78 | #define S3C2440_DSC1_SCK1_MASK (3<<28) | ||
79 | |||
80 | #define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26) | ||
81 | #define S3C2440_DSC1_SCK0_12mA (0<<26) | ||
82 | #define S3C2440_DSC1_SCK0_10mA (1<<26) | ||
83 | #define S3C2440_DSC1_SCK0_8mA (2<<26) | ||
84 | #define S3C2440_DSC1_SCK0_6mA (3<<26) | ||
85 | #define S3C2440_DSC1_SCK0_MASK (3<<26) | ||
86 | |||
87 | #define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24) | ||
88 | #define S3C2440_DSC1_SCKE_10mA (0<<24) | ||
89 | #define S3C2440_DSC1_SCKE_8mA (1<<24) | ||
90 | #define S3C2440_DSC1_SCKE_6mA (2<<24) | ||
91 | #define S3C2440_DSC1_SCKE_4mA (3<<24) | ||
92 | #define S3C2440_DSC1_SCKE_MASK (3<<24) | ||
93 | |||
94 | /* SDRAM nRAS/nCAS */ | ||
95 | #define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22) | ||
96 | #define S3C2440_DSC1_SDR_10mA (0<<22) | ||
97 | #define S3C2440_DSC1_SDR_8mA (1<<22) | ||
98 | #define S3C2440_DSC1_SDR_6mA (2<<22) | ||
99 | #define S3C2440_DSC1_SDR_4mA (3<<22) | ||
100 | #define S3C2440_DSC1_SDR_MASK (3<<22) | ||
101 | |||
102 | /* NAND Flash Controller */ | ||
103 | #define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20) | ||
104 | #define S3C2440_DSC1_NFC_10mA (0<<20) | ||
105 | #define S3C2440_DSC1_NFC_8mA (1<<20) | ||
106 | #define S3C2440_DSC1_NFC_6mA (2<<20) | ||
107 | #define S3C2440_DSC1_NFC_4mA (3<<20) | ||
108 | #define S3C2440_DSC1_NFC_MASK (3<<20) | ||
109 | |||
110 | /* nBE[0..3] */ | ||
111 | #define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18) | ||
112 | #define S3C2440_DSC1_nBE_10mA (0<<18) | ||
113 | #define S3C2440_DSC1_nBE_8mA (1<<18) | ||
114 | #define S3C2440_DSC1_nBE_6mA (2<<18) | ||
115 | #define S3C2440_DSC1_nBE_4mA (3<<18) | ||
116 | #define S3C2440_DSC1_nBE_MASK (3<<18) | ||
117 | |||
118 | #define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16) | ||
119 | #define S3C2440_DSC1_WOE_10mA (0<<16) | ||
120 | #define S3C2440_DSC1_WOE_8mA (1<<16) | ||
121 | #define S3C2440_DSC1_WOE_6mA (2<<16) | ||
122 | #define S3C2440_DSC1_WOE_4mA (3<<16) | ||
123 | #define S3C2440_DSC1_WOE_MASK (3<<16) | ||
124 | |||
125 | #define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14) | ||
126 | #define S3C2440_DSC1_CS7_10mA (0<<14) | ||
127 | #define S3C2440_DSC1_CS7_8mA (1<<14) | ||
128 | #define S3C2440_DSC1_CS7_6mA (2<<14) | ||
129 | #define S3C2440_DSC1_CS7_4mA (3<<14) | ||
130 | #define S3C2440_DSC1_CS7_MASK (3<<14) | ||
131 | |||
132 | #define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12) | ||
133 | #define S3C2440_DSC1_CS6_10mA (0<<12) | ||
134 | #define S3C2440_DSC1_CS6_8mA (1<<12) | ||
135 | #define S3C2440_DSC1_CS6_6mA (2<<12) | ||
136 | #define S3C2440_DSC1_CS6_4mA (3<<12) | ||
137 | #define S3C2440_DSC1_CS6_MASK (3<<12) | ||
138 | |||
139 | #define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10) | ||
140 | #define S3C2440_DSC1_CS5_10mA (0<<10) | ||
141 | #define S3C2440_DSC1_CS5_8mA (1<<10) | ||
142 | #define S3C2440_DSC1_CS5_6mA (2<<10) | ||
143 | #define S3C2440_DSC1_CS5_4mA (3<<10) | ||
144 | #define S3C2440_DSC1_CS5_MASK (3<<10) | ||
145 | |||
146 | #define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8) | ||
147 | #define S3C2440_DSC1_CS4_10mA (0<<8) | ||
148 | #define S3C2440_DSC1_CS4_8mA (1<<8) | ||
149 | #define S3C2440_DSC1_CS4_6mA (2<<8) | ||
150 | #define S3C2440_DSC1_CS4_4mA (3<<8) | ||
151 | #define S3C2440_DSC1_CS4_MASK (3<<8) | ||
152 | |||
153 | #define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6) | ||
154 | #define S3C2440_DSC1_CS3_10mA (0<<6) | ||
155 | #define S3C2440_DSC1_CS3_8mA (1<<6) | ||
156 | #define S3C2440_DSC1_CS3_6mA (2<<6) | ||
157 | #define S3C2440_DSC1_CS3_4mA (3<<6) | ||
158 | #define S3C2440_DSC1_CS3_MASK (3<<6) | ||
159 | |||
160 | #define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4) | ||
161 | #define S3C2440_DSC1_CS2_10mA (0<<4) | ||
162 | #define S3C2440_DSC1_CS2_8mA (1<<4) | ||
163 | #define S3C2440_DSC1_CS2_6mA (2<<4) | ||
164 | #define S3C2440_DSC1_CS2_4mA (3<<4) | ||
165 | #define S3C2440_DSC1_CS2_MASK (3<<4) | ||
166 | |||
167 | #define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2) | ||
168 | #define S3C2440_DSC1_CS1_10mA (0<<2) | ||
169 | #define S3C2440_DSC1_CS1_8mA (1<<2) | ||
170 | #define S3C2440_DSC1_CS1_6mA (2<<2) | ||
171 | #define S3C2440_DSC1_CS1_4mA (3<<2) | ||
172 | #define S3C2440_DSC1_CS1_MASK (3<<2) | ||
173 | |||
174 | #define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0) | ||
175 | #define S3C2440_DSC1_CS0_10mA (0<<0) | ||
176 | #define S3C2440_DSC1_CS0_8mA (1<<0) | ||
177 | #define S3C2440_DSC1_CS0_6mA (2<<0) | ||
178 | #define S3C2440_DSC1_CS0_4mA (3<<0) | ||
179 | #define S3C2440_DSC1_CS0_MASK (3<<0) | ||
180 | |||
181 | #endif /* CONFIG_CPU_S3C2440 */ | ||
182 | |||
183 | #endif /* __ASM_ARCH_REGS_DSC_H */ | ||
184 | |||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h new file mode 100644 index 000000000000..30bec027f5fa --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
@@ -0,0 +1,1163 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h | ||
2 | * | ||
3 | * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 GPIO register definitions | ||
11 | */ | ||
12 | |||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_GPIO_H | ||
15 | #define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $" | ||
16 | |||
17 | #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) | ||
18 | |||
19 | #define S3C2410_GPIO_BANKA (32*0) | ||
20 | #define S3C2410_GPIO_BANKB (32*1) | ||
21 | #define S3C2410_GPIO_BANKC (32*2) | ||
22 | #define S3C2410_GPIO_BANKD (32*3) | ||
23 | #define S3C2410_GPIO_BANKE (32*4) | ||
24 | #define S3C2410_GPIO_BANKF (32*5) | ||
25 | #define S3C2410_GPIO_BANKG (32*6) | ||
26 | #define S3C2410_GPIO_BANKH (32*7) | ||
27 | |||
28 | #ifdef CONFIG_CPU_S3C2400 | ||
29 | #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) | ||
30 | #define S3C24XX_MISCCR S3C2400_MISCCR | ||
31 | #else | ||
32 | #define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) | ||
33 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) | ||
34 | #endif /* CONFIG_CPU_S3C2400 */ | ||
35 | |||
36 | |||
37 | /* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */ | ||
38 | |||
39 | #define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32) | ||
40 | #define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2)) | ||
41 | #define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \ | ||
42 | (2 * (S3C2400_BANKNUM(pin)-2))) | ||
43 | |||
44 | #define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \ | ||
45 | S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \ | ||
46 | S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO) | ||
47 | |||
48 | |||
49 | #define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO) | ||
50 | #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31) | ||
51 | |||
52 | /* general configuration options */ | ||
53 | |||
54 | #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) | ||
55 | #define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ | ||
56 | #define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) | ||
57 | #define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ | ||
58 | #define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ | ||
59 | #define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ | ||
60 | |||
61 | /* register address for the GPIO registers. | ||
62 | * S3C24XX_GPIOREG2 is for the second set of registers in the | ||
63 | * GPIO which move between s3c2410 and s3c2412 type systems */ | ||
64 | |||
65 | #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) | ||
66 | #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) | ||
67 | |||
68 | |||
69 | /* configure GPIO ports A..G */ | ||
70 | |||
71 | /* port A - S3C2410: 22bits, zero in bit X makes pin X output | ||
72 | * S3C2400: 18bits, zero in bit X makes pin X output | ||
73 | * 1 makes port special function, this is default | ||
74 | */ | ||
75 | #define S3C2410_GPACON S3C2410_GPIOREG(0x00) | ||
76 | #define S3C2410_GPADAT S3C2410_GPIOREG(0x04) | ||
77 | |||
78 | #define S3C2400_GPACON S3C2410_GPIOREG(0x00) | ||
79 | #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) | ||
80 | |||
81 | #define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) | ||
82 | #define S3C2410_GPA0_OUT (0<<0) | ||
83 | #define S3C2410_GPA0_ADDR0 (1<<0) | ||
84 | |||
85 | #define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1) | ||
86 | #define S3C2410_GPA1_OUT (0<<1) | ||
87 | #define S3C2410_GPA1_ADDR16 (1<<1) | ||
88 | |||
89 | #define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2) | ||
90 | #define S3C2410_GPA2_OUT (0<<2) | ||
91 | #define S3C2410_GPA2_ADDR17 (1<<2) | ||
92 | |||
93 | #define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3) | ||
94 | #define S3C2410_GPA3_OUT (0<<3) | ||
95 | #define S3C2410_GPA3_ADDR18 (1<<3) | ||
96 | |||
97 | #define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4) | ||
98 | #define S3C2410_GPA4_OUT (0<<4) | ||
99 | #define S3C2410_GPA4_ADDR19 (1<<4) | ||
100 | |||
101 | #define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5) | ||
102 | #define S3C2410_GPA5_OUT (0<<5) | ||
103 | #define S3C2410_GPA5_ADDR20 (1<<5) | ||
104 | |||
105 | #define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6) | ||
106 | #define S3C2410_GPA6_OUT (0<<6) | ||
107 | #define S3C2410_GPA6_ADDR21 (1<<6) | ||
108 | |||
109 | #define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7) | ||
110 | #define S3C2410_GPA7_OUT (0<<7) | ||
111 | #define S3C2410_GPA7_ADDR22 (1<<7) | ||
112 | |||
113 | #define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8) | ||
114 | #define S3C2410_GPA8_OUT (0<<8) | ||
115 | #define S3C2410_GPA8_ADDR23 (1<<8) | ||
116 | |||
117 | #define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9) | ||
118 | #define S3C2410_GPA9_OUT (0<<9) | ||
119 | #define S3C2410_GPA9_ADDR24 (1<<9) | ||
120 | |||
121 | #define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) | ||
122 | #define S3C2410_GPA10_OUT (0<<10) | ||
123 | #define S3C2410_GPA10_ADDR25 (1<<10) | ||
124 | #define S3C2400_GPA10_SCKE (1<<10) | ||
125 | |||
126 | #define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) | ||
127 | #define S3C2410_GPA11_OUT (0<<11) | ||
128 | #define S3C2410_GPA11_ADDR26 (1<<11) | ||
129 | #define S3C2400_GPA11_nCAS0 (1<<11) | ||
130 | |||
131 | #define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) | ||
132 | #define S3C2410_GPA12_OUT (0<<12) | ||
133 | #define S3C2410_GPA12_nGCS1 (1<<12) | ||
134 | #define S3C2400_GPA12_nCAS1 (1<<12) | ||
135 | |||
136 | #define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) | ||
137 | #define S3C2410_GPA13_OUT (0<<13) | ||
138 | #define S3C2410_GPA13_nGCS2 (1<<13) | ||
139 | #define S3C2400_GPA13_nGCS1 (1<<13) | ||
140 | |||
141 | #define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) | ||
142 | #define S3C2410_GPA14_OUT (0<<14) | ||
143 | #define S3C2410_GPA14_nGCS3 (1<<14) | ||
144 | #define S3C2400_GPA14_nGCS2 (1<<14) | ||
145 | |||
146 | #define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) | ||
147 | #define S3C2410_GPA15_OUT (0<<15) | ||
148 | #define S3C2410_GPA15_nGCS4 (1<<15) | ||
149 | #define S3C2400_GPA15_nGCS3 (1<<15) | ||
150 | |||
151 | #define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) | ||
152 | #define S3C2410_GPA16_OUT (0<<16) | ||
153 | #define S3C2410_GPA16_nGCS5 (1<<16) | ||
154 | #define S3C2400_GPA16_nGCS4 (1<<16) | ||
155 | |||
156 | #define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) | ||
157 | #define S3C2410_GPA17_OUT (0<<17) | ||
158 | #define S3C2410_GPA17_CLE (1<<17) | ||
159 | #define S3C2400_GPA17_nGCS5 (1<<17) | ||
160 | |||
161 | #define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) | ||
162 | #define S3C2410_GPA18_OUT (0<<18) | ||
163 | #define S3C2410_GPA18_ALE (1<<18) | ||
164 | |||
165 | #define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19) | ||
166 | #define S3C2410_GPA19_OUT (0<<19) | ||
167 | #define S3C2410_GPA19_nFWE (1<<19) | ||
168 | |||
169 | #define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20) | ||
170 | #define S3C2410_GPA20_OUT (0<<20) | ||
171 | #define S3C2410_GPA20_nFRE (1<<20) | ||
172 | |||
173 | #define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21) | ||
174 | #define S3C2410_GPA21_OUT (0<<21) | ||
175 | #define S3C2410_GPA21_nRSTOUT (1<<21) | ||
176 | |||
177 | #define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22) | ||
178 | #define S3C2410_GPA22_OUT (0<<22) | ||
179 | #define S3C2410_GPA22_nFCE (1<<22) | ||
180 | |||
181 | /* 0x08 and 0x0c are reserved on S3C2410 */ | ||
182 | |||
183 | /* S3C2410: | ||
184 | * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. | ||
185 | * 00 = input, 01 = output, 10=special function, 11=reserved | ||
186 | |||
187 | * S3C2400: | ||
188 | * GPB is 16 IO pins, each configured by 2 bits each in GPBCON. | ||
189 | * 00 = input, 01 = output, 10=data, 11=special function | ||
190 | |||
191 | * bit 0,1 = pin 0, 2,3= pin 1... | ||
192 | * | ||
193 | * CPBUP = pull up resistor control, 1=disabled, 0=enabled | ||
194 | */ | ||
195 | |||
196 | #define S3C2410_GPBCON S3C2410_GPIOREG(0x10) | ||
197 | #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) | ||
198 | #define S3C2410_GPBUP S3C2410_GPIOREG(0x18) | ||
199 | |||
200 | #define S3C2400_GPBCON S3C2410_GPIOREG(0x08) | ||
201 | #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) | ||
202 | #define S3C2400_GPBUP S3C2410_GPIOREG(0x10) | ||
203 | |||
204 | /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ | ||
205 | |||
206 | #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) | ||
207 | #define S3C2410_GPB0_INP (0x00 << 0) | ||
208 | #define S3C2410_GPB0_OUTP (0x01 << 0) | ||
209 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) | ||
210 | #define S3C2400_GPB0_DATA16 (0x02 << 0) | ||
211 | |||
212 | #define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) | ||
213 | #define S3C2410_GPB1_INP (0x00 << 2) | ||
214 | #define S3C2410_GPB1_OUTP (0x01 << 2) | ||
215 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) | ||
216 | #define S3C2400_GPB1_DATA17 (0x02 << 2) | ||
217 | |||
218 | #define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) | ||
219 | #define S3C2410_GPB2_INP (0x00 << 4) | ||
220 | #define S3C2410_GPB2_OUTP (0x01 << 4) | ||
221 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) | ||
222 | #define S3C2400_GPB2_DATA18 (0x02 << 4) | ||
223 | #define S3C2400_GPB2_TCLK1 (0x03 << 4) | ||
224 | |||
225 | #define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) | ||
226 | #define S3C2410_GPB3_INP (0x00 << 6) | ||
227 | #define S3C2410_GPB3_OUTP (0x01 << 6) | ||
228 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) | ||
229 | #define S3C2400_GPB3_DATA19 (0x02 << 6) | ||
230 | #define S3C2400_GPB3_TXD1 (0x03 << 6) | ||
231 | |||
232 | #define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) | ||
233 | #define S3C2410_GPB4_INP (0x00 << 8) | ||
234 | #define S3C2410_GPB4_OUTP (0x01 << 8) | ||
235 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) | ||
236 | #define S3C2400_GPB4_DATA20 (0x02 << 8) | ||
237 | #define S3C2410_GPB4_MASK (0x03 << 8) | ||
238 | #define S3C2400_GPB4_RXD1 (0x03 << 8) | ||
239 | #define S3C2400_GPB4_MASK (0x03 << 8) | ||
240 | |||
241 | #define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) | ||
242 | #define S3C2410_GPB5_INP (0x00 << 10) | ||
243 | #define S3C2410_GPB5_OUTP (0x01 << 10) | ||
244 | #define S3C2410_GPB5_nXBACK (0x02 << 10) | ||
245 | #define S3C2443_GPB5_XBACK (0x03 << 10) | ||
246 | #define S3C2400_GPB5_DATA21 (0x02 << 10) | ||
247 | #define S3C2400_GPB5_nCTS1 (0x03 << 10) | ||
248 | |||
249 | #define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) | ||
250 | #define S3C2410_GPB6_INP (0x00 << 12) | ||
251 | #define S3C2410_GPB6_OUTP (0x01 << 12) | ||
252 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) | ||
253 | #define S3C2443_GPB6_XBREQ (0x03 << 12) | ||
254 | #define S3C2400_GPB6_DATA22 (0x02 << 12) | ||
255 | #define S3C2400_GPB6_nRTS1 (0x03 << 12) | ||
256 | |||
257 | #define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) | ||
258 | #define S3C2410_GPB7_INP (0x00 << 14) | ||
259 | #define S3C2410_GPB7_OUTP (0x01 << 14) | ||
260 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) | ||
261 | #define S3C2443_GPB7_XDACK1 (0x03 << 14) | ||
262 | #define S3C2400_GPB7_DATA23 (0x02 << 14) | ||
263 | |||
264 | #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) | ||
265 | #define S3C2410_GPB8_INP (0x00 << 16) | ||
266 | #define S3C2410_GPB8_OUTP (0x01 << 16) | ||
267 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) | ||
268 | #define S3C2400_GPB8_DATA24 (0x02 << 16) | ||
269 | |||
270 | #define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) | ||
271 | #define S3C2410_GPB9_INP (0x00 << 18) | ||
272 | #define S3C2410_GPB9_OUTP (0x01 << 18) | ||
273 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) | ||
274 | #define S3C2443_GPB9_XDACK0 (0x03 << 18) | ||
275 | #define S3C2400_GPB9_DATA25 (0x02 << 18) | ||
276 | #define S3C2400_GPB9_I2SSDI (0x03 << 18) | ||
277 | |||
278 | #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) | ||
279 | #define S3C2410_GPB10_INP (0x00 << 20) | ||
280 | #define S3C2410_GPB10_OUTP (0x01 << 20) | ||
281 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) | ||
282 | #define S3C2443_GPB10_XDREQ0 (0x03 << 20) | ||
283 | #define S3C2400_GPB10_DATA26 (0x02 << 20) | ||
284 | #define S3C2400_GPB10_nSS (0x03 << 20) | ||
285 | |||
286 | #define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11) | ||
287 | #define S3C2400_GPB11_INP (0x00 << 22) | ||
288 | #define S3C2400_GPB11_OUTP (0x01 << 22) | ||
289 | #define S3C2400_GPB11_DATA27 (0x02 << 22) | ||
290 | |||
291 | #define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12) | ||
292 | #define S3C2400_GPB12_INP (0x00 << 24) | ||
293 | #define S3C2400_GPB12_OUTP (0x01 << 24) | ||
294 | #define S3C2400_GPB12_DATA28 (0x02 << 24) | ||
295 | |||
296 | #define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13) | ||
297 | #define S3C2400_GPB13_INP (0x00 << 26) | ||
298 | #define S3C2400_GPB13_OUTP (0x01 << 26) | ||
299 | #define S3C2400_GPB13_DATA29 (0x02 << 26) | ||
300 | |||
301 | #define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14) | ||
302 | #define S3C2400_GPB14_INP (0x00 << 28) | ||
303 | #define S3C2400_GPB14_OUTP (0x01 << 28) | ||
304 | #define S3C2400_GPB14_DATA30 (0x02 << 28) | ||
305 | |||
306 | #define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15) | ||
307 | #define S3C2400_GPB15_INP (0x00 << 30) | ||
308 | #define S3C2400_GPB15_OUTP (0x01 << 30) | ||
309 | #define S3C2400_GPB15_DATA31 (0x02 << 30) | ||
310 | |||
311 | #define S3C2410_GPB_PUPDIS(x) (1<<(x)) | ||
312 | |||
313 | /* Port C consits of 16 GPIO/Special function | ||
314 | * | ||
315 | * almost identical setup to port b, but the special functions are mostly | ||
316 | * to do with the video system's sync/etc. | ||
317 | */ | ||
318 | |||
319 | #define S3C2410_GPCCON S3C2410_GPIOREG(0x20) | ||
320 | #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) | ||
321 | #define S3C2410_GPCUP S3C2410_GPIOREG(0x28) | ||
322 | |||
323 | #define S3C2400_GPCCON S3C2410_GPIOREG(0x14) | ||
324 | #define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) | ||
325 | #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) | ||
326 | |||
327 | #define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) | ||
328 | #define S3C2410_GPC0_INP (0x00 << 0) | ||
329 | #define S3C2410_GPC0_OUTP (0x01 << 0) | ||
330 | #define S3C2410_GPC0_LEND (0x02 << 0) | ||
331 | #define S3C2400_GPC0_VD0 (0x02 << 0) | ||
332 | |||
333 | #define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) | ||
334 | #define S3C2410_GPC1_INP (0x00 << 2) | ||
335 | #define S3C2410_GPC1_OUTP (0x01 << 2) | ||
336 | #define S3C2410_GPC1_VCLK (0x02 << 2) | ||
337 | #define S3C2400_GPC1_VD1 (0x02 << 2) | ||
338 | |||
339 | #define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) | ||
340 | #define S3C2410_GPC2_INP (0x00 << 4) | ||
341 | #define S3C2410_GPC2_OUTP (0x01 << 4) | ||
342 | #define S3C2410_GPC2_VLINE (0x02 << 4) | ||
343 | #define S3C2400_GPC2_VD2 (0x02 << 4) | ||
344 | |||
345 | #define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) | ||
346 | #define S3C2410_GPC3_INP (0x00 << 6) | ||
347 | #define S3C2410_GPC3_OUTP (0x01 << 6) | ||
348 | #define S3C2410_GPC3_VFRAME (0x02 << 6) | ||
349 | #define S3C2400_GPC3_VD3 (0x02 << 6) | ||
350 | |||
351 | #define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) | ||
352 | #define S3C2410_GPC4_INP (0x00 << 8) | ||
353 | #define S3C2410_GPC4_OUTP (0x01 << 8) | ||
354 | #define S3C2410_GPC4_VM (0x02 << 8) | ||
355 | #define S3C2400_GPC4_VD4 (0x02 << 8) | ||
356 | |||
357 | #define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) | ||
358 | #define S3C2410_GPC5_INP (0x00 << 10) | ||
359 | #define S3C2410_GPC5_OUTP (0x01 << 10) | ||
360 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) | ||
361 | #define S3C2400_GPC5_VD5 (0x02 << 10) | ||
362 | |||
363 | #define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) | ||
364 | #define S3C2410_GPC6_INP (0x00 << 12) | ||
365 | #define S3C2410_GPC6_OUTP (0x01 << 12) | ||
366 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) | ||
367 | #define S3C2400_GPC6_VD6 (0x02 << 12) | ||
368 | |||
369 | #define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) | ||
370 | #define S3C2410_GPC7_INP (0x00 << 14) | ||
371 | #define S3C2410_GPC7_OUTP (0x01 << 14) | ||
372 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) | ||
373 | #define S3C2400_GPC7_VD7 (0x02 << 14) | ||
374 | |||
375 | #define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) | ||
376 | #define S3C2410_GPC8_INP (0x00 << 16) | ||
377 | #define S3C2410_GPC8_OUTP (0x01 << 16) | ||
378 | #define S3C2410_GPC8_VD0 (0x02 << 16) | ||
379 | #define S3C2400_GPC8_VD8 (0x02 << 16) | ||
380 | |||
381 | #define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) | ||
382 | #define S3C2410_GPC9_INP (0x00 << 18) | ||
383 | #define S3C2410_GPC9_OUTP (0x01 << 18) | ||
384 | #define S3C2410_GPC9_VD1 (0x02 << 18) | ||
385 | #define S3C2400_GPC9_VD9 (0x02 << 18) | ||
386 | |||
387 | #define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) | ||
388 | #define S3C2410_GPC10_INP (0x00 << 20) | ||
389 | #define S3C2410_GPC10_OUTP (0x01 << 20) | ||
390 | #define S3C2410_GPC10_VD2 (0x02 << 20) | ||
391 | #define S3C2400_GPC10_VD10 (0x02 << 20) | ||
392 | |||
393 | #define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) | ||
394 | #define S3C2410_GPC11_INP (0x00 << 22) | ||
395 | #define S3C2410_GPC11_OUTP (0x01 << 22) | ||
396 | #define S3C2410_GPC11_VD3 (0x02 << 22) | ||
397 | #define S3C2400_GPC11_VD11 (0x02 << 22) | ||
398 | |||
399 | #define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) | ||
400 | #define S3C2410_GPC12_INP (0x00 << 24) | ||
401 | #define S3C2410_GPC12_OUTP (0x01 << 24) | ||
402 | #define S3C2410_GPC12_VD4 (0x02 << 24) | ||
403 | #define S3C2400_GPC12_VD12 (0x02 << 24) | ||
404 | |||
405 | #define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) | ||
406 | #define S3C2410_GPC13_INP (0x00 << 26) | ||
407 | #define S3C2410_GPC13_OUTP (0x01 << 26) | ||
408 | #define S3C2410_GPC13_VD5 (0x02 << 26) | ||
409 | #define S3C2400_GPC13_VD13 (0x02 << 26) | ||
410 | |||
411 | #define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) | ||
412 | #define S3C2410_GPC14_INP (0x00 << 28) | ||
413 | #define S3C2410_GPC14_OUTP (0x01 << 28) | ||
414 | #define S3C2410_GPC14_VD6 (0x02 << 28) | ||
415 | #define S3C2400_GPC14_VD14 (0x02 << 28) | ||
416 | |||
417 | #define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) | ||
418 | #define S3C2410_GPC15_INP (0x00 << 30) | ||
419 | #define S3C2410_GPC15_OUTP (0x01 << 30) | ||
420 | #define S3C2410_GPC15_VD7 (0x02 << 30) | ||
421 | #define S3C2400_GPC15_VD15 (0x02 << 30) | ||
422 | |||
423 | #define S3C2410_GPC_PUPDIS(x) (1<<(x)) | ||
424 | |||
425 | /* | ||
426 | * S3C2410: Port D consists of 16 GPIO/Special function | ||
427 | * | ||
428 | * almost identical setup to port b, but the special functions are mostly | ||
429 | * to do with the video system's data. | ||
430 | * | ||
431 | * S3C2400: Port D consists of 11 GPIO/Special function | ||
432 | * | ||
433 | * almost identical setup to port c | ||
434 | */ | ||
435 | |||
436 | #define S3C2410_GPDCON S3C2410_GPIOREG(0x30) | ||
437 | #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) | ||
438 | #define S3C2410_GPDUP S3C2410_GPIOREG(0x38) | ||
439 | |||
440 | #define S3C2400_GPDCON S3C2410_GPIOREG(0x20) | ||
441 | #define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) | ||
442 | #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) | ||
443 | |||
444 | #define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) | ||
445 | #define S3C2410_GPD0_INP (0x00 << 0) | ||
446 | #define S3C2410_GPD0_OUTP (0x01 << 0) | ||
447 | #define S3C2410_GPD0_VD8 (0x02 << 0) | ||
448 | #define S3C2400_GPD0_VFRAME (0x02 << 0) | ||
449 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) | ||
450 | |||
451 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) | ||
452 | #define S3C2410_GPD1_INP (0x00 << 2) | ||
453 | #define S3C2410_GPD1_OUTP (0x01 << 2) | ||
454 | #define S3C2410_GPD1_VD9 (0x02 << 2) | ||
455 | #define S3C2400_GPD1_VM (0x02 << 2) | ||
456 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) | ||
457 | |||
458 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) | ||
459 | #define S3C2410_GPD2_INP (0x00 << 4) | ||
460 | #define S3C2410_GPD2_OUTP (0x01 << 4) | ||
461 | #define S3C2410_GPD2_VD10 (0x02 << 4) | ||
462 | #define S3C2400_GPD2_VLINE (0x02 << 4) | ||
463 | |||
464 | #define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) | ||
465 | #define S3C2410_GPD3_INP (0x00 << 6) | ||
466 | #define S3C2410_GPD3_OUTP (0x01 << 6) | ||
467 | #define S3C2410_GPD3_VD11 (0x02 << 6) | ||
468 | #define S3C2400_GPD3_VCLK (0x02 << 6) | ||
469 | |||
470 | #define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) | ||
471 | #define S3C2410_GPD4_INP (0x00 << 8) | ||
472 | #define S3C2410_GPD4_OUTP (0x01 << 8) | ||
473 | #define S3C2410_GPD4_VD12 (0x02 << 8) | ||
474 | #define S3C2400_GPD4_LEND (0x02 << 8) | ||
475 | |||
476 | #define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) | ||
477 | #define S3C2410_GPD5_INP (0x00 << 10) | ||
478 | #define S3C2410_GPD5_OUTP (0x01 << 10) | ||
479 | #define S3C2410_GPD5_VD13 (0x02 << 10) | ||
480 | #define S3C2400_GPD5_TOUT0 (0x02 << 10) | ||
481 | |||
482 | #define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) | ||
483 | #define S3C2410_GPD6_INP (0x00 << 12) | ||
484 | #define S3C2410_GPD6_OUTP (0x01 << 12) | ||
485 | #define S3C2410_GPD6_VD14 (0x02 << 12) | ||
486 | #define S3C2400_GPD6_TOUT1 (0x02 << 12) | ||
487 | |||
488 | #define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) | ||
489 | #define S3C2410_GPD7_INP (0x00 << 14) | ||
490 | #define S3C2410_GPD7_OUTP (0x01 << 14) | ||
491 | #define S3C2410_GPD7_VD15 (0x02 << 14) | ||
492 | #define S3C2400_GPD7_TOUT2 (0x02 << 14) | ||
493 | |||
494 | #define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) | ||
495 | #define S3C2410_GPD8_INP (0x00 << 16) | ||
496 | #define S3C2410_GPD8_OUTP (0x01 << 16) | ||
497 | #define S3C2410_GPD8_VD16 (0x02 << 16) | ||
498 | #define S3C2400_GPD8_TOUT3 (0x02 << 16) | ||
499 | |||
500 | #define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) | ||
501 | #define S3C2410_GPD9_INP (0x00 << 18) | ||
502 | #define S3C2410_GPD9_OUTP (0x01 << 18) | ||
503 | #define S3C2410_GPD9_VD17 (0x02 << 18) | ||
504 | #define S3C2400_GPD9_TCLK0 (0x02 << 18) | ||
505 | #define S3C2410_GPD9_MASK (0x03 << 18) | ||
506 | |||
507 | #define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) | ||
508 | #define S3C2410_GPD10_INP (0x00 << 20) | ||
509 | #define S3C2410_GPD10_OUTP (0x01 << 20) | ||
510 | #define S3C2410_GPD10_VD18 (0x02 << 20) | ||
511 | #define S3C2400_GPD10_nWAIT (0x02 << 20) | ||
512 | |||
513 | #define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) | ||
514 | #define S3C2410_GPD11_INP (0x00 << 22) | ||
515 | #define S3C2410_GPD11_OUTP (0x01 << 22) | ||
516 | #define S3C2410_GPD11_VD19 (0x02 << 22) | ||
517 | |||
518 | #define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12) | ||
519 | #define S3C2410_GPD12_INP (0x00 << 24) | ||
520 | #define S3C2410_GPD12_OUTP (0x01 << 24) | ||
521 | #define S3C2410_GPD12_VD20 (0x02 << 24) | ||
522 | |||
523 | #define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13) | ||
524 | #define S3C2410_GPD13_INP (0x00 << 26) | ||
525 | #define S3C2410_GPD13_OUTP (0x01 << 26) | ||
526 | #define S3C2410_GPD13_VD21 (0x02 << 26) | ||
527 | |||
528 | #define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14) | ||
529 | #define S3C2410_GPD14_INP (0x00 << 28) | ||
530 | #define S3C2410_GPD14_OUTP (0x01 << 28) | ||
531 | #define S3C2410_GPD14_VD22 (0x02 << 28) | ||
532 | #define S3C2410_GPD14_nSS1 (0x03 << 28) | ||
533 | |||
534 | #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) | ||
535 | #define S3C2410_GPD15_INP (0x00 << 30) | ||
536 | #define S3C2410_GPD15_OUTP (0x01 << 30) | ||
537 | #define S3C2410_GPD15_VD23 (0x02 << 30) | ||
538 | #define S3C2410_GPD15_nSS0 (0x03 << 30) | ||
539 | |||
540 | #define S3C2410_GPD_PUPDIS(x) (1<<(x)) | ||
541 | |||
542 | /* S3C2410: | ||
543 | * Port E consists of 16 GPIO/Special function | ||
544 | * | ||
545 | * again, the same as port B, but dealing with I2S, SDI, and | ||
546 | * more miscellaneous functions | ||
547 | * | ||
548 | * S3C2400: | ||
549 | * Port E consists of 12 GPIO/Special function | ||
550 | * | ||
551 | * GPIO / interrupt inputs | ||
552 | */ | ||
553 | |||
554 | #define S3C2410_GPECON S3C2410_GPIOREG(0x40) | ||
555 | #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) | ||
556 | #define S3C2410_GPEUP S3C2410_GPIOREG(0x48) | ||
557 | |||
558 | #define S3C2400_GPECON S3C2410_GPIOREG(0x2C) | ||
559 | #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) | ||
560 | #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) | ||
561 | |||
562 | #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) | ||
563 | #define S3C2410_GPE0_INP (0x00 << 0) | ||
564 | #define S3C2410_GPE0_OUTP (0x01 << 0) | ||
565 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) | ||
566 | #define S3C2443_GPE0_AC_nRESET (0x03 << 0) | ||
567 | #define S3C2400_GPE0_EINT0 (0x02 << 0) | ||
568 | #define S3C2410_GPE0_MASK (0x03 << 0) | ||
569 | |||
570 | #define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) | ||
571 | #define S3C2410_GPE1_INP (0x00 << 2) | ||
572 | #define S3C2410_GPE1_OUTP (0x01 << 2) | ||
573 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) | ||
574 | #define S3C2443_GPE1_AC_SYNC (0x03 << 2) | ||
575 | #define S3C2400_GPE1_EINT1 (0x02 << 2) | ||
576 | #define S3C2400_GPE1_nSS (0x03 << 2) | ||
577 | #define S3C2410_GPE1_MASK (0x03 << 2) | ||
578 | |||
579 | #define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) | ||
580 | #define S3C2410_GPE2_INP (0x00 << 4) | ||
581 | #define S3C2410_GPE2_OUTP (0x01 << 4) | ||
582 | #define S3C2410_GPE2_CDCLK (0x02 << 4) | ||
583 | #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) | ||
584 | #define S3C2400_GPE2_EINT2 (0x02 << 4) | ||
585 | #define S3C2400_GPE2_I2SSDI (0x03 << 4) | ||
586 | |||
587 | #define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) | ||
588 | #define S3C2410_GPE3_INP (0x00 << 6) | ||
589 | #define S3C2410_GPE3_OUTP (0x01 << 6) | ||
590 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) | ||
591 | #define S3C2443_GPE3_AC_SDI (0x03 << 6) | ||
592 | #define S3C2400_GPE3_EINT3 (0x02 << 6) | ||
593 | #define S3C2400_GPE3_nCTS1 (0x03 << 6) | ||
594 | #define S3C2410_GPE3_nSS0 (0x03 << 6) | ||
595 | #define S3C2410_GPE3_MASK (0x03 << 6) | ||
596 | |||
597 | #define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4) | ||
598 | #define S3C2410_GPE4_INP (0x00 << 8) | ||
599 | #define S3C2410_GPE4_OUTP (0x01 << 8) | ||
600 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) | ||
601 | #define S3C2443_GPE4_AC_SDO (0x03 << 8) | ||
602 | #define S3C2400_GPE4_EINT4 (0x02 << 8) | ||
603 | #define S3C2400_GPE4_nRTS1 (0x03 << 8) | ||
604 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) | ||
605 | #define S3C2410_GPE4_MASK (0x03 << 8) | ||
606 | |||
607 | #define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5) | ||
608 | #define S3C2410_GPE5_INP (0x00 << 10) | ||
609 | #define S3C2410_GPE5_OUTP (0x01 << 10) | ||
610 | #define S3C2410_GPE5_SDCLK (0x02 << 10) | ||
611 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) | ||
612 | #define S3C2400_GPE5_EINT5 (0x02 << 10) | ||
613 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) | ||
614 | |||
615 | #define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) | ||
616 | #define S3C2410_GPE6_INP (0x00 << 12) | ||
617 | #define S3C2410_GPE6_OUTP (0x01 << 12) | ||
618 | #define S3C2410_GPE6_SDCMD (0x02 << 12) | ||
619 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) | ||
620 | #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) | ||
621 | #define S3C2400_GPE6_EINT6 (0x02 << 12) | ||
622 | |||
623 | #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) | ||
624 | #define S3C2410_GPE7_INP (0x00 << 14) | ||
625 | #define S3C2410_GPE7_OUTP (0x01 << 14) | ||
626 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) | ||
627 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) | ||
628 | #define S3C2443_GPE7_AC_SDI (0x03 << 14) | ||
629 | #define S3C2400_GPE7_EINT7 (0x02 << 14) | ||
630 | |||
631 | #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) | ||
632 | #define S3C2410_GPE8_INP (0x00 << 16) | ||
633 | #define S3C2410_GPE8_OUTP (0x01 << 16) | ||
634 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) | ||
635 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) | ||
636 | #define S3C2443_GPE8_AC_SDO (0x03 << 16) | ||
637 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) | ||
638 | |||
639 | #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) | ||
640 | #define S3C2410_GPE9_INP (0x00 << 18) | ||
641 | #define S3C2410_GPE9_OUTP (0x01 << 18) | ||
642 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) | ||
643 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) | ||
644 | #define S3C2443_GPE9_AC_SYNC (0x03 << 18) | ||
645 | #define S3C2400_GPE9_nXDACK1 (0x02 << 18) | ||
646 | #define S3C2400_GPE9_nXBACK (0x03 << 18) | ||
647 | |||
648 | #define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) | ||
649 | #define S3C2410_GPE10_INP (0x00 << 20) | ||
650 | #define S3C2410_GPE10_OUTP (0x01 << 20) | ||
651 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) | ||
652 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) | ||
653 | #define S3C2443_GPE10_AC_nRESET (0x03 << 20) | ||
654 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) | ||
655 | |||
656 | #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) | ||
657 | #define S3C2410_GPE11_INP (0x00 << 22) | ||
658 | #define S3C2410_GPE11_OUTP (0x01 << 22) | ||
659 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) | ||
660 | #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) | ||
661 | #define S3C2400_GPE11_nXBREQ (0x03 << 22) | ||
662 | |||
663 | #define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) | ||
664 | #define S3C2410_GPE12_INP (0x00 << 24) | ||
665 | #define S3C2410_GPE12_OUTP (0x01 << 24) | ||
666 | #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) | ||
667 | |||
668 | #define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13) | ||
669 | #define S3C2410_GPE13_INP (0x00 << 26) | ||
670 | #define S3C2410_GPE13_OUTP (0x01 << 26) | ||
671 | #define S3C2410_GPE13_SPICLK0 (0x02 << 26) | ||
672 | |||
673 | #define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14) | ||
674 | #define S3C2410_GPE14_INP (0x00 << 28) | ||
675 | #define S3C2410_GPE14_OUTP (0x01 << 28) | ||
676 | #define S3C2410_GPE14_IICSCL (0x02 << 28) | ||
677 | #define S3C2410_GPE14_MASK (0x03 << 28) | ||
678 | |||
679 | #define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15) | ||
680 | #define S3C2410_GPE15_INP (0x00 << 30) | ||
681 | #define S3C2410_GPE15_OUTP (0x01 << 30) | ||
682 | #define S3C2410_GPE15_IICSDA (0x02 << 30) | ||
683 | #define S3C2410_GPE15_MASK (0x03 << 30) | ||
684 | |||
685 | #define S3C2440_GPE0_ACSYNC (0x03 << 0) | ||
686 | #define S3C2440_GPE1_ACBITCLK (0x03 << 2) | ||
687 | #define S3C2440_GPE2_ACRESET (0x03 << 4) | ||
688 | #define S3C2440_GPE3_ACIN (0x03 << 6) | ||
689 | #define S3C2440_GPE4_ACOUT (0x03 << 8) | ||
690 | |||
691 | #define S3C2410_GPE_PUPDIS(x) (1<<(x)) | ||
692 | |||
693 | /* S3C2410: | ||
694 | * Port F consists of 8 GPIO/Special function | ||
695 | * | ||
696 | * GPIO / interrupt inputs | ||
697 | * | ||
698 | * GPFCON has 2 bits for each of the input pins on port F | ||
699 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined | ||
700 | * | ||
701 | * pull up works like all other ports. | ||
702 | * | ||
703 | * S3C2400: | ||
704 | * Port F consists of 7 GPIO/Special function | ||
705 | * | ||
706 | * GPIO/serial/misc pins | ||
707 | */ | ||
708 | |||
709 | #define S3C2410_GPFCON S3C2410_GPIOREG(0x50) | ||
710 | #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) | ||
711 | #define S3C2410_GPFUP S3C2410_GPIOREG(0x58) | ||
712 | |||
713 | #define S3C2400_GPFCON S3C2410_GPIOREG(0x38) | ||
714 | #define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) | ||
715 | #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) | ||
716 | |||
717 | #define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) | ||
718 | #define S3C2410_GPF0_INP (0x00 << 0) | ||
719 | #define S3C2410_GPF0_OUTP (0x01 << 0) | ||
720 | #define S3C2410_GPF0_EINT0 (0x02 << 0) | ||
721 | #define S3C2400_GPF0_RXD0 (0x02 << 0) | ||
722 | |||
723 | #define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) | ||
724 | #define S3C2410_GPF1_INP (0x00 << 2) | ||
725 | #define S3C2410_GPF1_OUTP (0x01 << 2) | ||
726 | #define S3C2410_GPF1_EINT1 (0x02 << 2) | ||
727 | #define S3C2400_GPF1_RXD1 (0x02 << 2) | ||
728 | #define S3C2400_GPF1_IICSDA (0x03 << 2) | ||
729 | |||
730 | #define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) | ||
731 | #define S3C2410_GPF2_INP (0x00 << 4) | ||
732 | #define S3C2410_GPF2_OUTP (0x01 << 4) | ||
733 | #define S3C2410_GPF2_EINT2 (0x02 << 4) | ||
734 | #define S3C2400_GPF2_TXD0 (0x02 << 4) | ||
735 | |||
736 | #define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) | ||
737 | #define S3C2410_GPF3_INP (0x00 << 6) | ||
738 | #define S3C2410_GPF3_OUTP (0x01 << 6) | ||
739 | #define S3C2410_GPF3_EINT3 (0x02 << 6) | ||
740 | #define S3C2400_GPF3_TXD1 (0x02 << 6) | ||
741 | #define S3C2400_GPF3_IICSCL (0x03 << 6) | ||
742 | |||
743 | #define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) | ||
744 | #define S3C2410_GPF4_INP (0x00 << 8) | ||
745 | #define S3C2410_GPF4_OUTP (0x01 << 8) | ||
746 | #define S3C2410_GPF4_EINT4 (0x02 << 8) | ||
747 | #define S3C2400_GPF4_nRTS0 (0x02 << 8) | ||
748 | #define S3C2400_GPF4_nXBACK (0x03 << 8) | ||
749 | |||
750 | #define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) | ||
751 | #define S3C2410_GPF5_INP (0x00 << 10) | ||
752 | #define S3C2410_GPF5_OUTP (0x01 << 10) | ||
753 | #define S3C2410_GPF5_EINT5 (0x02 << 10) | ||
754 | #define S3C2400_GPF5_nCTS0 (0x02 << 10) | ||
755 | #define S3C2400_GPF5_nXBREQ (0x03 << 10) | ||
756 | |||
757 | #define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) | ||
758 | #define S3C2410_GPF6_INP (0x00 << 12) | ||
759 | #define S3C2410_GPF6_OUTP (0x01 << 12) | ||
760 | #define S3C2410_GPF6_EINT6 (0x02 << 12) | ||
761 | #define S3C2400_GPF6_CLKOUT (0x02 << 12) | ||
762 | |||
763 | #define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) | ||
764 | #define S3C2410_GPF7_INP (0x00 << 14) | ||
765 | #define S3C2410_GPF7_OUTP (0x01 << 14) | ||
766 | #define S3C2410_GPF7_EINT7 (0x02 << 14) | ||
767 | |||
768 | #define S3C2410_GPF_PUPDIS(x) (1<<(x)) | ||
769 | |||
770 | /* S3C2410: | ||
771 | * Port G consists of 8 GPIO/IRQ/Special function | ||
772 | * | ||
773 | * GPGCON has 2 bits for each of the input pins on port F | ||
774 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | ||
775 | * | ||
776 | * pull up works like all other ports. | ||
777 | * | ||
778 | * S3C2400: | ||
779 | * Port G consists of 10 GPIO/Special function | ||
780 | */ | ||
781 | |||
782 | #define S3C2410_GPGCON S3C2410_GPIOREG(0x60) | ||
783 | #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) | ||
784 | #define S3C2410_GPGUP S3C2410_GPIOREG(0x68) | ||
785 | |||
786 | #define S3C2400_GPGCON S3C2410_GPIOREG(0x44) | ||
787 | #define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) | ||
788 | #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) | ||
789 | |||
790 | #define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) | ||
791 | #define S3C2410_GPG0_INP (0x00 << 0) | ||
792 | #define S3C2410_GPG0_OUTP (0x01 << 0) | ||
793 | #define S3C2410_GPG0_EINT8 (0x02 << 0) | ||
794 | #define S3C2400_GPG0_I2SLRCK (0x02 << 0) | ||
795 | |||
796 | #define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) | ||
797 | #define S3C2410_GPG1_INP (0x00 << 2) | ||
798 | #define S3C2410_GPG1_OUTP (0x01 << 2) | ||
799 | #define S3C2410_GPG1_EINT9 (0x02 << 2) | ||
800 | #define S3C2400_GPG1_I2SSCLK (0x02 << 2) | ||
801 | |||
802 | #define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) | ||
803 | #define S3C2410_GPG2_INP (0x00 << 4) | ||
804 | #define S3C2410_GPG2_OUTP (0x01 << 4) | ||
805 | #define S3C2410_GPG2_EINT10 (0x02 << 4) | ||
806 | #define S3C2410_GPG2_nSS0 (0x03 << 4) | ||
807 | #define S3C2400_GPG2_CDCLK (0x02 << 4) | ||
808 | |||
809 | #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) | ||
810 | #define S3C2410_GPG3_INP (0x00 << 6) | ||
811 | #define S3C2410_GPG3_OUTP (0x01 << 6) | ||
812 | #define S3C2410_GPG3_EINT11 (0x02 << 6) | ||
813 | #define S3C2410_GPG3_nSS1 (0x03 << 6) | ||
814 | #define S3C2400_GPG3_I2SSDO (0x02 << 6) | ||
815 | #define S3C2400_GPG3_I2SSDI (0x03 << 6) | ||
816 | |||
817 | #define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) | ||
818 | #define S3C2410_GPG4_INP (0x00 << 8) | ||
819 | #define S3C2410_GPG4_OUTP (0x01 << 8) | ||
820 | #define S3C2410_GPG4_EINT12 (0x02 << 8) | ||
821 | #define S3C2400_GPG4_MMCCLK (0x02 << 8) | ||
822 | #define S3C2400_GPG4_I2SSDI (0x03 << 8) | ||
823 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) | ||
824 | #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) | ||
825 | |||
826 | #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) | ||
827 | #define S3C2410_GPG5_INP (0x00 << 10) | ||
828 | #define S3C2410_GPG5_OUTP (0x01 << 10) | ||
829 | #define S3C2410_GPG5_EINT13 (0x02 << 10) | ||
830 | #define S3C2400_GPG5_MMCCMD (0x02 << 10) | ||
831 | #define S3C2400_GPG5_IICSDA (0x03 << 10) | ||
832 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ | ||
833 | |||
834 | #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) | ||
835 | #define S3C2410_GPG6_INP (0x00 << 12) | ||
836 | #define S3C2410_GPG6_OUTP (0x01 << 12) | ||
837 | #define S3C2410_GPG6_EINT14 (0x02 << 12) | ||
838 | #define S3C2400_GPG6_MMCDAT (0x02 << 12) | ||
839 | #define S3C2400_GPG6_IICSCL (0x03 << 12) | ||
840 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) | ||
841 | |||
842 | #define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) | ||
843 | #define S3C2410_GPG7_INP (0x00 << 14) | ||
844 | #define S3C2410_GPG7_OUTP (0x01 << 14) | ||
845 | #define S3C2410_GPG7_EINT15 (0x02 << 14) | ||
846 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) | ||
847 | #define S3C2400_GPG7_SPIMISO (0x02 << 14) | ||
848 | #define S3C2400_GPG7_IICSDA (0x03 << 14) | ||
849 | |||
850 | #define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) | ||
851 | #define S3C2410_GPG8_INP (0x00 << 16) | ||
852 | #define S3C2410_GPG8_OUTP (0x01 << 16) | ||
853 | #define S3C2410_GPG8_EINT16 (0x02 << 16) | ||
854 | #define S3C2400_GPG8_SPIMOSI (0x02 << 16) | ||
855 | #define S3C2400_GPG8_IICSCL (0x03 << 16) | ||
856 | |||
857 | #define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) | ||
858 | #define S3C2410_GPG9_INP (0x00 << 18) | ||
859 | #define S3C2410_GPG9_OUTP (0x01 << 18) | ||
860 | #define S3C2410_GPG9_EINT17 (0x02 << 18) | ||
861 | #define S3C2400_GPG9_SPICLK (0x02 << 18) | ||
862 | #define S3C2400_GPG9_MMCCLK (0x03 << 18) | ||
863 | |||
864 | #define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) | ||
865 | #define S3C2410_GPG10_INP (0x00 << 20) | ||
866 | #define S3C2410_GPG10_OUTP (0x01 << 20) | ||
867 | #define S3C2410_GPG10_EINT18 (0x02 << 20) | ||
868 | |||
869 | #define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11) | ||
870 | #define S3C2410_GPG11_INP (0x00 << 22) | ||
871 | #define S3C2410_GPG11_OUTP (0x01 << 22) | ||
872 | #define S3C2410_GPG11_EINT19 (0x02 << 22) | ||
873 | #define S3C2410_GPG11_TCLK1 (0x03 << 22) | ||
874 | #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) | ||
875 | |||
876 | #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) | ||
877 | #define S3C2410_GPG12_INP (0x00 << 24) | ||
878 | #define S3C2410_GPG12_OUTP (0x01 << 24) | ||
879 | #define S3C2410_GPG12_EINT20 (0x02 << 24) | ||
880 | #define S3C2410_GPG12_XMON (0x03 << 24) | ||
881 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) | ||
882 | #define S3C2443_GPG12_nINPACK (0x03 << 24) | ||
883 | |||
884 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) | ||
885 | #define S3C2410_GPG13_INP (0x00 << 26) | ||
886 | #define S3C2410_GPG13_OUTP (0x01 << 26) | ||
887 | #define S3C2410_GPG13_EINT21 (0x02 << 26) | ||
888 | #define S3C2410_GPG13_nXPON (0x03 << 26) | ||
889 | #define S3C2443_GPG13_CF_nREG (0x03 << 26) | ||
890 | |||
891 | #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) | ||
892 | #define S3C2410_GPG14_INP (0x00 << 28) | ||
893 | #define S3C2410_GPG14_OUTP (0x01 << 28) | ||
894 | #define S3C2410_GPG14_EINT22 (0x02 << 28) | ||
895 | #define S3C2410_GPG14_YMON (0x03 << 28) | ||
896 | #define S3C2443_GPG14_CF_RESET (0x03 << 28) | ||
897 | |||
898 | #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) | ||
899 | #define S3C2410_GPG15_INP (0x00 << 30) | ||
900 | #define S3C2410_GPG15_OUTP (0x01 << 30) | ||
901 | #define S3C2410_GPG15_EINT23 (0x02 << 30) | ||
902 | #define S3C2410_GPG15_nYPON (0x03 << 30) | ||
903 | #define S3C2443_GPG15_CF_PWR (0x03 << 30) | ||
904 | |||
905 | #define S3C2410_GPG_PUPDIS(x) (1<<(x)) | ||
906 | |||
907 | /* Port H consists of11 GPIO/serial/Misc pins | ||
908 | * | ||
909 | * GPGCON has 2 bits for each of the input pins on port F | ||
910 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | ||
911 | * | ||
912 | * pull up works like all other ports. | ||
913 | */ | ||
914 | |||
915 | #define S3C2410_GPHCON S3C2410_GPIOREG(0x70) | ||
916 | #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) | ||
917 | #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) | ||
918 | |||
919 | #define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0) | ||
920 | #define S3C2410_GPH0_INP (0x00 << 0) | ||
921 | #define S3C2410_GPH0_OUTP (0x01 << 0) | ||
922 | #define S3C2410_GPH0_nCTS0 (0x02 << 0) | ||
923 | |||
924 | #define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1) | ||
925 | #define S3C2410_GPH1_INP (0x00 << 2) | ||
926 | #define S3C2410_GPH1_OUTP (0x01 << 2) | ||
927 | #define S3C2410_GPH1_nRTS0 (0x02 << 2) | ||
928 | |||
929 | #define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2) | ||
930 | #define S3C2410_GPH2_INP (0x00 << 4) | ||
931 | #define S3C2410_GPH2_OUTP (0x01 << 4) | ||
932 | #define S3C2410_GPH2_TXD0 (0x02 << 4) | ||
933 | |||
934 | #define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3) | ||
935 | #define S3C2410_GPH3_INP (0x00 << 6) | ||
936 | #define S3C2410_GPH3_OUTP (0x01 << 6) | ||
937 | #define S3C2410_GPH3_RXD0 (0x02 << 6) | ||
938 | |||
939 | #define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4) | ||
940 | #define S3C2410_GPH4_INP (0x00 << 8) | ||
941 | #define S3C2410_GPH4_OUTP (0x01 << 8) | ||
942 | #define S3C2410_GPH4_TXD1 (0x02 << 8) | ||
943 | |||
944 | #define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5) | ||
945 | #define S3C2410_GPH5_INP (0x00 << 10) | ||
946 | #define S3C2410_GPH5_OUTP (0x01 << 10) | ||
947 | #define S3C2410_GPH5_RXD1 (0x02 << 10) | ||
948 | |||
949 | #define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6) | ||
950 | #define S3C2410_GPH6_INP (0x00 << 12) | ||
951 | #define S3C2410_GPH6_OUTP (0x01 << 12) | ||
952 | #define S3C2410_GPH6_TXD2 (0x02 << 12) | ||
953 | #define S3C2410_GPH6_nRTS1 (0x03 << 12) | ||
954 | |||
955 | #define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7) | ||
956 | #define S3C2410_GPH7_INP (0x00 << 14) | ||
957 | #define S3C2410_GPH7_OUTP (0x01 << 14) | ||
958 | #define S3C2410_GPH7_RXD2 (0x02 << 14) | ||
959 | #define S3C2410_GPH7_nCTS1 (0x03 << 14) | ||
960 | |||
961 | #define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8) | ||
962 | #define S3C2410_GPH8_INP (0x00 << 16) | ||
963 | #define S3C2410_GPH8_OUTP (0x01 << 16) | ||
964 | #define S3C2410_GPH8_UCLK (0x02 << 16) | ||
965 | |||
966 | #define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9) | ||
967 | #define S3C2410_GPH9_INP (0x00 << 18) | ||
968 | #define S3C2410_GPH9_OUTP (0x01 << 18) | ||
969 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) | ||
970 | #define S3C2442_GPH9_nSPICS0 (0x03 << 18) | ||
971 | |||
972 | #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) | ||
973 | #define S3C2410_GPH10_INP (0x00 << 20) | ||
974 | #define S3C2410_GPH10_OUTP (0x01 << 20) | ||
975 | #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) | ||
976 | |||
977 | /* The S3C2412 and S3C2413 move the GPJ register set to after | ||
978 | * GPH, which means all registers after 0x80 are now offset by 0x10 | ||
979 | * for the 2412/2413 from the 2410/2440/2442 | ||
980 | */ | ||
981 | |||
982 | /* miscellaneous control */ | ||
983 | #define S3C2400_MISCCR S3C2410_GPIOREG(0x54) | ||
984 | #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) | ||
985 | #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) | ||
986 | |||
987 | #define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84) | ||
988 | |||
989 | /* see clock.h for dclk definitions */ | ||
990 | |||
991 | /* pullup control on databus */ | ||
992 | #define S3C2410_MISCCR_SPUCR_HEN (0<<0) | ||
993 | #define S3C2410_MISCCR_SPUCR_HDIS (1<<0) | ||
994 | #define S3C2410_MISCCR_SPUCR_LEN (0<<1) | ||
995 | #define S3C2410_MISCCR_SPUCR_LDIS (1<<1) | ||
996 | |||
997 | #define S3C2400_MISCCR_SPUCR_LEN (0<<0) | ||
998 | #define S3C2400_MISCCR_SPUCR_LDIS (1<<0) | ||
999 | #define S3C2400_MISCCR_SPUCR_HEN (0<<1) | ||
1000 | #define S3C2400_MISCCR_SPUCR_HDIS (1<<1) | ||
1001 | |||
1002 | #define S3C2400_MISCCR_HZ_STOPEN (0<<2) | ||
1003 | #define S3C2400_MISCCR_HZ_STOPPREV (1<<2) | ||
1004 | |||
1005 | #define S3C2410_MISCCR_USBDEV (0<<3) | ||
1006 | #define S3C2410_MISCCR_USBHOST (1<<3) | ||
1007 | |||
1008 | #define S3C2410_MISCCR_CLK0_MPLL (0<<4) | ||
1009 | #define S3C2410_MISCCR_CLK0_UPLL (1<<4) | ||
1010 | #define S3C2410_MISCCR_CLK0_FCLK (2<<4) | ||
1011 | #define S3C2410_MISCCR_CLK0_HCLK (3<<4) | ||
1012 | #define S3C2410_MISCCR_CLK0_PCLK (4<<4) | ||
1013 | #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) | ||
1014 | #define S3C2410_MISCCR_CLK0_MASK (7<<4) | ||
1015 | |||
1016 | #define S3C2412_MISCCR_CLK0_RTC (2<<4) | ||
1017 | |||
1018 | #define S3C2410_MISCCR_CLK1_MPLL (0<<8) | ||
1019 | #define S3C2410_MISCCR_CLK1_UPLL (1<<8) | ||
1020 | #define S3C2410_MISCCR_CLK1_FCLK (2<<8) | ||
1021 | #define S3C2410_MISCCR_CLK1_HCLK (3<<8) | ||
1022 | #define S3C2410_MISCCR_CLK1_PCLK (4<<8) | ||
1023 | #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) | ||
1024 | #define S3C2410_MISCCR_CLK1_MASK (7<<8) | ||
1025 | |||
1026 | #define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) | ||
1027 | |||
1028 | #define S3C2410_MISCCR_USBSUSPND0 (1<<12) | ||
1029 | #define S3C2410_MISCCR_USBSUSPND1 (1<<13) | ||
1030 | |||
1031 | #define S3C2410_MISCCR_nRSTCON (1<<16) | ||
1032 | |||
1033 | #define S3C2410_MISCCR_nEN_SCLK0 (1<<17) | ||
1034 | #define S3C2410_MISCCR_nEN_SCLK1 (1<<18) | ||
1035 | #define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ | ||
1036 | #define S3C2410_MISCCR_SDSLEEP (7<<17) | ||
1037 | |||
1038 | /* external interrupt control... */ | ||
1039 | /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 | ||
1040 | * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 | ||
1041 | * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 | ||
1042 | * | ||
1043 | * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 | ||
1044 | * | ||
1045 | * Samsung datasheet p9-25 | ||
1046 | */ | ||
1047 | #define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58) | ||
1048 | #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) | ||
1049 | #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) | ||
1050 | #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) | ||
1051 | |||
1052 | #define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) | ||
1053 | #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) | ||
1054 | #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) | ||
1055 | |||
1056 | /* values for S3C2410_EXTINT0/1/2 */ | ||
1057 | #define S3C2410_EXTINT_LOWLEV (0x00) | ||
1058 | #define S3C2410_EXTINT_HILEV (0x01) | ||
1059 | #define S3C2410_EXTINT_FALLEDGE (0x02) | ||
1060 | #define S3C2410_EXTINT_RISEEDGE (0x04) | ||
1061 | #define S3C2410_EXTINT_BOTHEDGE (0x06) | ||
1062 | |||
1063 | /* interrupt filtering conrrol for EINT16..EINT23 */ | ||
1064 | #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) | ||
1065 | #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) | ||
1066 | #define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) | ||
1067 | #define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) | ||
1068 | |||
1069 | #define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) | ||
1070 | #define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) | ||
1071 | #define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) | ||
1072 | #define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) | ||
1073 | |||
1074 | /* values for interrupt filtering */ | ||
1075 | #define S3C2410_EINTFLT_PCLK (0x00) | ||
1076 | #define S3C2410_EINTFLT_EXTCLK (1<<7) | ||
1077 | #define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) | ||
1078 | |||
1079 | /* removed EINTxxxx defs from here, not meant for this */ | ||
1080 | |||
1081 | /* GSTATUS have miscellaneous information in them | ||
1082 | * | ||
1083 | * These move between s3c2410 and s3c2412 style systems. | ||
1084 | */ | ||
1085 | |||
1086 | #define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) | ||
1087 | #define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) | ||
1088 | #define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) | ||
1089 | #define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) | ||
1090 | #define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) | ||
1091 | |||
1092 | #define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) | ||
1093 | #define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) | ||
1094 | #define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) | ||
1095 | #define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) | ||
1096 | #define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) | ||
1097 | |||
1098 | #define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) | ||
1099 | #define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) | ||
1100 | #define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) | ||
1101 | #define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) | ||
1102 | #define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) | ||
1103 | |||
1104 | #define S3C2410_GSTATUS0_nWAIT (1<<3) | ||
1105 | #define S3C2410_GSTATUS0_NCON (1<<2) | ||
1106 | #define S3C2410_GSTATUS0_RnB (1<<1) | ||
1107 | #define S3C2410_GSTATUS0_nBATTFLT (1<<0) | ||
1108 | |||
1109 | #define S3C2410_GSTATUS1_IDMASK (0xffff0000) | ||
1110 | #define S3C2410_GSTATUS1_2410 (0x32410000) | ||
1111 | #define S3C2410_GSTATUS1_2412 (0x32412001) | ||
1112 | #define S3C2410_GSTATUS1_2440 (0x32440000) | ||
1113 | #define S3C2410_GSTATUS1_2442 (0x32440aaa) | ||
1114 | |||
1115 | #define S3C2410_GSTATUS2_WTRESET (1<<2) | ||
1116 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) | ||
1117 | #define S3C2410_GSTATUS2_PONRESET (1<<0) | ||
1118 | |||
1119 | /* open drain control register */ | ||
1120 | #define S3C2400_OPENCR S3C2410_GPIOREG(0x50) | ||
1121 | |||
1122 | #define S3C2400_OPENCR_OPC_RXD1DIS (0<<0) | ||
1123 | #define S3C2400_OPENCR_OPC_RXD1EN (1<<0) | ||
1124 | #define S3C2400_OPENCR_OPC_TXD1DIS (0<<1) | ||
1125 | #define S3C2400_OPENCR_OPC_TXD1EN (1<<1) | ||
1126 | #define S3C2400_OPENCR_OPC_CMDDIS (0<<2) | ||
1127 | #define S3C2400_OPENCR_OPC_CMDEN (1<<2) | ||
1128 | #define S3C2400_OPENCR_OPC_DATDIS (0<<3) | ||
1129 | #define S3C2400_OPENCR_OPC_DATEN (1<<3) | ||
1130 | #define S3C2400_OPENCR_OPC_MISODIS (0<<4) | ||
1131 | #define S3C2400_OPENCR_OPC_MISOEN (1<<4) | ||
1132 | #define S3C2400_OPENCR_OPC_MOSIDIS (0<<5) | ||
1133 | #define S3C2400_OPENCR_OPC_MOSIEN (1<<5) | ||
1134 | |||
1135 | /* 2412/2413 sleep configuration registers */ | ||
1136 | |||
1137 | #define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) | ||
1138 | #define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) | ||
1139 | #define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) | ||
1140 | #define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) | ||
1141 | #define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) | ||
1142 | #define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) | ||
1143 | |||
1144 | /* definitions for each pin bit */ | ||
1145 | #define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) | ||
1146 | #define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) | ||
1147 | #define S3C2412_GPIO_SLPCON_IN ( 0x02 ) | ||
1148 | #define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) | ||
1149 | |||
1150 | #define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) | ||
1151 | #define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) | ||
1152 | #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) | ||
1153 | #define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) | ||
1154 | #define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ | ||
1155 | #define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) | ||
1156 | |||
1157 | #define S3C2412_SLPCON_ALL_LOW (0x0) | ||
1158 | #define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) | ||
1159 | #define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) | ||
1160 | #define S3C2412_SLPCON_ALL_PULL (0x33333333) | ||
1161 | |||
1162 | #endif /* __ASM_ARCH_REGS_GPIO_H */ | ||
1163 | |||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h new file mode 100644 index 000000000000..1202ca5e99f6 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h | |||
@@ -0,0 +1,106 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-gpioj.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2440 GPIO J register definitions | ||
11 | */ | ||
12 | |||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_GPIOJ_H | ||
15 | #define __ASM_ARCH_REGS_GPIOJ_H "gpioj" | ||
16 | |||
17 | /* Port J consists of 13 GPIO/Camera pins | ||
18 | * | ||
19 | * GPJCON has 2 bits for each of the input pins on port F | ||
20 | * 00 = 0 input, 1 output, 2 Camera | ||
21 | * | ||
22 | * pull up works like all other ports. | ||
23 | */ | ||
24 | |||
25 | #define S3C2440_GPIO_BANKJ (416) | ||
26 | |||
27 | #define S3C2440_GPJCON S3C2410_GPIOREG(0xd0) | ||
28 | #define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4) | ||
29 | #define S3C2440_GPJUP S3C2410_GPIOREG(0xd8) | ||
30 | |||
31 | #define S3C2413_GPJCON S3C2410_GPIOREG(0x80) | ||
32 | #define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) | ||
33 | #define S3C2413_GPJUP S3C2410_GPIOREG(0x88) | ||
34 | #define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) | ||
35 | |||
36 | #define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0) | ||
37 | #define S3C2440_GPJ0_INP (0x00 << 0) | ||
38 | #define S3C2440_GPJ0_OUTP (0x01 << 0) | ||
39 | #define S3C2440_GPJ0_CAMDATA0 (0x02 << 0) | ||
40 | |||
41 | #define S3C2440_GPJ1 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1) | ||
42 | #define S3C2440_GPJ1_INP (0x00 << 2) | ||
43 | #define S3C2440_GPJ1_OUTP (0x01 << 2) | ||
44 | #define S3C2440_GPJ1_CAMDATA1 (0x02 << 2) | ||
45 | |||
46 | #define S3C2440_GPJ2 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2) | ||
47 | #define S3C2440_GPJ2_INP (0x00 << 4) | ||
48 | #define S3C2440_GPJ2_OUTP (0x01 << 4) | ||
49 | #define S3C2440_GPJ2_CAMDATA2 (0x02 << 4) | ||
50 | |||
51 | #define S3C2440_GPJ3 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3) | ||
52 | #define S3C2440_GPJ3_INP (0x00 << 6) | ||
53 | #define S3C2440_GPJ3_OUTP (0x01 << 6) | ||
54 | #define S3C2440_GPJ3_CAMDATA3 (0x02 << 6) | ||
55 | |||
56 | #define S3C2440_GPJ4 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4) | ||
57 | #define S3C2440_GPJ4_INP (0x00 << 8) | ||
58 | #define S3C2440_GPJ4_OUTP (0x01 << 8) | ||
59 | #define S3C2440_GPJ4_CAMDATA4 (0x02 << 8) | ||
60 | |||
61 | #define S3C2440_GPJ5 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5) | ||
62 | #define S3C2440_GPJ5_INP (0x00 << 10) | ||
63 | #define S3C2440_GPJ5_OUTP (0x01 << 10) | ||
64 | #define S3C2440_GPJ5_CAMDATA5 (0x02 << 10) | ||
65 | |||
66 | #define S3C2440_GPJ6 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6) | ||
67 | #define S3C2440_GPJ6_INP (0x00 << 12) | ||
68 | #define S3C2440_GPJ6_OUTP (0x01 << 12) | ||
69 | #define S3C2440_GPJ6_CAMDATA6 (0x02 << 12) | ||
70 | |||
71 | #define S3C2440_GPJ7 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7) | ||
72 | #define S3C2440_GPJ7_INP (0x00 << 14) | ||
73 | #define S3C2440_GPJ7_OUTP (0x01 << 14) | ||
74 | #define S3C2440_GPJ7_CAMDATA7 (0x02 << 14) | ||
75 | |||
76 | #define S3C2440_GPJ8 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8) | ||
77 | #define S3C2440_GPJ8_INP (0x00 << 16) | ||
78 | #define S3C2440_GPJ8_OUTP (0x01 << 16) | ||
79 | #define S3C2440_GPJ8_CAMPCLK (0x02 << 16) | ||
80 | |||
81 | #define S3C2440_GPJ9 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9) | ||
82 | #define S3C2440_GPJ9_INP (0x00 << 18) | ||
83 | #define S3C2440_GPJ9_OUTP (0x01 << 18) | ||
84 | #define S3C2440_GPJ9_CAMVSYNC (0x02 << 18) | ||
85 | |||
86 | #define S3C2440_GPJ10 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10) | ||
87 | #define S3C2440_GPJ10_INP (0x00 << 20) | ||
88 | #define S3C2440_GPJ10_OUTP (0x01 << 20) | ||
89 | #define S3C2440_GPJ10_CAMHREF (0x02 << 20) | ||
90 | |||
91 | #define S3C2440_GPJ11 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11) | ||
92 | #define S3C2440_GPJ11_INP (0x00 << 22) | ||
93 | #define S3C2440_GPJ11_OUTP (0x01 << 22) | ||
94 | #define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22) | ||
95 | |||
96 | #define S3C2440_GPJ12 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12) | ||
97 | #define S3C2440_GPJ12_INP (0x00 << 24) | ||
98 | #define S3C2440_GPJ12_OUTP (0x01 << 24) | ||
99 | #define S3C2440_GPJ12_CAMRESET (0x02 << 24) | ||
100 | |||
101 | #define S3C2443_GPJ13 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13) | ||
102 | #define S3C2443_GPJ14 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14) | ||
103 | #define S3C2443_GPJ15 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15) | ||
104 | |||
105 | #endif /* __ASM_ARCH_REGS_GPIOJ_H */ | ||
106 | |||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h new file mode 100644 index 000000000000..b057c06d167a --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-irq.h | |||
@@ -0,0 +1,43 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-irq.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | |||
12 | #ifndef ___ASM_ARCH_REGS_IRQ_H | ||
13 | #define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $" | ||
14 | |||
15 | /* interrupt controller */ | ||
16 | |||
17 | #define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ) | ||
18 | #define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO) | ||
19 | #define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2) | ||
20 | |||
21 | #define S3C2410_SRCPND S3C2410_IRQREG(0x000) | ||
22 | #define S3C2410_INTMOD S3C2410_IRQREG(0x004) | ||
23 | #define S3C2410_INTMSK S3C2410_IRQREG(0x008) | ||
24 | #define S3C2410_PRIORITY S3C2410_IRQREG(0x00C) | ||
25 | #define S3C2410_INTPND S3C2410_IRQREG(0x010) | ||
26 | #define S3C2410_INTOFFSET S3C2410_IRQREG(0x014) | ||
27 | #define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018) | ||
28 | #define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C) | ||
29 | |||
30 | /* mask: 0=enable, 1=disable | ||
31 | * 1 bit EINT, 4=EINT4, 23=EINT23 | ||
32 | * EINT0,1,2,3 are not handled here. | ||
33 | */ | ||
34 | |||
35 | #define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4) | ||
36 | #define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8) | ||
37 | #define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4) | ||
38 | #define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8) | ||
39 | |||
40 | #define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4) | ||
41 | #define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8) | ||
42 | |||
43 | #endif /* ___ASM_ARCH_REGS_IRQ_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h b/arch/arm/mach-s3c2410/include/mach/regs-lcd.h new file mode 100644 index 000000000000..893b8742f954 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-lcd.h | |||
@@ -0,0 +1,162 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-lcd.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | |||
12 | #ifndef ___ASM_ARCH_REGS_LCD_H | ||
13 | #define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $" | ||
14 | |||
15 | #define S3C2410_LCDREG(x) (x) | ||
16 | |||
17 | /* LCD control registers */ | ||
18 | #define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) | ||
19 | #define S3C2410_LCDCON2 S3C2410_LCDREG(0x04) | ||
20 | #define S3C2410_LCDCON3 S3C2410_LCDREG(0x08) | ||
21 | #define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C) | ||
22 | #define S3C2410_LCDCON5 S3C2410_LCDREG(0x10) | ||
23 | |||
24 | #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) | ||
25 | #define S3C2410_LCDCON1_MMODE (1<<7) | ||
26 | #define S3C2410_LCDCON1_DSCAN4 (0<<5) | ||
27 | #define S3C2410_LCDCON1_STN4 (1<<5) | ||
28 | #define S3C2410_LCDCON1_STN8 (2<<5) | ||
29 | #define S3C2410_LCDCON1_TFT (3<<5) | ||
30 | |||
31 | #define S3C2410_LCDCON1_STN1BPP (0<<1) | ||
32 | #define S3C2410_LCDCON1_STN2GREY (1<<1) | ||
33 | #define S3C2410_LCDCON1_STN4GREY (2<<1) | ||
34 | #define S3C2410_LCDCON1_STN8BPP (3<<1) | ||
35 | #define S3C2410_LCDCON1_STN12BPP (4<<1) | ||
36 | |||
37 | #define S3C2410_LCDCON1_TFT1BPP (8<<1) | ||
38 | #define S3C2410_LCDCON1_TFT2BPP (9<<1) | ||
39 | #define S3C2410_LCDCON1_TFT4BPP (10<<1) | ||
40 | #define S3C2410_LCDCON1_TFT8BPP (11<<1) | ||
41 | #define S3C2410_LCDCON1_TFT16BPP (12<<1) | ||
42 | #define S3C2410_LCDCON1_TFT24BPP (13<<1) | ||
43 | |||
44 | #define S3C2410_LCDCON1_ENVID (1) | ||
45 | |||
46 | #define S3C2410_LCDCON1_MODEMASK 0x1E | ||
47 | |||
48 | #define S3C2410_LCDCON2_VBPD(x) ((x) << 24) | ||
49 | #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) | ||
50 | #define S3C2410_LCDCON2_VFPD(x) ((x) << 6) | ||
51 | #define S3C2410_LCDCON2_VSPW(x) ((x) << 0) | ||
52 | |||
53 | #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) | ||
54 | #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) | ||
55 | #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) | ||
56 | |||
57 | #define S3C2410_LCDCON3_HBPD(x) ((x) << 19) | ||
58 | #define S3C2410_LCDCON3_WDLY(x) ((x) << 19) | ||
59 | #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) | ||
60 | #define S3C2410_LCDCON3_HFPD(x) ((x) << 0) | ||
61 | #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) | ||
62 | |||
63 | #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) | ||
64 | #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) | ||
65 | |||
66 | /* LDCCON4 changes for STN mode on the S3C2412 */ | ||
67 | |||
68 | #define S3C2410_LCDCON4_MVAL(x) ((x) << 8) | ||
69 | #define S3C2410_LCDCON4_HSPW(x) ((x) << 0) | ||
70 | #define S3C2410_LCDCON4_WLH(x) ((x) << 0) | ||
71 | |||
72 | #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) | ||
73 | |||
74 | #define S3C2410_LCDCON5_BPP24BL (1<<12) | ||
75 | #define S3C2410_LCDCON5_FRM565 (1<<11) | ||
76 | #define S3C2410_LCDCON5_INVVCLK (1<<10) | ||
77 | #define S3C2410_LCDCON5_INVVLINE (1<<9) | ||
78 | #define S3C2410_LCDCON5_INVVFRAME (1<<8) | ||
79 | #define S3C2410_LCDCON5_INVVD (1<<7) | ||
80 | #define S3C2410_LCDCON5_INVVDEN (1<<6) | ||
81 | #define S3C2410_LCDCON5_INVPWREN (1<<5) | ||
82 | #define S3C2410_LCDCON5_INVLEND (1<<4) | ||
83 | #define S3C2410_LCDCON5_PWREN (1<<3) | ||
84 | #define S3C2410_LCDCON5_ENLEND (1<<2) | ||
85 | #define S3C2410_LCDCON5_BSWP (1<<1) | ||
86 | #define S3C2410_LCDCON5_HWSWP (1<<0) | ||
87 | |||
88 | /* framebuffer start addressed */ | ||
89 | #define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14) | ||
90 | #define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18) | ||
91 | #define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C) | ||
92 | |||
93 | #define S3C2410_LCDBANK(x) ((x) << 21) | ||
94 | #define S3C2410_LCDBASEU(x) (x) | ||
95 | |||
96 | #define S3C2410_OFFSIZE(x) ((x) << 11) | ||
97 | #define S3C2410_PAGEWIDTH(x) (x) | ||
98 | |||
99 | /* colour lookup and miscellaneous controls */ | ||
100 | |||
101 | #define S3C2410_REDLUT S3C2410_LCDREG(0x20) | ||
102 | #define S3C2410_GREENLUT S3C2410_LCDREG(0x24) | ||
103 | #define S3C2410_BLUELUT S3C2410_LCDREG(0x28) | ||
104 | |||
105 | #define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) | ||
106 | #define S3C2410_TPAL S3C2410_LCDREG(0x50) | ||
107 | |||
108 | #define S3C2410_TPAL_EN (1<<24) | ||
109 | |||
110 | /* interrupt info */ | ||
111 | #define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) | ||
112 | #define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) | ||
113 | #define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) | ||
114 | #define S3C2410_LCDINT_FIWSEL (1<<2) | ||
115 | #define S3C2410_LCDINT_FRSYNC (1<<1) | ||
116 | #define S3C2410_LCDINT_FICNT (1<<0) | ||
117 | |||
118 | /* s3c2442 extra stn registers */ | ||
119 | |||
120 | #define S3C2442_REDLUT S3C2410_LCDREG(0x20) | ||
121 | #define S3C2442_GREENLUT S3C2410_LCDREG(0x24) | ||
122 | #define S3C2442_BLUELUT S3C2410_LCDREG(0x28) | ||
123 | #define S3C2442_DITHMODE S3C2410_LCDREG(0x20) | ||
124 | |||
125 | #define S3C2410_LPCSEL S3C2410_LCDREG(0x60) | ||
126 | |||
127 | #define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) | ||
128 | |||
129 | /* S3C2412 registers */ | ||
130 | |||
131 | #define S3C2412_TPAL S3C2410_LCDREG(0x20) | ||
132 | |||
133 | #define S3C2412_LCDINTPND S3C2410_LCDREG(0x24) | ||
134 | #define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28) | ||
135 | #define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C) | ||
136 | |||
137 | #define S3C2412_TCONSEL S3C2410_LCDREG(0x30) | ||
138 | |||
139 | #define S3C2412_LCDCON6 S3C2410_LCDREG(0x34) | ||
140 | #define S3C2412_LCDCON7 S3C2410_LCDREG(0x38) | ||
141 | #define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C) | ||
142 | #define S3C2412_LCDCON9 S3C2410_LCDREG(0x40) | ||
143 | |||
144 | #define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4)) | ||
145 | #define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4)) | ||
146 | #define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4)) | ||
147 | |||
148 | #define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4)) | ||
149 | |||
150 | /* general registers */ | ||
151 | |||
152 | /* base of the LCD registers, where INTPND, INTSRC and then INTMSK | ||
153 | * are available. */ | ||
154 | |||
155 | #define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54) | ||
156 | #define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24) | ||
157 | |||
158 | #define S3C24XX_LCDINTPND (0x00) | ||
159 | #define S3C24XX_LCDSRCPND (0x04) | ||
160 | #define S3C24XX_LCDINTMSK (0x08) | ||
161 | |||
162 | #endif /* ___ASM_ARCH_REGS_LCD_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h new file mode 100644 index 000000000000..f9926abd5cde --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h | |||
@@ -0,0 +1,220 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-mem.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 Memory Control register definitions | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARM_MEMREGS_H | ||
14 | #define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $" | ||
15 | |||
16 | #ifndef S3C2410_MEMREG | ||
17 | #define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) | ||
18 | #endif | ||
19 | |||
20 | /* bus width, and wait state control */ | ||
21 | #define S3C2410_BWSCON S3C2410_MEMREG(0x0000) | ||
22 | |||
23 | /* bank zero config - note, pinstrapped from OM pins! */ | ||
24 | #define S3C2410_BWSCON_DW0_16 (1<<1) | ||
25 | #define S3C2410_BWSCON_DW0_32 (2<<1) | ||
26 | |||
27 | /* bank one configs */ | ||
28 | #define S3C2410_BWSCON_DW1_8 (0<<4) | ||
29 | #define S3C2410_BWSCON_DW1_16 (1<<4) | ||
30 | #define S3C2410_BWSCON_DW1_32 (2<<4) | ||
31 | #define S3C2410_BWSCON_WS1 (1<<6) | ||
32 | #define S3C2410_BWSCON_ST1 (1<<7) | ||
33 | |||
34 | /* bank 2 configurations */ | ||
35 | #define S3C2410_BWSCON_DW2_8 (0<<8) | ||
36 | #define S3C2410_BWSCON_DW2_16 (1<<8) | ||
37 | #define S3C2410_BWSCON_DW2_32 (2<<8) | ||
38 | #define S3C2410_BWSCON_WS2 (1<<10) | ||
39 | #define S3C2410_BWSCON_ST2 (1<<11) | ||
40 | |||
41 | /* bank 3 configurations */ | ||
42 | #define S3C2410_BWSCON_DW3_8 (0<<12) | ||
43 | #define S3C2410_BWSCON_DW3_16 (1<<12) | ||
44 | #define S3C2410_BWSCON_DW3_32 (2<<12) | ||
45 | #define S3C2410_BWSCON_WS3 (1<<14) | ||
46 | #define S3C2410_BWSCON_ST3 (1<<15) | ||
47 | |||
48 | /* bank 4 configurations */ | ||
49 | #define S3C2410_BWSCON_DW4_8 (0<<16) | ||
50 | #define S3C2410_BWSCON_DW4_16 (1<<16) | ||
51 | #define S3C2410_BWSCON_DW4_32 (2<<16) | ||
52 | #define S3C2410_BWSCON_WS4 (1<<18) | ||
53 | #define S3C2410_BWSCON_ST4 (1<<19) | ||
54 | |||
55 | /* bank 5 configurations */ | ||
56 | #define S3C2410_BWSCON_DW5_8 (0<<20) | ||
57 | #define S3C2410_BWSCON_DW5_16 (1<<20) | ||
58 | #define S3C2410_BWSCON_DW5_32 (2<<20) | ||
59 | #define S3C2410_BWSCON_WS5 (1<<22) | ||
60 | #define S3C2410_BWSCON_ST5 (1<<23) | ||
61 | |||
62 | /* bank 6 configurations */ | ||
63 | #define S3C2410_BWSCON_DW6_8 (0<<24) | ||
64 | #define S3C2410_BWSCON_DW6_16 (1<<24) | ||
65 | #define S3C2410_BWSCON_DW6_32 (2<<24) | ||
66 | #define S3C2410_BWSCON_WS6 (1<<26) | ||
67 | #define S3C2410_BWSCON_ST6 (1<<27) | ||
68 | |||
69 | /* bank 7 configurations */ | ||
70 | #define S3C2410_BWSCON_DW7_8 (0<<28) | ||
71 | #define S3C2410_BWSCON_DW7_16 (1<<28) | ||
72 | #define S3C2410_BWSCON_DW7_32 (2<<28) | ||
73 | #define S3C2410_BWSCON_WS7 (1<<30) | ||
74 | #define S3C2410_BWSCON_ST7 (1<<31) | ||
75 | |||
76 | /* memory set (rom, ram) */ | ||
77 | #define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004) | ||
78 | #define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008) | ||
79 | #define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C) | ||
80 | #define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010) | ||
81 | #define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014) | ||
82 | #define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018) | ||
83 | #define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C) | ||
84 | #define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020) | ||
85 | |||
86 | /* bank configuration registers */ | ||
87 | |||
88 | #define S3C2410_BANKCON_PMCnorm (0x00) | ||
89 | #define S3C2410_BANKCON_PMC4 (0x01) | ||
90 | #define S3C2410_BANKCON_PMC8 (0x02) | ||
91 | #define S3C2410_BANKCON_PMC16 (0x03) | ||
92 | |||
93 | /* bank configurations for banks 0..7, note banks | ||
94 | * 6 and 7 have differnt configurations depending on | ||
95 | * the memory type bits */ | ||
96 | |||
97 | #define S3C2410_BANKCON_Tacp2 (0x0 << 2) | ||
98 | #define S3C2410_BANKCON_Tacp3 (0x1 << 2) | ||
99 | #define S3C2410_BANKCON_Tacp4 (0x2 << 2) | ||
100 | #define S3C2410_BANKCON_Tacp6 (0x3 << 2) | ||
101 | #define S3C2410_BANKCON_Tacp_SHIFT (2) | ||
102 | |||
103 | #define S3C2410_BANKCON_Tcah0 (0x0 << 4) | ||
104 | #define S3C2410_BANKCON_Tcah1 (0x1 << 4) | ||
105 | #define S3C2410_BANKCON_Tcah2 (0x2 << 4) | ||
106 | #define S3C2410_BANKCON_Tcah4 (0x3 << 4) | ||
107 | #define S3C2410_BANKCON_Tcah_SHIFT (4) | ||
108 | |||
109 | #define S3C2410_BANKCON_Tcoh0 (0x0 << 6) | ||
110 | #define S3C2410_BANKCON_Tcoh1 (0x1 << 6) | ||
111 | #define S3C2410_BANKCON_Tcoh2 (0x2 << 6) | ||
112 | #define S3C2410_BANKCON_Tcoh4 (0x3 << 6) | ||
113 | #define S3C2410_BANKCON_Tcoh_SHIFT (6) | ||
114 | |||
115 | #define S3C2410_BANKCON_Tacc1 (0x0 << 8) | ||
116 | #define S3C2410_BANKCON_Tacc2 (0x1 << 8) | ||
117 | #define S3C2410_BANKCON_Tacc3 (0x2 << 8) | ||
118 | #define S3C2410_BANKCON_Tacc4 (0x3 << 8) | ||
119 | #define S3C2410_BANKCON_Tacc6 (0x4 << 8) | ||
120 | #define S3C2410_BANKCON_Tacc8 (0x5 << 8) | ||
121 | #define S3C2410_BANKCON_Tacc10 (0x6 << 8) | ||
122 | #define S3C2410_BANKCON_Tacc14 (0x7 << 8) | ||
123 | #define S3C2410_BANKCON_Tacc_SHIFT (8) | ||
124 | |||
125 | #define S3C2410_BANKCON_Tcos0 (0x0 << 11) | ||
126 | #define S3C2410_BANKCON_Tcos1 (0x1 << 11) | ||
127 | #define S3C2410_BANKCON_Tcos2 (0x2 << 11) | ||
128 | #define S3C2410_BANKCON_Tcos4 (0x3 << 11) | ||
129 | #define S3C2410_BANKCON_Tcos_SHIFT (11) | ||
130 | |||
131 | #define S3C2410_BANKCON_Tacs0 (0x0 << 13) | ||
132 | #define S3C2410_BANKCON_Tacs1 (0x1 << 13) | ||
133 | #define S3C2410_BANKCON_Tacs2 (0x2 << 13) | ||
134 | #define S3C2410_BANKCON_Tacs4 (0x3 << 13) | ||
135 | #define S3C2410_BANKCON_Tacs_SHIFT (13) | ||
136 | |||
137 | #define S3C2410_BANKCON_SRAM (0x0 << 15) | ||
138 | #define S3C2400_BANKCON_EDODRAM (0x2 << 15) | ||
139 | #define S3C2410_BANKCON_SDRAM (0x3 << 15) | ||
140 | |||
141 | /* next bits only for EDO DRAM in 6,7 */ | ||
142 | #define S3C2400_BANKCON_EDO_Trcd1 (0x00 << 4) | ||
143 | #define S3C2400_BANKCON_EDO_Trcd2 (0x01 << 4) | ||
144 | #define S3C2400_BANKCON_EDO_Trcd3 (0x02 << 4) | ||
145 | #define S3C2400_BANKCON_EDO_Trcd4 (0x03 << 4) | ||
146 | |||
147 | /* CAS pulse width */ | ||
148 | #define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3) | ||
149 | #define S3C2400_BANKCON_EDO_PULSE2 (0x01 << 3) | ||
150 | |||
151 | /* CAS pre-charge */ | ||
152 | #define S3C2400_BANKCON_EDO_TCP1 (0x00 << 2) | ||
153 | #define S3C2400_BANKCON_EDO_TCP2 (0x01 << 2) | ||
154 | |||
155 | /* control column address select */ | ||
156 | #define S3C2400_BANKCON_EDO_SCANb8 (0x00 << 0) | ||
157 | #define S3C2400_BANKCON_EDO_SCANb9 (0x01 << 0) | ||
158 | #define S3C2400_BANKCON_EDO_SCANb10 (0x02 << 0) | ||
159 | #define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0) | ||
160 | |||
161 | /* next bits only for SDRAM in 6,7 */ | ||
162 | #define S3C2410_BANKCON_Trcd2 (0x00 << 2) | ||
163 | #define S3C2410_BANKCON_Trcd3 (0x01 << 2) | ||
164 | #define S3C2410_BANKCON_Trcd4 (0x02 << 2) | ||
165 | |||
166 | /* control column address select */ | ||
167 | #define S3C2410_BANKCON_SCANb8 (0x00 << 0) | ||
168 | #define S3C2410_BANKCON_SCANb9 (0x01 << 0) | ||
169 | #define S3C2410_BANKCON_SCANb10 (0x02 << 0) | ||
170 | |||
171 | #define S3C2410_REFRESH S3C2410_MEMREG(0x0024) | ||
172 | #define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028) | ||
173 | #define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C) | ||
174 | #define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030) | ||
175 | |||
176 | /* refresh control */ | ||
177 | |||
178 | #define S3C2410_REFRESH_REFEN (1<<23) | ||
179 | #define S3C2410_REFRESH_SELF (1<<22) | ||
180 | #define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1) | ||
181 | |||
182 | #define S3C2410_REFRESH_TRP_MASK (3<<20) | ||
183 | #define S3C2410_REFRESH_TRP_2clk (0<<20) | ||
184 | #define S3C2410_REFRESH_TRP_3clk (1<<20) | ||
185 | #define S3C2410_REFRESH_TRP_4clk (2<<20) | ||
186 | |||
187 | #define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20) | ||
188 | #define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20) | ||
189 | #define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20) | ||
190 | #define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20) | ||
191 | #define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20) | ||
192 | |||
193 | #define S3C2410_REFRESH_TSRC_MASK (3<<18) | ||
194 | #define S3C2410_REFRESH_TSRC_4clk (0<<18) | ||
195 | #define S3C2410_REFRESH_TSRC_5clk (1<<18) | ||
196 | #define S3C2410_REFRESH_TSRC_6clk (2<<18) | ||
197 | #define S3C2410_REFRESH_TSRC_7clk (3<<18) | ||
198 | |||
199 | |||
200 | /* mode select register(s) */ | ||
201 | |||
202 | #define S3C2410_MRSRB_CL1 (0x00 << 4) | ||
203 | #define S3C2410_MRSRB_CL2 (0x02 << 4) | ||
204 | #define S3C2410_MRSRB_CL3 (0x03 << 4) | ||
205 | |||
206 | /* bank size register */ | ||
207 | #define S3C2410_BANKSIZE_128M (0x2 << 0) | ||
208 | #define S3C2410_BANKSIZE_64M (0x1 << 0) | ||
209 | #define S3C2410_BANKSIZE_32M (0x0 << 0) | ||
210 | #define S3C2410_BANKSIZE_16M (0x7 << 0) | ||
211 | #define S3C2410_BANKSIZE_8M (0x6 << 0) | ||
212 | #define S3C2410_BANKSIZE_4M (0x5 << 0) | ||
213 | #define S3C2410_BANKSIZE_2M (0x4 << 0) | ||
214 | #define S3C2410_BANKSIZE_MASK (0x7 << 0) | ||
215 | #define S3C2400_BANKSIZE_MASK (0x4 << 0) | ||
216 | #define S3C2410_BANKSIZE_SCLK_EN (1<<4) | ||
217 | #define S3C2410_BANKSIZE_SCKE_EN (1<<5) | ||
218 | #define S3C2410_BANKSIZE_BURST (1<<7) | ||
219 | |||
220 | #endif /* __ASM_ARM_MEMREGS_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c2410/include/mach/regs-power.h new file mode 100644 index 000000000000..2d36353f57d7 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-power.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-power.h | ||
2 | * | ||
3 | * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C24XX power control register definitions | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARM_REGS_PWR | ||
14 | #define __ASM_ARM_REGS_PWR __FILE__ | ||
15 | |||
16 | #define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR) | ||
17 | |||
18 | #define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) | ||
19 | #define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) | ||
20 | |||
21 | #define S3C2412_INFORM0 S3C24XX_PWRREG(0x70) | ||
22 | #define S3C2412_INFORM1 S3C24XX_PWRREG(0x74) | ||
23 | #define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) | ||
24 | #define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) | ||
25 | |||
26 | #define S3C2412_PWRCFG_BATF_IRQ (1<<0) | ||
27 | #define S3C2412_PWRCFG_BATF_IGNORE (2<<0) | ||
28 | #define S3C2412_PWRCFG_BATF_SLEEP (3<<0) | ||
29 | #define S3C2412_PWRCFG_BATF_MASK (3<<0) | ||
30 | |||
31 | #define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6) | ||
32 | #define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6) | ||
33 | #define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6) | ||
34 | #define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6) | ||
35 | #define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6) | ||
36 | |||
37 | #define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8) | ||
38 | #define S3C2412_PWRCFG_NAND_NORST (1<<9) | ||
39 | |||
40 | #endif /* __ASM_ARM_REGS_PWR */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h new file mode 100644 index 000000000000..a4bf27123170 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * S3C2412 memory register definitions | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARM_REGS_S3C2412_MEM | ||
15 | #define __ASM_ARM_REGS_S3C2412_MEM | ||
16 | |||
17 | #ifndef S3C2412_MEMREG | ||
18 | #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) | ||
19 | #endif | ||
20 | |||
21 | #define S3C2412_BANKCFG S3C2412_MEMREG(0x00) | ||
22 | #define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) | ||
23 | #define S3C2412_BANKCON2 S3C2412_MEMREG(0x08) | ||
24 | #define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C) | ||
25 | |||
26 | #define S3C2412_REFRESH S3C2412_MEMREG(0x10) | ||
27 | #define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) | ||
28 | |||
29 | #endif /* __ASM_ARM_REGS_S3C2412_MEM */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h new file mode 100644 index 000000000000..aa69dc79bc38 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h | |||
@@ -0,0 +1,23 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h | ||
2 | * | ||
3 | * Copyright 2007 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * S3C2412 specific register definitions | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_S3C2412_H | ||
15 | #define __ASM_ARCH_REGS_S3C2412_H "s3c2412" | ||
16 | |||
17 | #define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) | ||
18 | #define S3C2412_SWRST_RESET (0x533C2412) | ||
19 | |||
20 | /* see regs-power.h for the other registers in the power block. */ | ||
21 | |||
22 | #endif /* __ASM_ARCH_REGS_S3C2412_H */ | ||
23 | |||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h new file mode 100644 index 000000000000..7dd458363a51 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h | |||
@@ -0,0 +1,195 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h | ||
2 | * | ||
3 | * Copyright (c) 2007 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * S3C2443 clock register definitions | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARM_REGS_S3C2443_CLOCK | ||
15 | #define __ASM_ARM_REGS_S3C2443_CLOCK | ||
16 | |||
17 | #define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) | ||
18 | |||
19 | #define S3C2443_PLLCON_MDIVSHIFT 16 | ||
20 | #define S3C2443_PLLCON_PDIVSHIFT 8 | ||
21 | #define S3C2443_PLLCON_SDIVSHIFT 0 | ||
22 | #define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1) | ||
23 | #define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1) | ||
24 | #define S3C2443_PLLCON_SDIVMASK (3) | ||
25 | |||
26 | #define S3C2443_MPLLCON S3C2443_CLKREG(0x10) | ||
27 | #define S3C2443_EPLLCON S3C2443_CLKREG(0x18) | ||
28 | #define S3C2443_CLKSRC S3C2443_CLKREG(0x20) | ||
29 | #define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24) | ||
30 | #define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28) | ||
31 | #define S3C2443_HCLKCON S3C2443_CLKREG(0x30) | ||
32 | #define S3C2443_PCLKCON S3C2443_CLKREG(0x34) | ||
33 | #define S3C2443_SCLKCON S3C2443_CLKREG(0x38) | ||
34 | #define S3C2443_PWRMODE S3C2443_CLKREG(0x40) | ||
35 | #define S3C2443_SWRST S3C2443_CLKREG(0x44) | ||
36 | #define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50) | ||
37 | #define S3C2443_SYSID S3C2443_CLKREG(0x5C) | ||
38 | #define S3C2443_PWRCFG S3C2443_CLKREG(0x60) | ||
39 | #define S3C2443_RSTCON S3C2443_CLKREG(0x64) | ||
40 | |||
41 | #define S3C2443_SWRST_RESET (0x533c2443) | ||
42 | |||
43 | #define S3C2443_PLLCON_OFF (1<<24) | ||
44 | |||
45 | #define S3C2443_CLKSRC_I2S_EXT (1<<14) | ||
46 | #define S3C2443_CLKSRC_I2S_EPLLDIV (0<<14) | ||
47 | #define S3C2443_CLKSRC_I2S_EPLLREF (2<<14) | ||
48 | #define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14) | ||
49 | #define S3C2443_CLKSRC_I2S_MASK (3<<14) | ||
50 | |||
51 | #define S3C2443_CLKSRC_EPLLREF_XTAL (2<<8) | ||
52 | #define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<8) | ||
53 | #define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<8) | ||
54 | #define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<8) | ||
55 | #define S3C2443_CLKSRC_EPLLREF_MASK (3<<8) | ||
56 | |||
57 | #define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6) | ||
58 | #define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4) | ||
59 | #define S3C2443_CLKSRC_EXTCLK_DIV (1<<3) | ||
60 | |||
61 | #define S3C2443_CLKDIV0_DVS (1<<13) | ||
62 | #define S3C2443_CLKDIV0_HALF_HCLK (1<<3) | ||
63 | #define S3C2443_CLKDIV0_HALF_PCLK (1<<2) | ||
64 | |||
65 | #define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0) | ||
66 | |||
67 | #define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6) | ||
68 | #define S3C2443_CLKDIV0_EXTDIV_SHIFT (6) | ||
69 | |||
70 | #define S3C2443_CLKDIV0_PREDIV_MASK (3<<4) | ||
71 | #define S3C2443_CLKDIV0_PREDIV_SHIFT (4) | ||
72 | |||
73 | #define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9) | ||
74 | #define S3C2443_CLKDIV0_ARMDIV_SHIFT (9) | ||
75 | #define S3C2443_CLKDIV0_ARMDIV_1 (0<<9) | ||
76 | #define S3C2443_CLKDIV0_ARMDIV_2 (8<<9) | ||
77 | #define S3C2443_CLKDIV0_ARMDIV_3 (2<<9) | ||
78 | #define S3C2443_CLKDIV0_ARMDIV_4 (9<<9) | ||
79 | #define S3C2443_CLKDIV0_ARMDIV_6 (10<<9) | ||
80 | #define S3C2443_CLKDIV0_ARMDIV_8 (11<<9) | ||
81 | #define S3C2443_CLKDIV0_ARMDIV_12 (13<<9) | ||
82 | #define S3C2443_CLKDIV0_ARMDIV_16 (15<<9) | ||
83 | |||
84 | /* S3C2443_CLKDIV1 */ | ||
85 | |||
86 | #define S3C2443_CLKDIV1_CAMDIV_MASK (15<<26) | ||
87 | #define S3C2443_CLKDIV1_CAMDIV_SHIFT (26) | ||
88 | |||
89 | #define S3C2443_CLKDIV1_HSSPIDIV_MASK (3<<24) | ||
90 | #define S3C2443_CLKDIV1_HSSPIDIV_SHIFT (24) | ||
91 | |||
92 | #define S3C2443_CLKDIV1_DISPDIV_MASK (0xff<<16) | ||
93 | #define S3C2443_CLKDIV1_DISPDIV_SHIFT (16) | ||
94 | |||
95 | #define S3C2443_CLKDIV1_I2SDIV_MASK (15<<12) | ||
96 | #define S3C2443_CLKDIV1_I2SDIV_SHIFT (12) | ||
97 | |||
98 | #define S3C2443_CLKDIV1_UARTDIV_MASK (15<<8) | ||
99 | #define S3C2443_CLKDIV1_UARTDIV_SHIFT (8) | ||
100 | |||
101 | #define S3C2443_CLKDIV1_HSMMCDIV_MASK (3<<6) | ||
102 | #define S3C2443_CLKDIV1_HSMMCDIV_SHIFT (6) | ||
103 | |||
104 | #define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4) | ||
105 | #define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4) | ||
106 | |||
107 | #define S3C2443_CLKCON_NAND | ||
108 | |||
109 | #define S3C2443_HCLKCON_DMA0 (1<<0) | ||
110 | #define S3C2443_HCLKCON_DMA1 (1<<1) | ||
111 | #define S3C2443_HCLKCON_DMA2 (1<<2) | ||
112 | #define S3C2443_HCLKCON_DMA3 (1<<3) | ||
113 | #define S3C2443_HCLKCON_DMA4 (1<<4) | ||
114 | #define S3C2443_HCLKCON_DMA5 (1<<5) | ||
115 | #define S3C2443_HCLKCON_CAMIF (1<<8) | ||
116 | #define S3C2443_HCLKCON_DISP (1<<9) | ||
117 | #define S3C2443_HCLKCON_LCDC (1<<10) | ||
118 | #define S3C2443_HCLKCON_USBH (1<<11) | ||
119 | #define S3C2443_HCLKCON_USBD (1<<12) | ||
120 | #define S3C2443_HCLKCON_HSMMC (1<<16) | ||
121 | #define S3C2443_HCLKCON_CFC (1<<17) | ||
122 | #define S3C2443_HCLKCON_SSMC (1<<18) | ||
123 | #define S3C2443_HCLKCON_DRAMC (1<<19) | ||
124 | |||
125 | #define S3C2443_PCLKCON_UART0 (1<<0) | ||
126 | #define S3C2443_PCLKCON_UART1 (1<<1) | ||
127 | #define S3C2443_PCLKCON_UART2 (1<<2) | ||
128 | #define S3C2443_PCLKCON_UART3 (1<<3) | ||
129 | #define S3C2443_PCLKCON_IIC (1<<4) | ||
130 | #define S3C2443_PCLKCON_SDI (1<<5) | ||
131 | #define S3C2443_PCLKCON_ADC (1<<7) | ||
132 | #define S3C2443_PCLKCON_AC97 (1<<8) | ||
133 | #define S3C2443_PCLKCON_IIS (1<<9) | ||
134 | #define S3C2443_PCLKCON_PWMT (1<<10) | ||
135 | #define S3C2443_PCLKCON_WDT (1<<11) | ||
136 | #define S3C2443_PCLKCON_RTC (1<<12) | ||
137 | #define S3C2443_PCLKCON_GPIO (1<<13) | ||
138 | #define S3C2443_PCLKCON_SPI0 (1<<14) | ||
139 | #define S3C2443_PCLKCON_SPI1 (1<<15) | ||
140 | |||
141 | #define S3C2443_SCLKCON_DDRCLK (1<<16) | ||
142 | #define S3C2443_SCLKCON_SSMCCLK (1<<15) | ||
143 | #define S3C2443_SCLKCON_HSSPICLK (1<<14) | ||
144 | #define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13) | ||
145 | #define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12) | ||
146 | #define S3C2443_SCLKCON_CAMCLK (1<<11) | ||
147 | #define S3C2443_SCLKCON_DISPCLK (1<<10) | ||
148 | #define S3C2443_SCLKCON_I2SCLK (1<<9) | ||
149 | #define S3C2443_SCLKCON_UARTCLK (1<<8) | ||
150 | #define S3C2443_SCLKCON_USBHOST (1<<1) | ||
151 | |||
152 | #include <asm/div64.h> | ||
153 | |||
154 | static inline unsigned int | ||
155 | s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk) | ||
156 | { | ||
157 | unsigned int mdiv, pdiv, sdiv; | ||
158 | uint64_t fvco; | ||
159 | |||
160 | mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; | ||
161 | pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; | ||
162 | sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; | ||
163 | |||
164 | mdiv &= S3C2443_PLLCON_MDIVMASK; | ||
165 | pdiv &= S3C2443_PLLCON_PDIVMASK; | ||
166 | sdiv &= S3C2443_PLLCON_SDIVMASK; | ||
167 | |||
168 | fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); | ||
169 | do_div(fvco, pdiv << sdiv); | ||
170 | |||
171 | return (unsigned int)fvco; | ||
172 | } | ||
173 | |||
174 | static inline unsigned int | ||
175 | s3c2443_get_epll(unsigned int pllval, unsigned int baseclk) | ||
176 | { | ||
177 | unsigned int mdiv, pdiv, sdiv; | ||
178 | uint64_t fvco; | ||
179 | |||
180 | mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; | ||
181 | pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; | ||
182 | sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; | ||
183 | |||
184 | mdiv &= S3C2443_PLLCON_MDIVMASK; | ||
185 | pdiv &= S3C2443_PLLCON_PDIVMASK; | ||
186 | sdiv &= S3C2443_PLLCON_SDIVMASK; | ||
187 | |||
188 | fvco = (uint64_t)baseclk * (mdiv + 8); | ||
189 | do_div(fvco, (pdiv + 2) << sdiv); | ||
190 | |||
191 | return (unsigned int)fvco; | ||
192 | } | ||
193 | |||
194 | #endif /* __ASM_ARM_REGS_S3C2443_CLOCK */ | ||
195 | |||
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h b/arch/arm/mach-s3c2410/include/mach/regs-sdi.h new file mode 100644 index 000000000000..cbf2d8884e30 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-sdi.h | |||
@@ -0,0 +1,127 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-sdi.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 MMC/SDIO register definitions | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARM_REGS_SDI | ||
14 | #define __ASM_ARM_REGS_SDI "regs-sdi.h" | ||
15 | |||
16 | #define S3C2410_SDICON (0x00) | ||
17 | #define S3C2410_SDIPRE (0x04) | ||
18 | #define S3C2410_SDICMDARG (0x08) | ||
19 | #define S3C2410_SDICMDCON (0x0C) | ||
20 | #define S3C2410_SDICMDSTAT (0x10) | ||
21 | #define S3C2410_SDIRSP0 (0x14) | ||
22 | #define S3C2410_SDIRSP1 (0x18) | ||
23 | #define S3C2410_SDIRSP2 (0x1C) | ||
24 | #define S3C2410_SDIRSP3 (0x20) | ||
25 | #define S3C2410_SDITIMER (0x24) | ||
26 | #define S3C2410_SDIBSIZE (0x28) | ||
27 | #define S3C2410_SDIDCON (0x2C) | ||
28 | #define S3C2410_SDIDCNT (0x30) | ||
29 | #define S3C2410_SDIDSTA (0x34) | ||
30 | #define S3C2410_SDIFSTA (0x38) | ||
31 | |||
32 | #define S3C2410_SDIDATA (0x3C) | ||
33 | #define S3C2410_SDIIMSK (0x40) | ||
34 | |||
35 | #define S3C2440_SDIDATA (0x40) | ||
36 | #define S3C2440_SDIIMSK (0x3C) | ||
37 | |||
38 | #define S3C2440_SDICON_SDRESET (1<<8) | ||
39 | #define S3C2440_SDICON_MMCCLOCK (1<<5) | ||
40 | #define S3C2410_SDICON_BYTEORDER (1<<4) | ||
41 | #define S3C2410_SDICON_SDIOIRQ (1<<3) | ||
42 | #define S3C2410_SDICON_RWAITEN (1<<2) | ||
43 | #define S3C2410_SDICON_FIFORESET (1<<1) | ||
44 | #define S3C2410_SDICON_CLOCKTYPE (1<<0) | ||
45 | |||
46 | #define S3C2410_SDICMDCON_ABORT (1<<12) | ||
47 | #define S3C2410_SDICMDCON_WITHDATA (1<<11) | ||
48 | #define S3C2410_SDICMDCON_LONGRSP (1<<10) | ||
49 | #define S3C2410_SDICMDCON_WAITRSP (1<<9) | ||
50 | #define S3C2410_SDICMDCON_CMDSTART (1<<8) | ||
51 | #define S3C2410_SDICMDCON_SENDERHOST (1<<6) | ||
52 | #define S3C2410_SDICMDCON_INDEX (0x3f) | ||
53 | |||
54 | #define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) | ||
55 | #define S3C2410_SDICMDSTAT_CMDSENT (1<<11) | ||
56 | #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) | ||
57 | #define S3C2410_SDICMDSTAT_RSPFIN (1<<9) | ||
58 | #define S3C2410_SDICMDSTAT_XFERING (1<<8) | ||
59 | #define S3C2410_SDICMDSTAT_INDEX (0xff) | ||
60 | |||
61 | #define S3C2440_SDIDCON_DS_BYTE (0<<22) | ||
62 | #define S3C2440_SDIDCON_DS_HALFWORD (1<<22) | ||
63 | #define S3C2440_SDIDCON_DS_WORD (2<<22) | ||
64 | #define S3C2410_SDIDCON_IRQPERIOD (1<<21) | ||
65 | #define S3C2410_SDIDCON_TXAFTERRESP (1<<20) | ||
66 | #define S3C2410_SDIDCON_RXAFTERCMD (1<<19) | ||
67 | #define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) | ||
68 | #define S3C2410_SDIDCON_BLOCKMODE (1<<17) | ||
69 | #define S3C2410_SDIDCON_WIDEBUS (1<<16) | ||
70 | #define S3C2410_SDIDCON_DMAEN (1<<15) | ||
71 | #define S3C2410_SDIDCON_STOP (1<<14) | ||
72 | #define S3C2440_SDIDCON_DATSTART (1<<14) | ||
73 | #define S3C2410_SDIDCON_DATMODE (3<<12) | ||
74 | #define S3C2410_SDIDCON_BLKNUM (0x7ff) | ||
75 | |||
76 | /* constants for S3C2410_SDIDCON_DATMODE */ | ||
77 | #define S3C2410_SDIDCON_XFER_READY (0<<12) | ||
78 | #define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) | ||
79 | #define S3C2410_SDIDCON_XFER_RXSTART (2<<12) | ||
80 | #define S3C2410_SDIDCON_XFER_TXSTART (3<<12) | ||
81 | |||
82 | #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) | ||
83 | #define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) | ||
84 | |||
85 | #define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) | ||
86 | #define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) | ||
87 | #define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ | ||
88 | #define S3C2410_SDIDSTA_CRCFAIL (1<<7) | ||
89 | #define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) | ||
90 | #define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) | ||
91 | #define S3C2410_SDIDSTA_XFERFINISH (1<<4) | ||
92 | #define S3C2410_SDIDSTA_BUSYFINISH (1<<3) | ||
93 | #define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ | ||
94 | #define S3C2410_SDIDSTA_TXDATAON (1<<1) | ||
95 | #define S3C2410_SDIDSTA_RXDATAON (1<<0) | ||
96 | |||
97 | #define S3C2440_SDIFSTA_FIFORESET (1<<16) | ||
98 | #define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ | ||
99 | #define S3C2410_SDIFSTA_TFDET (1<<13) | ||
100 | #define S3C2410_SDIFSTA_RFDET (1<<12) | ||
101 | #define S3C2410_SDIFSTA_TFHALF (1<<11) | ||
102 | #define S3C2410_SDIFSTA_TFEMPTY (1<<10) | ||
103 | #define S3C2410_SDIFSTA_RFLAST (1<<9) | ||
104 | #define S3C2410_SDIFSTA_RFFULL (1<<8) | ||
105 | #define S3C2410_SDIFSTA_RFHALF (1<<7) | ||
106 | #define S3C2410_SDIFSTA_COUNTMASK (0x7f) | ||
107 | |||
108 | #define S3C2410_SDIIMSK_RESPONSECRC (1<<17) | ||
109 | #define S3C2410_SDIIMSK_CMDSENT (1<<16) | ||
110 | #define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) | ||
111 | #define S3C2410_SDIIMSK_RESPONSEND (1<<14) | ||
112 | #define S3C2410_SDIIMSK_READWAIT (1<<13) | ||
113 | #define S3C2410_SDIIMSK_SDIOIRQ (1<<12) | ||
114 | #define S3C2410_SDIIMSK_FIFOFAIL (1<<11) | ||
115 | #define S3C2410_SDIIMSK_CRCSTATUS (1<<10) | ||
116 | #define S3C2410_SDIIMSK_DATACRC (1<<9) | ||
117 | #define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) | ||
118 | #define S3C2410_SDIIMSK_DATAFINISH (1<<7) | ||
119 | #define S3C2410_SDIIMSK_BUSYFINISH (1<<6) | ||
120 | #define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ | ||
121 | #define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) | ||
122 | #define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) | ||
123 | #define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) | ||
124 | #define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) | ||
125 | #define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) | ||
126 | |||
127 | #endif /* __ASM_ARM_REGS_SDI */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/reset.h b/arch/arm/mach-s3c2410/include/mach/reset.h new file mode 100644 index 000000000000..f8c9387b049d --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/reset.h | |||
@@ -0,0 +1,22 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/reset.h | ||
2 | * | ||
3 | * Copyright (c) 2007 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * S3C2410 CPU reset controls | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_RESET_H | ||
15 | #define __ASM_ARCH_RESET_H __FILE__ | ||
16 | |||
17 | /* This allows the over-ride of the default reset code | ||
18 | */ | ||
19 | |||
20 | extern void (*s3c24xx_reset_hook)(void); | ||
21 | |||
22 | #endif /* __ASM_ARCH_RESET_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h new file mode 100644 index 000000000000..3fe8be9ca110 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h | |||
@@ -0,0 +1,27 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/spi-gpio.h | ||
2 | * | ||
3 | * Copyright (c) 2006 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - SPI Controller platfrom_device info | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_SPIGPIO_H | ||
14 | #define __ASM_ARCH_SPIGPIO_H __FILE__ | ||
15 | |||
16 | struct s3c2410_spigpio_info { | ||
17 | unsigned long pin_clk; | ||
18 | unsigned long pin_mosi; | ||
19 | unsigned long pin_miso; | ||
20 | |||
21 | int bus_num; | ||
22 | |||
23 | void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs); | ||
24 | }; | ||
25 | |||
26 | |||
27 | #endif /* __ASM_ARCH_SPIGPIO_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h new file mode 100644 index 000000000000..921b13b4f0a0 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/spi.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/spi.h | ||
2 | * | ||
3 | * Copyright (c) 2006 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - SPI Controller platform_device info | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_SPI_H | ||
14 | #define __ASM_ARCH_SPI_H __FILE__ | ||
15 | |||
16 | struct s3c2410_spi_info { | ||
17 | unsigned long pin_cs; /* simple gpio cs */ | ||
18 | unsigned int num_cs; /* total chipselects */ | ||
19 | int bus_num; /* bus number to use. */ | ||
20 | |||
21 | void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); | ||
22 | }; | ||
23 | |||
24 | |||
25 | #endif /* __ASM_ARCH_SPI_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h new file mode 100644 index 000000000000..ec2defebf0d5 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h | |||
@@ -0,0 +1,64 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/system-reset.h | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - System define for arch_reset() function | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <mach/hardware.h> | ||
14 | #include <asm/io.h> | ||
15 | |||
16 | #include <asm/plat-s3c/regs-watchdog.h> | ||
17 | #include <mach/regs-clock.h> | ||
18 | |||
19 | #include <linux/clk.h> | ||
20 | #include <linux/err.h> | ||
21 | |||
22 | extern void (*s3c24xx_reset_hook)(void); | ||
23 | |||
24 | static void | ||
25 | arch_reset(char mode) | ||
26 | { | ||
27 | struct clk *wdtclk; | ||
28 | |||
29 | if (mode == 's') { | ||
30 | cpu_reset(0); | ||
31 | } | ||
32 | |||
33 | if (s3c24xx_reset_hook) | ||
34 | s3c24xx_reset_hook(); | ||
35 | |||
36 | printk("arch_reset: attempting watchdog reset\n"); | ||
37 | |||
38 | __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ | ||
39 | |||
40 | wdtclk = clk_get(NULL, "watchdog"); | ||
41 | if (!IS_ERR(wdtclk)) { | ||
42 | clk_enable(wdtclk); | ||
43 | } else | ||
44 | printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); | ||
45 | |||
46 | /* put initial values into count and data */ | ||
47 | __raw_writel(0x80, S3C2410_WTCNT); | ||
48 | __raw_writel(0x80, S3C2410_WTDAT); | ||
49 | |||
50 | /* set the watchdog to go and reset... */ | ||
51 | __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | | ||
52 | S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); | ||
53 | |||
54 | /* wait for reset to assert... */ | ||
55 | mdelay(500); | ||
56 | |||
57 | printk(KERN_ERR "Watchdog reset failed to assert reset\n"); | ||
58 | |||
59 | /* delay to allow the serial port to show the message */ | ||
60 | mdelay(50); | ||
61 | |||
62 | /* we'll take a jump through zero as a poor second */ | ||
63 | cpu_reset(0); | ||
64 | } | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/system.h b/arch/arm/mach-s3c2410/include/mach/system.h new file mode 100644 index 000000000000..e9f676bc0116 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/system.h | |||
@@ -0,0 +1,58 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/system.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - System function defines and includes | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <mach/hardware.h> | ||
14 | #include <asm/io.h> | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | #include <mach/idle.h> | ||
18 | #include <mach/reset.h> | ||
19 | |||
20 | #include <mach/regs-clock.h> | ||
21 | |||
22 | void (*s3c24xx_idle)(void); | ||
23 | void (*s3c24xx_reset_hook)(void); | ||
24 | |||
25 | void s3c24xx_default_idle(void) | ||
26 | { | ||
27 | unsigned long tmp; | ||
28 | int i; | ||
29 | |||
30 | /* idle the system by using the idle mode which will wait for an | ||
31 | * interrupt to happen before restarting the system. | ||
32 | */ | ||
33 | |||
34 | /* Warning: going into idle state upsets jtag scanning */ | ||
35 | |||
36 | __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE, | ||
37 | S3C2410_CLKCON); | ||
38 | |||
39 | /* the samsung port seems to do a loop and then unset idle.. */ | ||
40 | for (i = 0; i < 50; i++) { | ||
41 | tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */ | ||
42 | } | ||
43 | |||
44 | /* this bit is not cleared on re-start... */ | ||
45 | |||
46 | __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE, | ||
47 | S3C2410_CLKCON); | ||
48 | } | ||
49 | |||
50 | static void arch_idle(void) | ||
51 | { | ||
52 | if (s3c24xx_idle != NULL) | ||
53 | (s3c24xx_idle)(); | ||
54 | else | ||
55 | s3c24xx_default_idle(); | ||
56 | } | ||
57 | |||
58 | #include <mach/system-reset.h> | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/mach-s3c2410/include/mach/timex.h new file mode 100644 index 000000000000..2a425ed0a7e0 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/timex.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/timex.h | ||
2 | * | ||
3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - time parameters | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_TIMEX_H | ||
14 | #define __ASM_ARCH_TIMEX_H | ||
15 | |||
16 | /* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it | ||
17 | * a variable is useless. It seems as long as we make our timers an | ||
18 | * exact multiple of HZ, any value that makes a 1->1 correspondence | ||
19 | * for the time conversion functions to/from jiffies is acceptable. | ||
20 | */ | ||
21 | |||
22 | |||
23 | #define CLOCK_TICK_RATE 12000000 | ||
24 | |||
25 | |||
26 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h new file mode 100644 index 000000000000..708e47459ffc --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/uncompress.h | ||
2 | * | ||
3 | * Copyright (c) 2003, 2007 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C2410 - uncompress code | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
15 | #define __ASM_ARCH_UNCOMPRESS_H | ||
16 | |||
17 | #include <mach/regs-gpio.h> | ||
18 | #include <mach/map.h> | ||
19 | |||
20 | /* working in physical space... */ | ||
21 | #undef S3C2410_GPIOREG | ||
22 | #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) | ||
23 | |||
24 | #include <asm/plat-s3c/uncompress.h> | ||
25 | |||
26 | static inline int is_arm926(void) | ||
27 | { | ||
28 | unsigned int cpuid; | ||
29 | |||
30 | asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid)); | ||
31 | |||
32 | return ((cpuid & 0xff0) == 0x260); | ||
33 | } | ||
34 | |||
35 | static void arch_detect_cpu(void) | ||
36 | { | ||
37 | unsigned int cpuid; | ||
38 | |||
39 | cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); | ||
40 | cpuid &= S3C2410_GSTATUS1_IDMASK; | ||
41 | |||
42 | if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || | ||
43 | cpuid == S3C2410_GSTATUS1_2442) { | ||
44 | fifo_mask = S3C2440_UFSTAT_TXMASK; | ||
45 | fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; | ||
46 | } else { | ||
47 | fifo_mask = S3C2410_UFSTAT_TXMASK; | ||
48 | fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT; | ||
49 | } | ||
50 | } | ||
51 | |||
52 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/usb-control.h b/arch/arm/mach-s3c2410/include/mach/usb-control.h new file mode 100644 index 000000000000..cd91d1591f31 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/usb-control.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/usb-control.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - usb port information | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_USBCONTROL_H | ||
14 | #define __ASM_ARCH_USBCONTROL_H "arch/arm/mach-s3c2410/include/mach/usb-control.h" | ||
15 | |||
16 | #define S3C_HCDFLG_USED (1) | ||
17 | |||
18 | struct s3c2410_hcd_port { | ||
19 | unsigned char flags; | ||
20 | unsigned char power; | ||
21 | unsigned char oc_status; | ||
22 | unsigned char oc_changed; | ||
23 | }; | ||
24 | |||
25 | struct s3c2410_hcd_info { | ||
26 | struct usb_hcd *hcd; | ||
27 | struct s3c2410_hcd_port port[2]; | ||
28 | |||
29 | void (*power_control)(int port, int to); | ||
30 | void (*enable_oc)(struct s3c2410_hcd_info *, int on); | ||
31 | void (*report_oc)(struct s3c2410_hcd_info *, int ports); | ||
32 | }; | ||
33 | |||
34 | static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports) | ||
35 | { | ||
36 | if (info->report_oc != NULL) { | ||
37 | (info->report_oc)(info, ports); | ||
38 | } | ||
39 | } | ||
40 | |||
41 | #endif /*__ASM_ARCH_USBCONTROL_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h new file mode 100644 index 000000000000..315b0078a34d --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/vmalloc.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/vmalloc.h | ||
2 | * | ||
3 | * from arch/arm/mach-iop3xx/include/mach/vmalloc.h | ||
4 | * | ||
5 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
6 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | * S3C2410 vmalloc definition | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_VMALLOC_H | ||
16 | #define __ASM_ARCH_VMALLOC_H | ||
17 | |||
18 | #define VMALLOC_END (0xE0000000) | ||
19 | |||
20 | #endif /* __ASM_ARCH_VMALLOC_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h new file mode 100644 index 000000000000..e4119913d7c5 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * VR1000 - CPLD control constants | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_VR1000CPLD_H | ||
14 | #define __ASM_ARCH_VR1000CPLD_H | ||
15 | |||
16 | #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */ | ||
17 | |||
18 | #endif /* __ASM_ARCH_VR1000CPLD_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h new file mode 100644 index 000000000000..f53f85b4ad8b --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h | ||
2 | * | ||
3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Machine VR1000 - IRQ Number definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_VR1000IRQ_H | ||
14 | #define __ASM_ARCH_VR1000IRQ_H | ||
15 | |||
16 | /* irq numbers to onboard peripherals */ | ||
17 | |||
18 | #define IRQ_USBOC IRQ_EINT19 | ||
19 | #define IRQ_IDE0 IRQ_EINT16 | ||
20 | #define IRQ_IDE1 IRQ_EINT17 | ||
21 | #define IRQ_VR1000_SERIAL IRQ_EINT12 | ||
22 | #define IRQ_VR1000_DM9000A IRQ_EINT10 | ||
23 | #define IRQ_VR1000_DM9000N IRQ_EINT9 | ||
24 | #define IRQ_SMALERT IRQ_EINT8 | ||
25 | |||
26 | #endif /* __ASM_ARCH_VR1000IRQ_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h b/arch/arm/mach-s3c2410/include/mach/vr1000-map.h new file mode 100644 index 000000000000..99612fcc4eb2 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/vr1000-map.h | |||
@@ -0,0 +1,110 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/vr1000-map.h | ||
2 | * | ||
3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Machine VR1000 - Memory map definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | /* needs arch/map.h including with this */ | ||
14 | |||
15 | /* ok, we've used up to 0x13000000, now we need to find space for the | ||
16 | * peripherals that live in the nGCS[x] areas, which are quite numerous | ||
17 | * in their space. We also have the board's CPLD to find register space | ||
18 | * for. | ||
19 | */ | ||
20 | |||
21 | #ifndef __ASM_ARCH_VR1000MAP_H | ||
22 | #define __ASM_ARCH_VR1000MAP_H | ||
23 | |||
24 | #include <mach/bast-map.h> | ||
25 | |||
26 | #define VR1000_IOADDR(x) BAST_IOADDR(x) | ||
27 | |||
28 | /* we put the CPLD registers next, to get them out of the way */ | ||
29 | |||
30 | #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */ | ||
31 | #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000) | ||
32 | |||
33 | #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */ | ||
34 | #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000) | ||
35 | |||
36 | #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */ | ||
37 | #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000) | ||
38 | |||
39 | #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */ | ||
40 | #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000) | ||
41 | |||
42 | /* next, we have the PC104 ISA interrupt registers */ | ||
43 | |||
44 | #define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ | ||
45 | #define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000) | ||
46 | |||
47 | #define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ | ||
48 | #define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000) | ||
49 | |||
50 | #define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ | ||
51 | #define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000) | ||
52 | |||
53 | /* 0xE0000000 contains the IO space that is split by speed and | ||
54 | * wether the access is for 8 or 16bit IO... this ensures that | ||
55 | * the correct access is made | ||
56 | * | ||
57 | * 0x10000000 of space, partitioned as so: | ||
58 | * | ||
59 | * 0x00000000 to 0x04000000 8bit, slow | ||
60 | * 0x04000000 to 0x08000000 16bit, slow | ||
61 | * 0x08000000 to 0x0C000000 16bit, net | ||
62 | * 0x0C000000 to 0x10000000 16bit, fast | ||
63 | * | ||
64 | * each of these spaces has the following in: | ||
65 | * | ||
66 | * 0x02000000 to 0x02100000 1MB IDE primary channel | ||
67 | * 0x02100000 to 0x02200000 1MB IDE primary channel aux | ||
68 | * 0x02200000 to 0x02400000 1MB IDE secondary channel | ||
69 | * 0x02300000 to 0x02400000 1MB IDE secondary channel aux | ||
70 | * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers | ||
71 | * 0x02600000 to 0x02700000 1MB | ||
72 | * | ||
73 | * the phyiscal layout of the zones are: | ||
74 | * nGCS2 - 8bit, slow | ||
75 | * nGCS3 - 16bit, slow | ||
76 | * nGCS4 - 16bit, net | ||
77 | * nGCS5 - 16bit, fast | ||
78 | */ | ||
79 | |||
80 | #define VR1000_VA_MULTISPACE (0xE0000000) | ||
81 | |||
82 | #define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000) | ||
83 | #define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000) | ||
84 | #define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000) | ||
85 | #define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000) | ||
86 | #define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000) | ||
87 | #define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000) | ||
88 | #define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000) | ||
89 | #define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000) | ||
90 | #define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000) | ||
91 | |||
92 | /* physical offset addresses for the peripherals */ | ||
93 | |||
94 | #define VR1000_PA_IDEPRI (0x02000000) | ||
95 | #define VR1000_PA_IDEPRIAUX (0x02800000) | ||
96 | #define VR1000_PA_IDESEC (0x03000000) | ||
97 | #define VR1000_PA_IDESECAUX (0x03800000) | ||
98 | #define VR1000_PA_DM9000 (0x05000000) | ||
99 | |||
100 | #define VR1000_PA_SERIAL (0x11800000) | ||
101 | #define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000)) | ||
102 | |||
103 | /* VR1000 ram is in CS1, with A26..A24 = 2_101 */ | ||
104 | #define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000) | ||
105 | |||
106 | /* some configurations for the peripherals */ | ||
107 | |||
108 | #define VR1000_DM9000_CS VR1000_VAM_CS4 | ||
109 | |||
110 | #endif /* __ASM_ARCH_VR1000MAP_H */ | ||