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authorKukjin Kim <kgene.kim@samsung.com>2011-08-30 03:49:36 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-09-16 07:20:33 -0400
commitae79ac5c0ccb8789df661b8aa4b16bac4243f43d (patch)
tree8a6816c4c35083b543c2c6a4e8940e767e80f1ba /arch/arm/mach-s3c2410/include/mach/map.h
parentb6fd41e29dea9c6753b1843a77e50433e6123bcb (diff)
ARM: SAMSUNG: Move map header file into plat-samsung
This is required to work consolidation Samsung platform. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/map.h')
-rw-r--r--arch/arm/mach-s3c2410/include/mach/map.h52
1 files changed, 46 insertions, 6 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 425552d84b60..4cf495f813a7 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -14,9 +14,53 @@
14#define __ASM_ARCH_MAP_H 14#define __ASM_ARCH_MAP_H
15 15
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map.h>
18 17
19#define S3C2410_ADDR(x) S3C_ADDR(x) 18/*
19 * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x4000)
23
24#include <plat/map-s3c.h>
25
26/*
27 * interrupt controller is the first thing we put in, to make
28 * the assembly code for the irq detection easier
29 */
30#define S3C2410_PA_IRQ (0x4A000000)
31#define S3C24XX_SZ_IRQ SZ_1M
32
33/* memory controller registers */
34#define S3C2410_PA_MEMCTRL (0x48000000)
35#define S3C24XX_SZ_MEMCTRL SZ_1M
36
37/* UARTs */
38#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
39
40/* Timers */
41#define S3C2410_PA_TIMER (0x51000000)
42#define S3C24XX_SZ_TIMER SZ_1M
43
44/* Clock and Power management */
45#define S3C24XX_SZ_CLKPWR SZ_1M
46
47/* USB Device port */
48#define S3C2410_PA_USBDEV (0x52000000)
49#define S3C24XX_SZ_USBDEV SZ_1M
50
51/* Watchdog */
52#define S3C2410_PA_WATCHDOG (0x53000000)
53#define S3C24XX_SZ_WATCHDOG SZ_1M
54
55/* Standard size definitions for peripheral blocks. */
56
57#define S3C24XX_SZ_UART SZ_1M
58#define S3C24XX_SZ_IIS SZ_1M
59#define S3C24XX_SZ_ADC SZ_1M
60#define S3C24XX_SZ_SPI SZ_1M
61#define S3C24XX_SZ_SDI SZ_1M
62#define S3C24XX_SZ_NAND SZ_1M
63#define S3C24XX_SZ_GPIO SZ_1M
20 64
21/* USB host controller */ 65/* USB host controller */
22#define S3C2410_PA_USBHOST (0x49000000) 66#define S3C2410_PA_USBHOST (0x49000000)
@@ -75,10 +119,8 @@
75 119
76/* S3C2412 memory and IO controls */ 120/* S3C2412 memory and IO controls */
77#define S3C2412_PA_SSMC (0x4F000000) 121#define S3C2412_PA_SSMC (0x4F000000)
78#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
79 122
80#define S3C2412_PA_EBI (0x48800000) 123#define S3C2412_PA_EBI (0x48800000)
81#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
82 124
83/* physical addresses of all the chip-select areas */ 125/* physical addresses of all the chip-select areas */
84 126
@@ -100,12 +142,10 @@
100#define S3C24XX_PA_DMA S3C2410_PA_DMA 142#define S3C24XX_PA_DMA S3C2410_PA_DMA
101#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR 143#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
102#define S3C24XX_PA_LCD S3C2410_PA_LCD 144#define S3C24XX_PA_LCD S3C2410_PA_LCD
103#define S3C24XX_PA_UART S3C2410_PA_UART
104#define S3C24XX_PA_TIMER S3C2410_PA_TIMER 145#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
105#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV 146#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
106#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG 147#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
107#define S3C24XX_PA_IIS S3C2410_PA_IIS 148#define S3C24XX_PA_IIS S3C2410_PA_IIS
108#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
109#define S3C24XX_PA_RTC S3C2410_PA_RTC 149#define S3C24XX_PA_RTC S3C2410_PA_RTC
110#define S3C24XX_PA_ADC S3C2410_PA_ADC 150#define S3C24XX_PA_ADC S3C2410_PA_ADC
111#define S3C24XX_PA_SPI S3C2410_PA_SPI 151#define S3C24XX_PA_SPI S3C2410_PA_SPI