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authorLucas Correia Villa Real <lucasvr@gobolinux.org>2006-02-01 16:24:23 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-02-01 16:24:23 -0500
commit0ca5bc3de715f6e031d44ffecdd2d127891eccf5 (patch)
treeec963c52b7c60d1cd6862798f5bdfce87387082b /arch/arm/mach-s3c2410/gpio.c
parent7610dfa3723e87705964b29db9775620d96bf618 (diff)
[ARM] 3284/1: S3C2400 - adds support to GPIO
Patch from Lucas Correia Villa Real This patch adds support to GPIO on the S3C2400, which is going to be used by the GP32 machine and the SMDK2400 development board. Signed-off-by: Lucas Correia Villa Real <lucasvr@gobolinux.org> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410/gpio.c')
-rw-r--r--arch/arm/mach-s3c2410/gpio.c72
1 files changed, 8 insertions, 64 deletions
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index 23ea3d5fa09c..cd39e8684584 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -31,6 +31,7 @@
31 * 05-Nov-2004 BJD EXPORT_SYMBOL() added for all code 31 * 05-Nov-2004 BJD EXPORT_SYMBOL() added for all code
32 * 13-Mar-2005 BJD Updates for __iomem 32 * 13-Mar-2005 BJD Updates for __iomem
33 * 26-Oct-2005 BJD Added generic configuration types 33 * 26-Oct-2005 BJD Added generic configuration types
34 * 15-Jan-2006 LCVR Added support for the S3C2400
34 */ 35 */
35 36
36 37
@@ -48,7 +49,7 @@
48 49
49void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function) 50void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
50{ 51{
51 void __iomem *base = S3C2410_GPIO_BASE(pin); 52 void __iomem *base = S3C24XX_GPIO_BASE(pin);
52 unsigned long mask; 53 unsigned long mask;
53 unsigned long con; 54 unsigned long con;
54 unsigned long flags; 55 unsigned long flags;
@@ -95,7 +96,7 @@ EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
95 96
96unsigned int s3c2410_gpio_getcfg(unsigned int pin) 97unsigned int s3c2410_gpio_getcfg(unsigned int pin)
97{ 98{
98 void __iomem *base = S3C2410_GPIO_BASE(pin); 99 void __iomem *base = S3C24XX_GPIO_BASE(pin);
99 unsigned long mask; 100 unsigned long mask;
100 101
101 if (pin < S3C2410_GPIO_BANKB) { 102 if (pin < S3C2410_GPIO_BANKB) {
@@ -111,7 +112,7 @@ EXPORT_SYMBOL(s3c2410_gpio_getcfg);
111 112
112void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) 113void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
113{ 114{
114 void __iomem *base = S3C2410_GPIO_BASE(pin); 115 void __iomem *base = S3C24XX_GPIO_BASE(pin);
115 unsigned long offs = S3C2410_GPIO_OFFSET(pin); 116 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
116 unsigned long flags; 117 unsigned long flags;
117 unsigned long up; 118 unsigned long up;
@@ -133,7 +134,7 @@ EXPORT_SYMBOL(s3c2410_gpio_pullup);
133 134
134void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) 135void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
135{ 136{
136 void __iomem *base = S3C2410_GPIO_BASE(pin); 137 void __iomem *base = S3C24XX_GPIO_BASE(pin);
137 unsigned long offs = S3C2410_GPIO_OFFSET(pin); 138 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
138 unsigned long flags; 139 unsigned long flags;
139 unsigned long dat; 140 unsigned long dat;
@@ -152,7 +153,7 @@ EXPORT_SYMBOL(s3c2410_gpio_setpin);
152 153
153unsigned int s3c2410_gpio_getpin(unsigned int pin) 154unsigned int s3c2410_gpio_getpin(unsigned int pin)
154{ 155{
155 void __iomem *base = S3C2410_GPIO_BASE(pin); 156 void __iomem *base = S3C24XX_GPIO_BASE(pin);
156 unsigned long offs = S3C2410_GPIO_OFFSET(pin); 157 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
157 158
158 return __raw_readl(base + 0x04) & (1<< offs); 159 return __raw_readl(base + 0x04) & (1<< offs);
@@ -166,70 +167,13 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
166 unsigned long misccr; 167 unsigned long misccr;
167 168
168 local_irq_save(flags); 169 local_irq_save(flags);
169 misccr = __raw_readl(S3C2410_MISCCR); 170 misccr = __raw_readl(S3C24XX_MISCCR);
170 misccr &= ~clear; 171 misccr &= ~clear;
171 misccr ^= change; 172 misccr ^= change;
172 __raw_writel(misccr, S3C2410_MISCCR); 173 __raw_writel(misccr, S3C24XX_MISCCR);
173 local_irq_restore(flags); 174 local_irq_restore(flags);
174 175
175 return misccr; 176 return misccr;
176} 177}
177 178
178EXPORT_SYMBOL(s3c2410_modify_misccr); 179EXPORT_SYMBOL(s3c2410_modify_misccr);
179
180int s3c2410_gpio_getirq(unsigned int pin)
181{
182 if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15_EINT23)
183 return -1; /* not valid interrupts */
184
185 if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
186 return -1; /* not valid pin */
187
188 if (pin < S3C2410_GPF4)
189 return (pin - S3C2410_GPF0) + IRQ_EINT0;
190
191 if (pin < S3C2410_GPG0)
192 return (pin - S3C2410_GPF4) + IRQ_EINT4;
193
194 return (pin - S3C2410_GPG0) + IRQ_EINT8;
195}
196
197EXPORT_SYMBOL(s3c2410_gpio_getirq);
198
199int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
200 unsigned int config)
201{
202 void __iomem *reg = S3C2410_EINFLT0;
203 unsigned long flags;
204 unsigned long val;
205
206 if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
207 return -1;
208
209 config &= 0xff;
210
211 pin -= S3C2410_GPG8_EINT16;
212 reg += pin & ~3;
213
214 local_irq_save(flags);
215
216 /* update filter width and clock source */
217
218 val = __raw_readl(reg);
219 val &= ~(0xff << ((pin & 3) * 8));
220 val |= config << ((pin & 3) * 8);
221 __raw_writel(val, reg);
222
223 /* update filter enable */
224
225 val = __raw_readl(S3C2410_EXTINT2);
226 val &= ~(1 << ((pin * 4) + 3));
227 val |= on << ((pin * 4) + 3);
228 __raw_writel(val, S3C2410_EXTINT2);
229
230 local_irq_restore(flags);
231
232 return 0;
233}
234
235EXPORT_SYMBOL(s3c2410_gpio_irqfilter);