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authorMarc Zyngier <Marc.Zyngier@arm.com>2012-01-31 05:49:46 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-02-02 12:00:26 -0500
commitc997e519f3fe6b40a5ad972e2a334960065d6154 (patch)
tree9f4358b16a58e8feef8b1e898d9314e0051a7f80 /arch/arm/mach-realview
parent75c06963dd947252271ffa6107a25cddb2b8f362 (diff)
ARM: 7309/1: realview: fix unconnected interrupts on EB11MP
Since commit 2eac58d (ARM: amba: make use of -1 IRQs warn), we're able to detect the use of value -1 to indicate the lack of interrupt line. The RealView EB, when used with the 11MPCore tile, has a number of devices without interrupts, and uses the value -1 to indicate this. Change that value to 0 to conform to the new behaviour. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-realview')
-rw-r--r--arch/arm/mach-realview/include/mach/irqs-eb.h23
1 files changed, 13 insertions, 10 deletions
diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h
index 204d5378f309..d6b5073692d2 100644
--- a/arch/arm/mach-realview/include/mach/irqs-eb.h
+++ b/arch/arm/mach-realview/include/mach/irqs-eb.h
@@ -96,16 +96,19 @@
96#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30) 96#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
97#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31) 97#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
98 98
99#define IRQ_EB11MP_UART2 -1 99/*
100#define IRQ_EB11MP_UART3 -1 100 * The 11MPcore tile leaves the following unconnected.
101#define IRQ_EB11MP_CLCD -1 101 */
102#define IRQ_EB11MP_DMA -1 102#define IRQ_EB11MP_UART2 0
103#define IRQ_EB11MP_WDOG -1 103#define IRQ_EB11MP_UART3 0
104#define IRQ_EB11MP_GPIO0 -1 104#define IRQ_EB11MP_CLCD 0
105#define IRQ_EB11MP_GPIO1 -1 105#define IRQ_EB11MP_DMA 0
106#define IRQ_EB11MP_GPIO2 -1 106#define IRQ_EB11MP_WDOG 0
107#define IRQ_EB11MP_SCI -1 107#define IRQ_EB11MP_GPIO0 0
108#define IRQ_EB11MP_SSP -1 108#define IRQ_EB11MP_GPIO1 0
109#define IRQ_EB11MP_GPIO2 0
110#define IRQ_EB11MP_SCI 0
111#define IRQ_EB11MP_SSP 0
109 112
110#define NR_GIC_EB11MP 2 113#define NR_GIC_EB11MP 2
111 114