Merge 'Linux v3.0' into Litmus

Some notes:
* Litmus^RT scheduling class is the topmost scheduling class
  (above stop_sched_class).
* scheduler_ipi() function (e.g., in smp_reschedule_interrupt())
  may increase IPI latencies.
* Added path into schedule() to quickly re-evaluate scheduling
  decision without becoming preemptive again. This used to be
  a standard path before the removal of BKL.

Conflicts:
	Makefile
	arch/arm/kernel/calls.S
	arch/arm/kernel/smp.c
	arch/x86/include/asm/unistd_32.h
	arch/x86/kernel/smp.c
	arch/x86/kernel/syscall_table_32.S
	include/linux/hrtimer.h
	kernel/printk.c
	kernel/sched.c
	kernel/sched_fair.c

18 files changed, 174 insertions, 767 deletions

diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index b4575ae9648e..b9a9805e4828 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -2,52 +2,57 @@ menu "RealView platform type"
         depends on ARCH_REALVIEW
 
 config MACH_REALVIEW_EB
-        bool "Support RealView/EB platform"
+        bool "Support RealView(R) Emulation Baseboard"
         select ARM_GIC
         help
-          Include support for the ARM(R) RealView Emulation Baseboard platform.
+          Include support for the ARM(R) RealView(R) Emulation Baseboard
+          platform.
 
 config REALVIEW_EB_A9MP
-        bool "Support Multicore Cortex-A9"
+        bool "Support Multicore Cortex-A9 Tile"
         depends on MACH_REALVIEW_EB
         select CPU_V7
         help
-          Enable support for the Cortex-A9MPCore tile on the Realview platform.
+          Enable support for the Cortex-A9MPCore tile fitted to the
+          Realview(R) Emulation Baseboard platform.
 
 config REALVIEW_EB_ARM11MP
-        bool "Support ARM11MPCore tile"
+        bool "Support ARM11MPCore Tile"
         depends on MACH_REALVIEW_EB
-        select CPU_V6
+        select CPU_V6K
         select ARCH_HAS_BARRIERS if SMP
         help
-          Enable support for the ARM11MPCore tile on the Realview platform.
+          Enable support for the ARM11MPCore tile fitted to the Realview(R)
+          Emulation Baseboard platform.
 
 config REALVIEW_EB_ARM11MP_REVB
-        bool "Support ARM11MPCore RevB tile"
+        bool "Support ARM11MPCore RevB Tile"
         depends on REALVIEW_EB_ARM11MP
         help
-          Enable support for the ARM11MPCore RevB tile on the Realview
-          platform. Since there are device address differences, a
-          kernel built with this option enabled is not compatible with
-          other revisions of the ARM11MPCore tile.
+          Enable support for the ARM11MPCore Revision B tile on the
+          Realview(R) Emulation Baseboard platform. Since there are device
+          address differences, a kernel built with this option enabled is
+          not compatible with other revisions of the ARM11MPCore tile.
 
 config MACH_REALVIEW_PB11MP
-        bool "Support RealView/PB11MPCore platform"
-        select CPU_V6
+        bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
+        select CPU_V6K
         select ARM_GIC
         select HAVE_PATA_PLATFORM
         select ARCH_HAS_BARRIERS if SMP
         help
-          Include support for the ARM(R) RealView MPCore Platform Baseboard.
-          PB11MPCore is a platform with an on-board ARM11MPCore and has
+          Include support for the ARM(R) RealView(R) Platform Baseboard for
+          the ARM11MPCore.  This platform has an on-board ARM11MPCore and has
           support for PCI-E and Compact Flash.
 
+# ARMv6 CPU without K extensions, but does have the new exclusive ops
 config MACH_REALVIEW_PB1176
-        bool "Support RealView/PB1176 platform"
+        bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
         select CPU_V6
         select ARM_GIC
         help
-          Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
+          Include support for the ARM(R) RealView(R) Platform Baseboard for
+          ARM1176JZF-S.
 
 config REALVIEW_PB1176_SECURE_FLASH
         bool "Allow access to the secure flash memory block"
@@ -59,23 +64,24 @@ config REALVIEW_PB1176_SECURE_FLASH
           block (64MB @ 0x3c000000) is required.
 
 config MACH_REALVIEW_PBA8
-        bool "Support RealView/PB-A8 platform"
+        bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform"
         select CPU_V7
         select ARM_GIC
         select HAVE_PATA_PLATFORM
         help
-          Include support for the ARM(R) RealView Cortex-A8 Platform Baseboard.
-          PB-A8 is a platform with an on-board Cortex-A8 and has support for
-          PCI-E and Compact Flash.
+          Include support for the ARM(R) RealView Platform Baseboard for
+          Cortex(tm)-A8.  This platform has an on-board Cortex-A8 and has
+          support for PCI-E and Compact Flash.
 
 config MACH_REALVIEW_PBX
-        bool "Support RealView/PBX platform"
+        bool "Support RealView(R) Platform Baseboard Explore"
         select ARM_GIC
         select HAVE_PATA_PLATFORM
         select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
         select ZONE_DMA if SPARSEMEM
         help
-          Include support for the ARM(R) RealView PBX platform.
+          Include support for the ARM(R) RealView(R) Platform Baseboard
+          Explore.
 
 config REALVIEW_HIGH_PHYS_OFFSET
         bool "High physical base address for the RealView platform"
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index a01b76b7c956..541fa4c109ef 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -8,6 +8,5 @@ obj-$(CONFIG_MACH_REALVIEW_PB11MP)	+= realview_pb11mp.o
 obj-$(CONFIG_MACH_REALVIEW_PB1176)      += realview_pb1176.o
 obj-$(CONFIG_MACH_REALVIEW_PBA8)        += realview_pba8.o
 obj-$(CONFIG_MACH_REALVIEW_PBX)         += realview_pbx.o
-obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
+obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_LOCAL_TIMERS)              += localtimer.o
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 2fa38df28414..5c23450d2d1d 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -30,8 +30,9 @@
 #include <linux/ata_platform.h>
 #include <linux/amba/mmci.h>
 #include <linux/gfp.h>
+#include <linux/clkdev.h>
+#include <linux/mtd/physmap.h>
 
-#include <asm/clkdev.h>
 #include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -41,64 +42,23 @@
 #include <asm/hardware/icst.h>
 
 #include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
 #include <asm/hardware/gic.h>
 
-#include <mach/clkdev.h>
 #include <mach/platform.h>
 #include <mach/irqs.h>
-#include <plat/timer-sp.h>
+#include <asm/hardware/timer-sp.h>
 
-#include "core.h"
-
-/* used by entry-macro.S and platsmp.c */
-void __iomem *gic_cpu_base_addr;
-
-#ifdef CONFIG_ZONE_DMA
-/*
- * Adjust the zones if there are restrictions for DMA access.
- */
-void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
-{
-        unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
-
-        if (!machine_is_realview_pbx() || size[0] <= dma_size)
-                return;
-
-        size[ZONE_NORMAL] = size[0] - dma_size;
-        size[ZONE_DMA] = dma_size;
-        hole[ZONE_NORMAL] = hole[0];
-        hole[ZONE_DMA] = 0;
-}
-#endif
+#include <plat/clcd.h>
+#include <plat/sched_clock.h>
 
+#include "core.h"
 
 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
 
-static int realview_flash_init(void)
-{
-        u32 val;
-
-        val = __raw_readl(REALVIEW_FLASHCTRL);
-        val &= ~REALVIEW_FLASHPROG_FLVPPEN;
-        __raw_writel(val, REALVIEW_FLASHCTRL);
-
-        return 0;
-}
-
-static void realview_flash_exit(void)
-{
-        u32 val;
-
-        val = __raw_readl(REALVIEW_FLASHCTRL);
-        val &= ~REALVIEW_FLASHPROG_FLVPPEN;
-        __raw_writel(val, REALVIEW_FLASHCTRL);
-}
-
-static void realview_flash_set_vpp(int on)
+static void realview_flash_set_vpp(struct platform_device *pdev, int on)
 {
         u32 val;
 
@@ -110,16 +70,13 @@ static void realview_flash_set_vpp(int on)
         __raw_writel(val, REALVIEW_FLASHCTRL);
 }
 
-static struct flash_platform_data realview_flash_data = {
-        .map_name               = "cfi_probe",
+static struct physmap_flash_data realview_flash_data = {
         .width                  = 4,
-        .init                   = realview_flash_init,
-        .exit                   = realview_flash_exit,
         .set_vpp                = realview_flash_set_vpp,
 };
 
 struct platform_device realview_flash_device = {
-        .name                   = "armflash",
+        .name                   = "physmap-flash",
         .id                     = 0,
         .dev                    = {
                 .platform_data  = &realview_flash_data,
@@ -259,6 +216,7 @@ struct mmci_platform_data realview_mmc0_plat_data = {
         .status         = realview_mmc_status,
         .gpio_wp        = 17,
         .gpio_cd        = 16,
+        .cd_invert      = true,
 };
 
 struct mmci_platform_data realview_mmc1_plat_data = {
@@ -266,6 +224,7 @@ struct mmci_platform_data realview_mmc1_plat_data = {
         .status         = realview_mmc_status,
         .gpio_wp        = 19,
         .gpio_cd        = 18,
+        .cd_invert      = true,
 };
 
 /*
@@ -314,6 +273,10 @@ static struct clk ref24_clk = {
         .rate   = 24000000,
 };
 
+static struct clk sp804_clk = {
+        .rate   = 1000000,
+};
+
 static struct clk dummy_apb_pclk;
 
 static struct clk_lookup lookups[] = {
@@ -356,21 +319,25 @@ static struct clk_lookup lookups[] = {
         }, {    /* SSP */
                 .dev_id         = "dev:ssp0",
                 .clk            = &ref24_clk,
-        }
+        }, {    /* SP804 timers */
+                .dev_id         = "sp804",
+                .clk            = &sp804_clk,
+        },
 };
 
-static int __init clk_init(void)
+void __init realview_init_early(void)
 {
+        void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
+
         if (machine_is_realview_pb1176())
-                oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
+                oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
         else
-                oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
+                oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
-        return 0;
+        versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
 }
-core_initcall(clk_init);
 
 /*
  * CLCD support.
@@ -385,157 +352,6 @@ core_initcall(clk_init);
 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 
-static struct clcd_panel vga = {
-        .mode           = {
-                .name           = "VGA",
-                .refresh        = 60,
-                .xres           = 640,
-                .yres           = 480,
-                .pixclock       = 39721,
-                .left_margin    = 40,
-                .right_margin   = 24,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 96,
-                .vsync_len      = 2,
-                .sync           = 0,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = TIM2_BCD | TIM2_IPC,
-        .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
-        .bpp            = 16,
-};
-
-static struct clcd_panel xvga = {
-        .mode           = {
-                .name           = "XVGA",
-                .refresh        = 60,
-                .xres           = 1024,
-                .yres           = 768,
-                .pixclock       = 15748,
-                .left_margin    = 152,
-                .right_margin   = 48,
-                .upper_margin   = 23,
-                .lower_margin   = 3,
-                .hsync_len      = 104,
-                .vsync_len      = 4,
-                .sync           = 0,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = TIM2_BCD | TIM2_IPC,
-        .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
-        .bpp            = 16,
-};
-
-static struct clcd_panel sanyo_3_8_in = {
-        .mode           = {
-                .name           = "Sanyo QVGA",
-                .refresh        = 116,
-                .xres           = 320,
-                .yres           = 240,
-                .pixclock       = 100000,
-                .left_margin    = 6,
-                .right_margin   = 6,
-                .upper_margin   = 5,
-                .lower_margin   = 5,
-                .hsync_len      = 6,
-                .vsync_len      = 6,
-                .sync           = 0,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = TIM2_BCD,
-        .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
-        .bpp            = 16,
-};
-
-static struct clcd_panel sanyo_2_5_in = {
-        .mode           = {
-                .name           = "Sanyo QVGA Portrait",
-                .refresh        = 116,
-                .xres           = 240,
-                .yres           = 320,
-                .pixclock       = 100000,
-                .left_margin    = 20,
-                .right_margin   = 10,
-                .upper_margin   = 2,
-                .lower_margin   = 2,
-                .hsync_len      = 10,
-                .vsync_len      = 2,
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
-        .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
-        .bpp            = 16,
-};
-
-static struct clcd_panel epson_2_2_in = {
-        .mode           = {
-                .name           = "Epson QCIF",
-                .refresh        = 390,
-                .xres           = 176,
-                .yres           = 220,
-                .pixclock       = 62500,
-                .left_margin    = 3,
-                .right_margin   = 2,
-                .upper_margin   = 1,
-                .lower_margin   = 0,
-                .hsync_len      = 3,
-                .vsync_len      = 2,
-                .sync           = 0,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = TIM2_BCD | TIM2_IPC,
-        .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
-        .bpp            = 16,
-};
-
-/*
- * Detect which LCD panel is connected, and return the appropriate
- * clcd_panel structure.  Note: we do not have any information on
- * the required timings for the 8.4in panel, so we presently assume
- * VGA timings.
- */
-static struct clcd_panel *realview_clcd_panel(void)
-{
-        void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
-        struct clcd_panel *vga_panel;
-        struct clcd_panel *panel;
-        u32 val;
-
-        if (machine_is_realview_eb())
-                vga_panel = &vga;
-        else
-                vga_panel = &xvga;
-
-        val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
-        if (val == SYS_CLCD_ID_SANYO_3_8)
-                panel = &sanyo_3_8_in;
-        else if (val == SYS_CLCD_ID_SANYO_2_5)
-                panel = &sanyo_2_5_in;
-        else if (val == SYS_CLCD_ID_EPSON_2_2)
-                panel = &epson_2_2_in;
-        else if (val == SYS_CLCD_ID_VGA)
-                panel = vga_panel;
-        else {
-                printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
-                        val);
-                panel = vga_panel;
-        }
-
-        return panel;
-}
-
 /*
  * Disable all display connectors on the interface module.
  */
@@ -565,56 +381,60 @@ static void realview_clcd_enable(struct clcd_fb *fb)
         writel(val, sys_clcd);
 }
 
+/*
+ * Detect which LCD panel is connected, and return the appropriate
+ * clcd_panel structure.  Note: we do not have any information on
+ * the required timings for the 8.4in panel, so we presently assume
+ * VGA timings.
+ */
 static int realview_clcd_setup(struct clcd_fb *fb)
 {
+        void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
+        const char *panel_name, *vga_panel_name;
         unsigned long framesize;
-        dma_addr_t dma;
+        u32 val;
 
-        if (machine_is_realview_eb())
+        if (machine_is_realview_eb()) {
                 /* VGA, 16bpp */
                 framesize = 640 * 480 * 2;
-        else
+                vga_panel_name = "VGA";
+        } else {
                 /* XVGA, 16bpp */
                 framesize = 1024 * 768 * 2;
-
-        fb->panel               = realview_clcd_panel();
-
-        fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
-                                                    &dma, GFP_KERNEL | GFP_DMA);
-        if (!fb->fb.screen_base) {
-                printk(KERN_ERR "CLCD: unable to map framebuffer\n");
-                return -ENOMEM;
+                vga_panel_name = "XVGA";
         }
 
-        fb->fb.fix.smem_start   = dma;
-        fb->fb.fix.smem_len     = framesize;
-
-        return 0;
-}
+        val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
+        if (val == SYS_CLCD_ID_SANYO_3_8)
+                panel_name = "Sanyo TM38QV67A02A";
+        else if (val == SYS_CLCD_ID_SANYO_2_5)
+                panel_name = "Sanyo QVGA Portrait";
+        else if (val == SYS_CLCD_ID_EPSON_2_2)
+                panel_name = "Epson L2F50113T00";
+        else if (val == SYS_CLCD_ID_VGA)
+                panel_name = vga_panel_name;
+        else {
+                pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val);
+                panel_name = vga_panel_name;
+        }
 
-static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
-{
-        return dma_mmap_writecombine(&fb->dev->dev, vma,
-                                     fb->fb.screen_base,
-                                     fb->fb.fix.smem_start,
-                                     fb->fb.fix.smem_len);
-}
+        fb->panel = versatile_clcd_get_panel(panel_name);
+        if (!fb->panel)
+                return -EINVAL;
 
-static void realview_clcd_remove(struct clcd_fb *fb)
-{
-        dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
-                              fb->fb.screen_base, fb->fb.fix.smem_start);
+        return versatile_clcd_setup_dma(fb, framesize);
 }
 
 struct clcd_board clcd_plat_data = {
         .name           = "RealView",
+        .caps           = CLCD_CAP_ALL,
         .check          = clcdfb_check,
         .decode         = clcdfb_decode,
         .disable        = realview_clcd_disable,
         .enable         = realview_clcd_enable,
         .setup          = realview_clcd_setup,
-        .mmap           = realview_clcd_mmap,
-        .remove         = realview_clcd_remove,
+        .mmap           = versatile_clcd_mmap_dma,
+        .remove         = versatile_clcd_remove_dma,
 };
 
 #ifdef CONFIG_LEDS
@@ -690,8 +510,8 @@ void __init realview_timer_init(unsigned int timer_irq)
         writel(0, timer2_va_base + TIMER_CTRL);
         writel(0, timer3_va_base + TIMER_CTRL);
 
-        sp804_clocksource_init(timer3_va_base);
-        sp804_clockevents_init(timer0_va_base, timer_irq);
+        sp804_clocksource_init(timer3_va_base, "timer3");
+        sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
 }
 
 /*
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 781bca68a9fa..5c83d1e87a03 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -42,7 +42,6 @@ static struct amba_device name##_device = {			\
         },                                                      \
         .dma_mask       = ~0,                                   \
         .irq            = base##_IRQ,                           \
-        /* .dma         = base##_DMA,*/                         \
 }
 
 struct machine_desc;
@@ -53,7 +52,6 @@ extern struct platform_device realview_i2c_device;
 extern struct mmci_platform_data realview_mmc0_plat_data;
 extern struct mmci_platform_data realview_mmc1_plat_data;
 extern struct clcd_board clcd_plat_data;
-extern void __iomem *gic_cpu_base_addr;
 extern void __iomem *timer0_va_base;
 extern void __iomem *timer1_va_base;
 extern void __iomem *timer2_va_base;
@@ -64,6 +62,7 @@ extern void realview_timer_init(unsigned int timer_irq);
 extern int realview_flash_register(struct resource *res, u32 num);
 extern int realview_eth_register(const char *name, struct resource *res);
 extern int realview_usb_register(struct resource *res);
+extern void realview_init_early(void);
 extern void realview_fixup(struct machine_desc *mdesc, struct tag *tags,
                            char **from, struct meminfo *meminfo);
 extern void (*realview_reset)(char);
diff --git a/arch/arm/mach-realview/headsmp.S b/arch/arm/mach-realview/headsmp.S
deleted file mode 100644
index 4075473cf68a..000000000000
--- a/arch/arm/mach-realview/headsmp.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/arch/arm/mach-realview/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-        __INIT
-
-/*
- * Realview specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(realview_secondary_startup)
-        mrc     p15, 0, r0, c0, c0, 5
-        and     r0, r0, #15
-        adr     r4, 1f
-        ldmia   r4, {r5, r6}
-        sub     r4, r4, r5
-        add     r6, r6, r4
-pen:    ldr     r7, [r6]
-        cmp     r7, r0
-        bne     pen
-
-        /*
-         * we've been released from the holding pen: secondary_stack
-         * should now contain the SVC stack for this core
-         */
-        b       secondary_startup
-
-1:      .long   .
-        .long   pen_release
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index f95521a5e5ce..a87523d095e6 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -11,14 +11,11 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
-#include <linux/completion.h>
 
 #include <asm/cacheflush.h>
 
 extern volatile int pen_release;
 
-static DECLARE_COMPLETION(cpu_killed);
-
 static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
@@ -34,10 +31,10 @@ static inline void cpu_enter_lowpower(void)
         "       bic     %0, %0, #0x20\n"
         "       mcr     p15, 0, %0, c1, c0, 1\n"
         "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, #0x04\n"
+        "       bic     %0, %0, %2\n"
         "       mcr     p15, 0, %0, c1, c0, 0\n"
           : "=&r" (v)
-          : "r" (0)
+          : "r" (0), "Ir" (CR_C)
           : "cc");
 }
 
@@ -46,17 +43,17 @@ static inline void cpu_leave_lowpower(void)
         unsigned int v;
 
         asm volatile(   "mrc    p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, #0x04\n"
+        "       orr     %0, %0, %1\n"
         "       mcr     p15, 0, %0, c1, c0, 0\n"
         "       mrc     p15, 0, %0, c1, c0, 1\n"
         "       orr     %0, %0, #0x20\n"
         "       mcr     p15, 0, %0, c1, c0, 1\n"
           : "=&r" (v)
-          :
+          : "Ir" (CR_C)
           : "cc");
 }
 
-static inline void platform_do_lowpower(unsigned int cpu)
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
         /*
          * there is no power-control hardware on this platform, so all
@@ -80,22 +77,19 @@ static inline void platform_do_lowpower(unsigned int cpu)
                 }
 
                 /*
-                 * getting here, means that we have come out of WFI without
+                 * Getting here, means that we have come out of WFI without
                  * having been woken up - this shouldn't happen
                  *
-                 * The trouble is, letting people know about this is not really
-                 * possible, since we are currently running incoherently, and
-                 * therefore cannot safely call printk() or anything else
+                 * Just note it happening - when we're woken, we can report
+                 * its occurrence.
                  */
-#ifdef DEBUG
-                printk("CPU%u: spurious wakeup call\n", cpu);
-#endif
+                (*spurious)++;
         }
 }
 
 int platform_cpu_kill(unsigned int cpu)
 {
-        return wait_for_completion_timeout(&cpu_killed, 5000);
+        return 1;
 }
 
 /*
@@ -105,30 +99,22 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-#ifdef DEBUG
-        unsigned int this_cpu = hard_smp_processor_id();
-
-        if (cpu != this_cpu) {
-                printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
-                           this_cpu, cpu);
-                BUG();
-        }
-#endif
-
-        printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
-        complete(&cpu_killed);
+        int spurious = 0;
 
         /*
          * we're ready for shutdown now, so do it
          */
         cpu_enter_lowpower();
-        platform_do_lowpower(cpu);
+        platform_do_lowpower(cpu, &spurious);
 
         /*
          * bring this CPU back into the world of cache
          * coherency, and then restore interrupts
          */
         cpu_leave_lowpower();
+
+        if (spurious)
+                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
 
 int platform_cpu_disable(unsigned int cpu)
diff --git a/arch/arm/mach-realview/include/mach/barriers.h b/arch/arm/mach-realview/include/mach/barriers.h
index 0c5d749d7b5f..9a732195aa1c 100644
--- a/arch/arm/mach-realview/include/mach/barriers.h
+++ b/arch/arm/mach-realview/include/mach/barriers.h
@@ -4,5 +4,5 @@
  * operation to deadlock the system.
  */
 #define mb()            dsb()
-#define rmb()           dmb()
+#define rmb()           dsb()
 #define wmb()           mb()
diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S
index 86622289b74e..90b687cbe04e 100644
--- a/arch/arm/mach-realview/include/mach/debug-macro.S
+++ b/arch/arm/mach-realview/include/mach/debug-macro.S
@@ -33,12 +33,10 @@
 #error "Unknown RealView platform"
 #endif
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx,      #0x10000000
-                movne   \rx,      #0xfb000000   @ virtual base
-                orr     \rx, \rx, #DEBUG_LL_UART_OFFSET
+                .macro  addruart, rp, rv
+                mov     \rp, #DEBUG_LL_UART_OFFSET
+                orr     \rv, \rp, #0xfb000000   @ virtual base
+                orr     \rp, \rp, #0x10000000   @ physical base
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
index 340a5c276946..4071164aebaa 100644
--- a/arch/arm/mach-realview/include/mach/entry-macro.S
+++ b/arch/arm/mach-realview/include/mach/entry-macro.S
@@ -8,74 +8,11 @@
  * warranty of any kind, whether express or implied.
  */
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
                 .macro  disable_fiq
                 .endm
 
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =gic_cpu_base_addr
-                ldr     \base, [\base]
-                .endm
-
                 .macro  arch_ret_to_user, tmp1, tmp2
                 .endm
 
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an interrupt if it's
-                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
-                ldr     \tmp, =1021
-
-                bic     \irqnr, \irqstat, #0x1c00
-
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-
-                .endm
-
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt on the
-                 * controller, since this requires the original irqstat value which
-                 * we won't easily be able to recreate later.
-                 */
-
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* As above, this assumes that irqstat and base are preserved.. */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
index 5dafc157b276..1759fa673eea 100644
--- a/arch/arm/mach-realview/include/mach/memory.h
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -24,18 +24,13 @@
  * Physical DRAM offset.
  */
 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
-#define PHYS_OFFSET             UL(0x70000000)
+#define PLAT_PHYS_OFFSET                UL(0x70000000)
 #else
-#define PHYS_OFFSET             UL(0x00000000)
+#define PLAT_PHYS_OFFSET                UL(0x00000000)
 #endif
 
-#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA)
-extern void realview_adjust_zones(unsigned long *size, unsigned long *hole);
-#define arch_adjust_zones(size, hole) \
-        realview_adjust_zones(size, hole)
-
-#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_256M - 1)
-#define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_256M)
+#ifdef CONFIG_ZONE_DMA
+#define ARM_DMA_ZONE_SIZE       SZ_256M
 #endif
 
 #ifdef CONFIG_SPARSEMEM
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
deleted file mode 100644
index dd53892d44a7..000000000000
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef ASMARM_ARCH_SMP_H
-#define ASMARM_ARCH_SMP_H
-
-
-#include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()                 \
-        ({                                              \
-                unsigned int cpunum;                    \
-                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
-                        : "=r" (cpunum));               \
-                cpunum &= 0x0F;                         \
-        })
-
-/*
- * We use IRQ1 as the IPI
- */
-static inline void smp_cross_call(const struct cpumask *mask)
-{
-        gic_raise_softirq(mask, 1);
-}
-
-#endif
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
deleted file mode 100644
index 60b4e111f459..000000000000
--- a/arch/arm/mach-realview/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  linux/arch/arm/mach-realview/localtimer.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-
-#include <asm/irq.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-}
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 009265818d55..963bf0d8119a 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -10,32 +10,22 @@
  */
 #include <linux/init.h>
 #include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 
-#include <asm/cacheflush.h>
 #include <mach/hardware.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
-#include <asm/localtimer.h>
+#include <asm/smp_scu.h>
 #include <asm/unified.h>
 
 #include <mach/board-eb.h>
 #include <mach/board-pb11mp.h>
 #include <mach/board-pbx.h>
-#include <asm/smp_scu.h>
 
 #include "core.h"
 
-extern void realview_secondary_startup(void);
-
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
+extern void versatile_secondary_startup(void);
 
 static void __iomem *scu_base_addr(void)
 {
@@ -50,134 +40,18 @@ static void __iomem *scu_base_addr(void)
                 return (void __iomem *)0;
 }
 
-static inline unsigned int get_core_count(void)
-{
-        void __iomem *scu_base = scu_base_addr();
-        if (scu_base)
-                return scu_get_core_count(scu_base);
-        return 1;
-}
-
-static DEFINE_SPINLOCK(boot_lock);
-
-void __cpuinit platform_secondary_init(unsigned int cpu)
-{
-        trace_hardirqs_off();
-
-        /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_cpu_init(0, gic_cpu_base_addr);
-
-        /*
-         * let the primary processor know we're out of the
-         * pen, then head off into the C entry point
-         */
-        pen_release = -1;
-        smp_wmb();
-
-        /*
-         * Synchronise with the boot thread.
-         */
-        spin_lock(&boot_lock);
-        spin_unlock(&boot_lock);
-}
-
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        unsigned long timeout;
-
-        /*
-         * set synchronisation state between this boot processor
-         * and the secondary one
-         */
-        spin_lock(&boot_lock);
-
-        /*
-         * The secondary processor is waiting to be released from
-         * the holding pen - release it, then wait for it to flag
-         * that it has been released by resetting pen_release.
-         *
-         * Note that "pen_release" is the hardware CPU ID, whereas
-         * "cpu" is Linux's internal ID.
-         */
-        pen_release = cpu;
-        flush_cache_all();
-
-        /*
-         * XXX
-         *
-         * This is a later addition to the booting protocol: the
-         * bootMonitor now puts secondary cores into WFI, so
-         * poke_milo() no longer gets the cores moving; we need
-         * to send a soft interrupt to wake the secondary core.
-         * Use smp_cross_call() for this, since there's little
-         * point duplicating the code here
-         */
-        smp_cross_call(cpumask_of(cpu));
-
-        timeout = jiffies + (1 * HZ);
-        while (time_before(jiffies, timeout)) {
-                smp_rmb();
-                if (pen_release == -1)
-                        break;
-
-                udelay(10);
-        }
-
-        /*
-         * now the secondary core is starting up let it run its
-         * calibrations, then wait for it to finish
-         */
-        spin_unlock(&boot_lock);
-
-        return pen_release != -1 ? -ENOSYS : 0;
-}
-
-static void __init poke_milo(void)
-{
-        /* nobody is to be released from the pen yet */
-        pen_release = -1;
-
-        /*
-         * Write the address of secondary startup into the system-wide flags
-         * register. The BootMonitor waits for this register to become
-         * non-zero.
-         */
-        __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
-                     __io_address(REALVIEW_SYS_FLAGSSET));
-
-        mb();
-}
-
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 void __init smp_init_cpus(void)
 {
-        unsigned int i, ncores = get_core_count();
+        void __iomem *scu_base = scu_base_addr();
+        unsigned int i, ncores;
 
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
-        unsigned int ncores = get_core_count();
-        unsigned int cpu = smp_processor_id();
-        int i;
+        ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
         /* sanity check */
-        if (ncores == 0) {
-                printk(KERN_ERR
-                       "Realview: strange CM count of 0? Default to 1\n");
-
-                ncores = 1;
-        }
-
         if (ncores > NR_CPUS) {
                 printk(KERN_WARNING
                        "Realview: no. of cores (%d) greater than configured "
@@ -186,13 +60,15 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                 ncores = NR_CPUS;
         }
 
-        smp_store_cpu_info(cpu);
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
 
-        /*
-         * are we trying to boot more cores than exist?
-         */
-        if (max_cpus > ncores)
-                max_cpus = ncores;
+        set_smp_cross_call(gic_raise_softirq);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
 
         /*
          * Initialise the present map, which describes the set of CPUs
@@ -201,21 +77,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
+        scu_enable(scu_base_addr());
+
         /*
-         * Initialise the SCU if there are more than one CPU and let
-         * them know where to start. Note that, on modern versions of
-         * MILO, the "poke" doesn't actually do anything until each
-         * individual core is sent a soft interrupt to get it out of
-         * WFI
+         * Write the address of secondary startup into the
+         * system-wide flags register. The BootMonitor waits
+         * until it receives a soft interrupt, and then the
+         * secondary CPU branches to this address.
          */
-        if (max_cpus > 1) {
-                /*
-                 * Enable the local timer or broadcast device for the
-                 * boot CPU, but only if we have more than one CPU.
-                 */
-                percpu_timer_setup();
-
-                scu_enable(scu_base_addr());
-                poke_milo();
-        }
+        __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
+                     __io_address(REALVIEW_SYS_FLAGSSET));
 }
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 991c1f8390e2..10e75faba4c9 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -144,60 +144,39 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  * These devices are connected via the core APB bridge
  */
 #define GPIO2_IRQ       { IRQ_EB_GPIO2, NO_IRQ }
-#define GPIO2_DMA       { 0, 0 }
 #define GPIO3_IRQ       { IRQ_EB_GPIO3, NO_IRQ }
-#define GPIO3_DMA       { 0, 0 }
 
 #define AACI_IRQ        { IRQ_EB_AACI, NO_IRQ }
-#define AACI_DMA        { 0x80, 0x81 }
 #define MMCI0_IRQ       { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
-#define MMCI0_DMA       { 0x84, 0 }
 #define KMI0_IRQ        { IRQ_EB_KMI0, NO_IRQ }
-#define KMI0_DMA        { 0, 0 }
 #define KMI1_IRQ        { IRQ_EB_KMI1, NO_IRQ }
-#define KMI1_DMA        { 0, 0 }
 
 /*
  * These devices are connected directly to the multi-layer AHB switch
  */
 #define EB_SMC_IRQ      { NO_IRQ, NO_IRQ }
-#define EB_SMC_DMA      { 0, 0 }
 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
-#define MPMC_DMA        { 0, 0 }
 #define EB_CLCD_IRQ     { IRQ_EB_CLCD, NO_IRQ }
-#define EB_CLCD_DMA     { 0, 0 }
 #define DMAC_IRQ        { IRQ_EB_DMA, NO_IRQ }
-#define DMAC_DMA        { 0, 0 }
 
 /*
  * These devices are connected via the core APB bridge
  */
 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
-#define SCTL_DMA        { 0, 0 }
 #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
-#define EB_WATCHDOG_DMA { 0, 0 }
 #define EB_GPIO0_IRQ    { IRQ_EB_GPIO0, NO_IRQ }
-#define EB_GPIO0_DMA    { 0, 0 }
 #define GPIO1_IRQ       { IRQ_EB_GPIO1, NO_IRQ }
-#define GPIO1_DMA       { 0, 0 }
 #define EB_RTC_IRQ      { IRQ_EB_RTC, NO_IRQ }
-#define EB_RTC_DMA      { 0, 0 }
 
 /*
  * These devices are connected via the DMA APB bridge
  */
 #define SCI_IRQ         { IRQ_EB_SCI, NO_IRQ }
-#define SCI_DMA         { 7, 6 }
 #define EB_UART0_IRQ    { IRQ_EB_UART0, NO_IRQ }
-#define EB_UART0_DMA    { 15, 14 }
 #define EB_UART1_IRQ    { IRQ_EB_UART1, NO_IRQ }
-#define EB_UART1_DMA    { 13, 12 }
 #define EB_UART2_IRQ    { IRQ_EB_UART2, NO_IRQ }
-#define EB_UART2_DMA    { 11, 10 }
 #define EB_UART3_IRQ    { IRQ_EB_UART3, NO_IRQ }
-#define EB_UART3_DMA    { 0x86, 0x87 }
 #define EB_SSP_IRQ      { IRQ_EB_SSP, NO_IRQ }
-#define EB_SSP_DMA      { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,  "fpga:aaci",  AACI,     NULL);
@@ -364,21 +343,19 @@ static void __init gic_init_irq(void)
                 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
 
                 /* core tile GIC, primary */
-                gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
-                gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
-                gic_cpu_init(0, gic_cpu_base_addr);
+                gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE),
+                         __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
 
 #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
                 /* board GIC, secondary */
-                gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
-                gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
+                gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE),
+                         __io_address(REALVIEW_EB_GIC_CPU_BASE));
                 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
 #endif
         } else {
                 /* board GIC, primary */
-                gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
-                gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
-                gic_cpu_init(0, gic_cpu_base_addr);
+                gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE),
+                         __io_address(REALVIEW_EB_GIC_CPU_BASE));
         }
 }
 
@@ -486,11 +463,10 @@ static void __init realview_eb_init(void)
 
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_EB_UART0_BASE & SECTION_MASK,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
-        .boot_params    = PHYS_OFFSET + 0x00000100,
+        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
         .fixup          = realview_fixup,
         .map_io         = realview_eb_map_io,
+        .init_early     = realview_init_early,
         .init_irq       = gic_init_irq,
         .timer          = &realview_eb_timer,
         .init_machine   = realview_eb_init,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d2be12eb829e..eab6070f66d0 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -134,47 +134,26 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  * RealView PB1176 AMBA devices
  */
 #define GPIO2_IRQ       { IRQ_PB1176_GPIO2, NO_IRQ }
-#define GPIO2_DMA       { 0, 0 }
 #define GPIO3_IRQ       { IRQ_PB1176_GPIO3, NO_IRQ }
-#define GPIO3_DMA       { 0, 0 }
 #define AACI_IRQ        { IRQ_PB1176_AACI, NO_IRQ }
-#define AACI_DMA        { 0x80, 0x81 }
 #define MMCI0_IRQ       { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
-#define MMCI0_DMA       { 0x84, 0 }
 #define KMI0_IRQ        { IRQ_PB1176_KMI0, NO_IRQ }
-#define KMI0_DMA        { 0, 0 }
 #define KMI1_IRQ        { IRQ_PB1176_KMI1, NO_IRQ }
-#define KMI1_DMA        { 0, 0 }
 #define PB1176_SMC_IRQ  { NO_IRQ, NO_IRQ }
-#define PB1176_SMC_DMA  { 0, 0 }
 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
-#define MPMC_DMA        { 0, 0 }
 #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
-#define PB1176_CLCD_DMA { 0, 0 }
 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
-#define SCTL_DMA        { 0, 0 }
 #define PB1176_WATCHDOG_IRQ     { IRQ_DC1176_WATCHDOG, NO_IRQ }
-#define PB1176_WATCHDOG_DMA     { 0, 0 }
 #define PB1176_GPIO0_IRQ        { IRQ_PB1176_GPIO0, NO_IRQ }
-#define PB1176_GPIO0_DMA        { 0, 0 }
 #define GPIO1_IRQ       { IRQ_PB1176_GPIO1, NO_IRQ }
-#define GPIO1_DMA       { 0, 0 }
 #define PB1176_RTC_IRQ  { IRQ_DC1176_RTC, NO_IRQ }
-#define PB1176_RTC_DMA  { 0, 0 }
 #define SCI_IRQ         { IRQ_PB1176_SCI, NO_IRQ }
-#define SCI_DMA         { 7, 6 }
 #define PB1176_UART0_IRQ        { IRQ_DC1176_UART0, NO_IRQ }
-#define PB1176_UART0_DMA        { 15, 14 }
 #define PB1176_UART1_IRQ        { IRQ_DC1176_UART1, NO_IRQ }
-#define PB1176_UART1_DMA        { 13, 12 }
 #define PB1176_UART2_IRQ        { IRQ_DC1176_UART2, NO_IRQ }
-#define PB1176_UART2_DMA        { 11, 10 }
 #define PB1176_UART3_IRQ        { IRQ_DC1176_UART3, NO_IRQ }
-#define PB1176_UART3_DMA        { 0x86, 0x87 }
 #define PB1176_UART4_IRQ        { IRQ_PB1176_UART4, NO_IRQ }
-#define PB1176_UART4_DMA        { 0, 0 }
 #define PB1176_SSP_IRQ          { IRQ_DC1176_SSP, NO_IRQ }
-#define PB1176_SSP_DMA          { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
@@ -304,13 +283,14 @@ static struct platform_device char_lcd_device = {
 static void __init gic_init_irq(void)
 {
         /* ARM1176 DevChip GIC, primary */
-        gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
-        gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START);
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_init(0, IRQ_DC1176_GIC_START,
+                 __io_address(REALVIEW_DC1176_GIC_DIST_BASE),
+                 __io_address(REALVIEW_DC1176_GIC_CPU_BASE));
 
         /* board GIC, secondary */
-        gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START);
-        gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
+        gic_init(1, IRQ_PB1176_GIC_START,
+                 __io_address(REALVIEW_PB1176_GIC_DIST_BASE),
+                 __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
         gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
 }
 
@@ -378,11 +358,10 @@ static void __init realview_pb1176_init(void)
 
 MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_PB1176_UART0_BASE & SECTION_MASK,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc,
-        .boot_params    = PHYS_OFFSET + 0x00000100,
+        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
         .fixup          = realview_pb1176_fixup,
         .map_io         = realview_pb1176_map_io,
+        .init_early     = realview_init_early,
         .init_irq       = gic_init_irq,
         .timer          = &realview_pb1176_timer,
         .init_machine   = realview_pb1176_init,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index d591bc00b86e..b2985fc7cd4e 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -136,47 +136,26 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  */
 
 #define GPIO2_IRQ               { IRQ_PB11MP_GPIO2, NO_IRQ }
-#define GPIO2_DMA               { 0, 0 }
 #define GPIO3_IRQ               { IRQ_PB11MP_GPIO3, NO_IRQ }
-#define GPIO3_DMA               { 0, 0 }
 #define AACI_IRQ                { IRQ_TC11MP_AACI, NO_IRQ }
-#define AACI_DMA                { 0x80, 0x81 }
 #define MMCI0_IRQ               { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
-#define MMCI0_DMA               { 0x84, 0 }
 #define KMI0_IRQ                { IRQ_TC11MP_KMI0, NO_IRQ }
-#define KMI0_DMA                { 0, 0 }
 #define KMI1_IRQ                { IRQ_TC11MP_KMI1, NO_IRQ }
-#define KMI1_DMA                { 0, 0 }
 #define PB11MP_SMC_IRQ          { NO_IRQ, NO_IRQ }
-#define PB11MP_SMC_DMA          { 0, 0 }
 #define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define MPMC_DMA                { 0, 0 }
 #define PB11MP_CLCD_IRQ         { IRQ_PB11MP_CLCD, NO_IRQ }
-#define PB11MP_CLCD_DMA         { 0, 0 }
 #define DMAC_IRQ                { IRQ_PB11MP_DMAC, NO_IRQ }
-#define DMAC_DMA                { 0, 0 }
 #define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define SCTL_DMA                { 0, 0 }
 #define PB11MP_WATCHDOG_IRQ     { IRQ_PB11MP_WATCHDOG, NO_IRQ }
-#define PB11MP_WATCHDOG_DMA     { 0, 0 }
 #define PB11MP_GPIO0_IRQ        { IRQ_PB11MP_GPIO0, NO_IRQ }
-#define PB11MP_GPIO0_DMA        { 0, 0 }
 #define GPIO1_IRQ               { IRQ_PB11MP_GPIO1, NO_IRQ }
-#define GPIO1_DMA               { 0, 0 }
 #define PB11MP_RTC_IRQ          { IRQ_TC11MP_RTC, NO_IRQ }
-#define PB11MP_RTC_DMA          { 0, 0 }
 #define SCI_IRQ                 { IRQ_PB11MP_SCI, NO_IRQ }
-#define SCI_DMA                 { 7, 6 }
 #define PB11MP_UART0_IRQ        { IRQ_TC11MP_UART0, NO_IRQ }
-#define PB11MP_UART0_DMA        { 15, 14 }
 #define PB11MP_UART1_IRQ        { IRQ_TC11MP_UART1, NO_IRQ }
-#define PB11MP_UART1_DMA        { 13, 12 }
 #define PB11MP_UART2_IRQ        { IRQ_PB11MP_UART2, NO_IRQ }
-#define PB11MP_UART2_DMA        { 11, 10 }
 #define PB11MP_UART3_IRQ        { IRQ_PB11MP_UART3, NO_IRQ }
-#define PB11MP_UART3_DMA        { 0x86, 0x87 }
 #define PB11MP_SSP_IRQ          { IRQ_PB11MP_SSP, NO_IRQ }
-#define PB11MP_SSP_DMA          { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
@@ -309,13 +288,13 @@ static void __init gic_init_irq(void)
         writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
 
         /* ARM11MPCore test chip GIC, primary */
-        gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
-        gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29);
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
+                 __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
 
         /* board GIC, secondary */
-        gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START);
-        gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
+        gic_init(1, IRQ_PB11MP_GIC_START,
+                 __io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
+                 __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
         gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
 }
 
@@ -381,11 +360,10 @@ static void __init realview_pb11mp_init(void)
 
 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_PB11MP_UART0_BASE & SECTION_MASK,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
-        .boot_params    = PHYS_OFFSET + 0x00000100,
+        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
         .fixup          = realview_fixup,
         .map_io         = realview_pb11mp_map_io,
+        .init_early     = realview_init_early,
         .init_irq       = gic_init_irq,
         .timer          = &realview_pb11mp_timer,
         .init_machine   = realview_pb11mp_init,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 6c37621217bc..fb6866558760 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -126,47 +126,26 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  */
 
 #define GPIO2_IRQ               { IRQ_PBA8_GPIO2, NO_IRQ }
-#define GPIO2_DMA               { 0, 0 }
 #define GPIO3_IRQ               { IRQ_PBA8_GPIO3, NO_IRQ }
-#define GPIO3_DMA               { 0, 0 }
 #define AACI_IRQ                { IRQ_PBA8_AACI, NO_IRQ }
-#define AACI_DMA                { 0x80, 0x81 }
 #define MMCI0_IRQ               { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B }
-#define MMCI0_DMA               { 0x84, 0 }
 #define KMI0_IRQ                { IRQ_PBA8_KMI0, NO_IRQ }
-#define KMI0_DMA                { 0, 0 }
 #define KMI1_IRQ                { IRQ_PBA8_KMI1, NO_IRQ }
-#define KMI1_DMA                { 0, 0 }
 #define PBA8_SMC_IRQ            { NO_IRQ, NO_IRQ }
-#define PBA8_SMC_DMA            { 0, 0 }
 #define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define MPMC_DMA                { 0, 0 }
 #define PBA8_CLCD_IRQ           { IRQ_PBA8_CLCD, NO_IRQ }
-#define PBA8_CLCD_DMA           { 0, 0 }
 #define DMAC_IRQ                { IRQ_PBA8_DMAC, NO_IRQ }
-#define DMAC_DMA                { 0, 0 }
 #define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define SCTL_DMA                { 0, 0 }
 #define PBA8_WATCHDOG_IRQ       { IRQ_PBA8_WATCHDOG, NO_IRQ }
-#define PBA8_WATCHDOG_DMA       { 0, 0 }
 #define PBA8_GPIO0_IRQ          { IRQ_PBA8_GPIO0, NO_IRQ }
-#define PBA8_GPIO0_DMA          { 0, 0 }
 #define GPIO1_IRQ               { IRQ_PBA8_GPIO1, NO_IRQ }
-#define GPIO1_DMA               { 0, 0 }
 #define PBA8_RTC_IRQ            { IRQ_PBA8_RTC, NO_IRQ }
-#define PBA8_RTC_DMA            { 0, 0 }
 #define SCI_IRQ                 { IRQ_PBA8_SCI, NO_IRQ }
-#define SCI_DMA                 { 7, 6 }
 #define PBA8_UART0_IRQ          { IRQ_PBA8_UART0, NO_IRQ }
-#define PBA8_UART0_DMA          { 15, 14 }
 #define PBA8_UART1_IRQ          { IRQ_PBA8_UART1, NO_IRQ }
-#define PBA8_UART1_DMA          { 13, 12 }
 #define PBA8_UART2_IRQ          { IRQ_PBA8_UART2, NO_IRQ }
-#define PBA8_UART2_DMA          { 11, 10 }
 #define PBA8_UART3_IRQ          { IRQ_PBA8_UART3, NO_IRQ }
-#define PBA8_UART3_DMA          { 0x86, 0x87 }
 #define PBA8_SSP_IRQ            { IRQ_PBA8_SSP, NO_IRQ }
-#define PBA8_SSP_DMA            { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
@@ -273,9 +252,9 @@ static struct platform_device pmu_device = {
 static void __init gic_init_irq(void)
 {
         /* ARM PB-A8 on-board GIC */
-        gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE);
-        gic_dist_init(0, __io_address(REALVIEW_PBA8_GIC_DIST_BASE), IRQ_PBA8_GIC_START);
-        gic_cpu_init(0, __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
+        gic_init(0, IRQ_PBA8_GIC_START,
+                 __io_address(REALVIEW_PBA8_GIC_DIST_BASE),
+                 __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
 }
 
 static void __init realview_pba8_timer_init(void)
@@ -331,11 +310,10 @@ static void __init realview_pba8_init(void)
 
 MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_PBA8_UART0_BASE & SECTION_MASK,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PBA8_UART0_BASE) >> 18) & 0xfffc,
-        .boot_params    = PHYS_OFFSET + 0x00000100,
+        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
         .fixup          = realview_fixup,
         .map_io         = realview_pba8_map_io,
+        .init_early     = realview_init_early,
         .init_irq       = gic_init_irq,
         .timer          = &realview_pba8_timer,
         .init_machine   = realview_pba8_init,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 9428eff0b116..92ace2cf2b2c 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -148,47 +148,26 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  */
 
 #define GPIO2_IRQ               { IRQ_PBX_GPIO2, NO_IRQ }
-#define GPIO2_DMA               { 0, 0 }
 #define GPIO3_IRQ               { IRQ_PBX_GPIO3, NO_IRQ }
-#define GPIO3_DMA               { 0, 0 }
 #define AACI_IRQ                { IRQ_PBX_AACI, NO_IRQ }
-#define AACI_DMA                { 0x80, 0x81 }
 #define MMCI0_IRQ               { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
-#define MMCI0_DMA               { 0x84, 0 }
 #define KMI0_IRQ                { IRQ_PBX_KMI0, NO_IRQ }
-#define KMI0_DMA                { 0, 0 }
 #define KMI1_IRQ                { IRQ_PBX_KMI1, NO_IRQ }
-#define KMI1_DMA                { 0, 0 }
 #define PBX_SMC_IRQ             { NO_IRQ, NO_IRQ }
-#define PBX_SMC_DMA             { 0, 0 }
 #define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define MPMC_DMA                { 0, 0 }
 #define PBX_CLCD_IRQ            { IRQ_PBX_CLCD, NO_IRQ }
-#define PBX_CLCD_DMA            { 0, 0 }
 #define DMAC_IRQ                { IRQ_PBX_DMAC, NO_IRQ }
-#define DMAC_DMA                { 0, 0 }
 #define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define SCTL_DMA                { 0, 0 }
 #define PBX_WATCHDOG_IRQ        { IRQ_PBX_WATCHDOG, NO_IRQ }
-#define PBX_WATCHDOG_DMA        { 0, 0 }
 #define PBX_GPIO0_IRQ           { IRQ_PBX_GPIO0, NO_IRQ }
-#define PBX_GPIO0_DMA           { 0, 0 }
 #define GPIO1_IRQ               { IRQ_PBX_GPIO1, NO_IRQ }
-#define GPIO1_DMA               { 0, 0 }
 #define PBX_RTC_IRQ             { IRQ_PBX_RTC, NO_IRQ }
-#define PBX_RTC_DMA             { 0, 0 }
 #define SCI_IRQ                 { IRQ_PBX_SCI, NO_IRQ }
-#define SCI_DMA                 { 7, 6 }
 #define PBX_UART0_IRQ           { IRQ_PBX_UART0, NO_IRQ }
-#define PBX_UART0_DMA           { 15, 14 }
 #define PBX_UART1_IRQ           { IRQ_PBX_UART1, NO_IRQ }
-#define PBX_UART1_DMA           { 13, 12 }
 #define PBX_UART2_IRQ           { IRQ_PBX_UART2, NO_IRQ }
-#define PBX_UART2_DMA           { 11, 10 }
 #define PBX_UART3_IRQ           { IRQ_PBX_UART3, NO_IRQ }
-#define PBX_UART3_DMA           { 0x86, 0x87 }
 #define PBX_SSP_IRQ             { IRQ_PBX_SSP, NO_IRQ }
-#define PBX_SSP_DMA             { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
@@ -313,15 +292,12 @@ static void __init gic_init_irq(void)
 {
         /* ARM PBX on-board GIC */
         if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
-                gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE);
-                gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
-                              29);
-                gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
+                gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
+                         __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
         } else {
-                gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE);
-                gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE),
-                              IRQ_PBX_GIC_START);
-                gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE));
+                gic_init(0, IRQ_PBX_GIC_START,
+                         __io_address(REALVIEW_PBX_GIC_DIST_BASE),
+                         __io_address(REALVIEW_PBX_GIC_CPU_BASE));
         }
 }
 
@@ -417,11 +393,10 @@ static void __init realview_pbx_init(void)
 
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_PBX_UART0_BASE & SECTION_MASK,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PBX_UART0_BASE) >> 18) & 0xfffc,
-        .boot_params    = PHYS_OFFSET + 0x00000100,
+        .boot_params    = PLAT_PHYS_OFFSET + 0x00000100,
         .fixup          = realview_pbx_fixup,
         .map_io         = realview_pbx_map_io,
+        .init_early     = realview_init_early,
         .init_irq       = gic_init_irq,
         .timer          = &realview_pbx_timer,
         .init_machine   = realview_pbx_init,